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CHG: TI code did have the tickstimer started.
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 #ifndef SHORT_COIL
23 # define SHORT_COIL() LOW(GPIO_SSC_DOUT)
24 #endif
25 #ifndef OPEN_COIL
26 # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
27 #endif
28
29 /**
30 * Function to do a modulation and then get samples.
31 * @param delay_off
32 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
33 * @param useHighFreg
34 * @param command
35 */
36 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
37 {
38 /* Make sure the tag is reset */
39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
41 SpinDelay(200);
42
43 uint16_t period_0 = periods >> 16;
44 uint16_t period_1 = periods & 0xFFFF;
45
46 // 95 == 125 KHz 88 == 124.8 KHz
47 int divisor_used = (useHighFreq) ? 88 : 95;
48 sample_config sc = { 0,0,1, divisor_used, 0};
49 setSamplingConfig(&sc);
50
51 //clear read buffer
52 BigBuf_Clear_keep_EM();
53
54 LFSetupFPGAForADC(sc.divisor, 1);
55
56 // And a little more time for the tag to fully power up
57 SpinDelay(50);
58
59 // now modulate the reader field
60 while(*command != '\0' && *command != ' ') {
61 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
62 LED_D_OFF();
63 WaitUS(delay_off);
64 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
65
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
67 LED_D_ON();
68 if(*(command++) == '0')
69 WaitUS(period_0);
70 else
71 WaitUS(period_1);
72 }
73 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
74 LED_D_OFF();
75 WaitUS(delay_off);
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
78
79 // now do the read
80 DoAcquisition_config(false);
81 }
82
83 /* blank r/w tag data stream
84 ...0000000000000000 01111111
85 1010101010101010101010101010101010101010101010101010101010101010
86 0011010010100001
87 01111111
88 101010101010101[0]000...
89
90 [5555fe852c5555555555555555fe0000]
91 */
92 void ReadTItag(void)
93 {
94 StartTicks();
95 // some hardcoded initial params
96 // when we read a TI tag we sample the zerocross line at 2Mhz
97 // TI tags modulate a 1 as 16 cycles of 123.2Khz
98 // TI tags modulate a 0 as 16 cycles of 134.2Khz
99 #define FSAMPLE 2000000
100 #define FREQLO 123200
101 #define FREQHI 134200
102
103 signed char *dest = (signed char *)BigBuf_get_addr();
104 uint16_t n = BigBuf_max_traceLen();
105 // 128 bit shift register [shift3:shift2:shift1:shift0]
106 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
107
108 int i, cycles=0, samples=0;
109 // how many sample points fit in 16 cycles of each frequency
110 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
111 // when to tell if we're close enough to one freq or another
112 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
113
114 // TI tags charge at 134.2Khz
115 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
117
118 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
119 // connects to SSP_DIN and the SSP_DOUT logic level controls
120 // whether we're modulating the antenna (high)
121 // or listening to the antenna (low)
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
123
124 // get TI tag data into the buffer
125 AcquireTiType();
126
127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
128
129 for (i=0; i<n-1; i++) {
130 // count cycles by looking for lo to hi zero crossings
131 if ( (dest[i]<0) && (dest[i+1]>0) ) {
132 cycles++;
133 // after 16 cycles, measure the frequency
134 if (cycles>15) {
135 cycles=0;
136 samples=i-samples; // number of samples in these 16 cycles
137
138 // TI bits are coming to us lsb first so shift them
139 // right through our 128 bit right shift register
140 shift0 = (shift0>>1) | (shift1 << 31);
141 shift1 = (shift1>>1) | (shift2 << 31);
142 shift2 = (shift2>>1) | (shift3 << 31);
143 shift3 >>= 1;
144
145 // check if the cycles fall close to the number
146 // expected for either the low or high frequency
147 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
148 // low frequency represents a 1
149 shift3 |= (1<<31);
150 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
151 // high frequency represents a 0
152 } else {
153 // probably detected a gay waveform or noise
154 // use this as gaydar or discard shift register and start again
155 shift3 = shift2 = shift1 = shift0 = 0;
156 }
157 samples = i;
158
159 // for each bit we receive, test if we've detected a valid tag
160
161 // if we see 17 zeroes followed by 6 ones, we might have a tag
162 // remember the bits are backwards
163 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
164 // if start and end bytes match, we have a tag so break out of the loop
165 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
166 cycles = 0xF0B; //use this as a flag (ugly but whatever)
167 break;
168 }
169 }
170 }
171 }
172 }
173
174 // if flag is set we have a tag
175 if (cycles!=0xF0B) {
176 DbpString("Info: No valid tag detected.");
177 } else {
178 // put 64 bit data into shift1 and shift0
179 shift0 = (shift0>>24) | (shift1 << 8);
180 shift1 = (shift1>>24) | (shift2 << 8);
181
182 // align 16 bit crc into lower half of shift2
183 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
184
185 // if r/w tag, check ident match
186 if (shift3 & (1<<15) ) {
187 DbpString("Info: TI tag is rewriteable");
188 // only 15 bits compare, last bit of ident is not valid
189 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
190 DbpString("Error: Ident mismatch!");
191 } else {
192 DbpString("Info: TI tag ident is valid");
193 }
194 } else {
195 DbpString("Info: TI tag is readonly");
196 }
197
198 // WARNING the order of the bytes in which we calc crc below needs checking
199 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
200 // bytes in reverse or something
201 // calculate CRC
202 uint32_t crc=0;
203
204 crc = update_crc16(crc, (shift0)&0xff);
205 crc = update_crc16(crc, (shift0>>8)&0xff);
206 crc = update_crc16(crc, (shift0>>16)&0xff);
207 crc = update_crc16(crc, (shift0>>24)&0xff);
208 crc = update_crc16(crc, (shift1)&0xff);
209 crc = update_crc16(crc, (shift1>>8)&0xff);
210 crc = update_crc16(crc, (shift1>>16)&0xff);
211 crc = update_crc16(crc, (shift1>>24)&0xff);
212
213 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
214 if (crc != (shift2&0xffff)) {
215 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
216 } else {
217 DbpString("Info: CRC is good");
218 }
219 }
220 StopTicks();
221 }
222
223 void WriteTIbyte(uint8_t b)
224 {
225 int i = 0;
226
227 // modulate 8 bits out to the antenna
228 for (i=0; i<8; i++)
229 {
230 if ( b & ( 1 << i ) ) {
231 // stop modulating antenna 1ms
232 LOW(GPIO_SSC_DOUT);
233 WaitUS(1000);
234 // modulate antenna 1ms
235 HIGH(GPIO_SSC_DOUT);
236 WaitUS(1000);
237 } else {
238 // stop modulating antenna 1ms
239 LOW(GPIO_SSC_DOUT);
240 WaitUS(300);
241 // modulate antenna 1m
242 HIGH(GPIO_SSC_DOUT);
243 WaitUS(1700);
244 }
245 }
246 }
247
248 void AcquireTiType(void)
249 {
250 int i, j, n;
251 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
252 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
253 #define TIBUFLEN 1250
254
255 // clear buffer
256 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
257
258 //clear buffer now so it does not interfere with timing later
259 BigBuf_Clear_ext(false);
260
261 // Set up the synchronous serial port
262 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
263 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
264
265 // steal this pin from the SSP and use it to control the modulation
266 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
267 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
268
269 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
270 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
271
272 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
273 // 48/2 = 24 MHz clock must be divided by 12
274 AT91C_BASE_SSC->SSC_CMR = 12;
275
276 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
277 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
278 AT91C_BASE_SSC->SSC_TCMR = 0;
279 AT91C_BASE_SSC->SSC_TFMR = 0;
280 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
281 LED_D_ON();
282
283 // modulate antenna
284 HIGH(GPIO_SSC_DOUT);
285
286 // Charge TI tag for 50ms.
287 WaitMS(50);
288
289 // stop modulating antenna and listen
290 LOW(GPIO_SSC_DOUT);
291
292 LED_D_OFF();
293
294 i = 0;
295 for(;;) {
296 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
297 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
298 i++; if(i >= TIBUFLEN) break;
299 }
300 WDT_HIT();
301 }
302
303 // return stolen pin to SSP
304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
306
307 char *dest = (char *)BigBuf_get_addr();
308 n = TIBUFLEN * 32;
309
310 // unpack buffer
311 for (i = TIBUFLEN-1; i >= 0; i--) {
312 for (j = 0; j < 32; j++) {
313 if(buf[i] & (1 << j)) {
314 dest[--n] = 1;
315 } else {
316 dest[--n] = -1;
317 }
318 }
319 }
320 }
321
322 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
323 // if crc provided, it will be written with the data verbatim (even if bogus)
324 // if not provided a valid crc will be computed from the data and written.
325 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
326 {
327 StartTicks();
328 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
329 if(crc == 0) {
330 crc = update_crc16(crc, (idlo)&0xff);
331 crc = update_crc16(crc, (idlo>>8)&0xff);
332 crc = update_crc16(crc, (idlo>>16)&0xff);
333 crc = update_crc16(crc, (idlo>>24)&0xff);
334 crc = update_crc16(crc, (idhi)&0xff);
335 crc = update_crc16(crc, (idhi>>8)&0xff);
336 crc = update_crc16(crc, (idhi>>16)&0xff);
337 crc = update_crc16(crc, (idhi>>24)&0xff);
338 }
339 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
340
341 // TI tags charge at 134.2Khz
342 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
343 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
344 // connects to SSP_DIN and the SSP_DOUT logic level controls
345 // whether we're modulating the antenna (high)
346 // or listening to the antenna (low)
347 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
348 LED_A_ON();
349
350 // steal this pin from the SSP and use it to control the modulation
351 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
352 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
353
354 // writing algorithm:
355 // a high bit consists of a field off for 1ms and field on for 1ms
356 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
357 // initiate a charge time of 50ms (field on) then immediately start writing bits
358 // start by writing 0xBB (keyword) and 0xEB (password)
359 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
360 // finally end with 0x0300 (write frame)
361 // all data is sent lsb first
362 // finish with 15ms programming time
363
364 // modulate antenna
365 HIGH(GPIO_SSC_DOUT);
366 WaitMS(50); // charge time
367
368 WriteTIbyte(0xbb); // keyword
369 WriteTIbyte(0xeb); // password
370 WriteTIbyte( (idlo )&0xff );
371 WriteTIbyte( (idlo>>8 )&0xff );
372 WriteTIbyte( (idlo>>16)&0xff );
373 WriteTIbyte( (idlo>>24)&0xff );
374 WriteTIbyte( (idhi )&0xff );
375 WriteTIbyte( (idhi>>8 )&0xff );
376 WriteTIbyte( (idhi>>16)&0xff );
377 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
378 WriteTIbyte( (crc )&0xff ); // crc lo
379 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
380 WriteTIbyte(0x00); // write frame lo
381 WriteTIbyte(0x03); // write frame hi
382 HIGH(GPIO_SSC_DOUT);
383 WaitMS(50); // programming time
384
385 LED_A_OFF();
386
387 // get TI tag data into the buffer
388 AcquireTiType();
389
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
391 DbpString("Now use `lf ti read` to check");
392 StopTicks();
393 }
394
395 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
396 {
397 int i = 0;
398 uint8_t *tab = BigBuf_get_addr();
399
400 StartTicks();
401
402 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
403
404 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
405 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
406 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
407
408 for(;;) {
409 WDT_HIT();
410
411 if (ledcontrol) LED_D_ON();
412
413 //wait until SSC_CLK goes HIGH
414 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
415 WDT_HIT();
416 if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
417 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
418 LED_D_OFF();
419 return;
420 }
421 }
422
423 if(tab[i])
424 OPEN_COIL();
425 else
426 SHORT_COIL();
427
428 if (ledcontrol) LED_D_OFF();
429
430 //wait until SSC_CLK goes LOW
431 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
432 WDT_HIT();
433 if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
434 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
435 LED_D_OFF();
436 return;
437 }
438 }
439
440 i++;
441 if(i == period) {
442 i = 0;
443 if (gap) {
444 WDT_HIT();
445 SHORT_COIL();
446 WaitUS(gap);
447 }
448 }
449 }
450 StopTicks();
451 }
452
453 #define DEBUG_FRAME_CONTENTS 1
454 void SimulateTagLowFrequencyBidir(int divisor, int t0)
455 {
456 }
457
458 // compose fc/8 fc/10 waveform (FSK2)
459 static void fc(int c, int *n)
460 {
461 uint8_t *dest = BigBuf_get_addr();
462 int idx;
463
464 // for when we want an fc8 pattern every 4 logical bits
465 if(c==0) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475
476 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
477 if(c==8) {
478 for (idx=0; idx<6; idx++) {
479 dest[((*n)++)]=1;
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=0;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 }
488 }
489
490 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
491 if(c==10) {
492 for (idx=0; idx<5; idx++) {
493 dest[((*n)++)]=1;
494 dest[((*n)++)]=1;
495 dest[((*n)++)]=1;
496 dest[((*n)++)]=1;
497 dest[((*n)++)]=1;
498 dest[((*n)++)]=0;
499 dest[((*n)++)]=0;
500 dest[((*n)++)]=0;
501 dest[((*n)++)]=0;
502 dest[((*n)++)]=0;
503 }
504 }
505 }
506 // compose fc/X fc/Y waveform (FSKx)
507 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
508 {
509 uint8_t *dest = BigBuf_get_addr();
510 uint8_t halfFC = fc/2;
511 uint8_t wavesPerClock = clock/fc;
512 uint8_t mod = clock % fc; //modifier
513 uint8_t modAdj = fc/mod; //how often to apply modifier
514 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
515 // loop through clock - step field clock
516 for (uint8_t idx=0; idx < wavesPerClock; idx++){
517 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
518 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
519 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
520 *n += fc;
521 }
522 if (mod>0) (*modCnt)++;
523 if ((mod>0) && modAdjOk){ //fsk2
524 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
525 memset(dest+(*n), 0, fc-halfFC);
526 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
527 *n += fc;
528 }
529 }
530 if (mod>0 && !modAdjOk){ //fsk1
531 memset(dest+(*n), 0, mod-(mod/2));
532 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
533 *n += mod;
534 }
535 }
536
537 // prepare a waveform pattern in the buffer based on the ID given then
538 // simulate a HID tag until the button is pressed
539 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
540 {
541 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
542 set_tracing(FALSE);
543
544 int n = 0, i = 0;
545 /*
546 HID tag bitstream format
547 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
548 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
549 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
550 A fc8 is inserted before every 4 bits
551 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
552 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
553 */
554
555 if (hi > 0xFFF) {
556 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
557 return;
558 }
559 fc(0,&n);
560 // special start of frame marker containing invalid bit sequences
561 fc(8, &n); fc(8, &n); // invalid
562 fc(8, &n); fc(10, &n); // logical 0
563 fc(10, &n); fc(10, &n); // invalid
564 fc(8, &n); fc(10, &n); // logical 0
565
566 WDT_HIT();
567 // manchester encode bits 43 to 32
568 for (i=11; i>=0; i--) {
569 if ((i%4)==3) fc(0,&n);
570 if ((hi>>i)&1) {
571 fc(10, &n); fc(8, &n); // low-high transition
572 } else {
573 fc(8, &n); fc(10, &n); // high-low transition
574 }
575 }
576
577 WDT_HIT();
578 // manchester encode bits 31 to 0
579 for (i=31; i>=0; i--) {
580 if ((i%4)==3) fc(0,&n);
581 if ((lo>>i)&1) {
582 fc(10, &n); fc(8, &n); // low-high transition
583 } else {
584 fc(8, &n); fc(10, &n); // high-low transition
585 }
586 }
587 WDT_HIT();
588
589 if (ledcontrol) LED_A_ON();
590 SimulateTagLowFrequency(n, 0, ledcontrol);
591 if (ledcontrol) LED_A_OFF();
592 }
593
594 // prepare a waveform pattern in the buffer based on the ID given then
595 // simulate a FSK tag until the button is pressed
596 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
597 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
598 {
599 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
600
601 // free eventually allocated BigBuf memory
602 BigBuf_free(); BigBuf_Clear_ext(false);
603 clear_trace();
604 set_tracing(FALSE);
605
606 int ledcontrol = 1, n = 0, i = 0;
607 uint8_t fcHigh = arg1 >> 8;
608 uint8_t fcLow = arg1 & 0xFF;
609 uint16_t modCnt = 0;
610 uint8_t clk = arg2 & 0xFF;
611 uint8_t invert = (arg2 >> 8) & 1;
612
613 for (i=0; i<size; i++){
614
615 if (BitStream[i] == invert)
616 fcAll(fcLow, &n, clk, &modCnt);
617 else
618 fcAll(fcHigh, &n, clk, &modCnt);
619 }
620 WDT_HIT();
621
622 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
623
624 if (ledcontrol) LED_A_ON();
625 SimulateTagLowFrequency(n, 0, ledcontrol);
626 if (ledcontrol) LED_A_OFF();
627 }
628
629 // compose ask waveform for one bit(ASK)
630 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
631 {
632 uint8_t *dest = BigBuf_get_addr();
633 uint8_t halfClk = clock/2;
634 // c = current bit 1 or 0
635 if (manchester==1){
636 memset(dest+(*n), c, halfClk);
637 memset(dest+(*n) + halfClk, c^1, halfClk);
638 } else {
639 memset(dest+(*n), c, clock);
640 }
641 *n += clock;
642 }
643
644 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
645 {
646 uint8_t *dest = BigBuf_get_addr();
647 uint8_t halfClk = clock/2;
648 if (c){
649 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
650 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
651 } else {
652 memset(dest+(*n), c ^ *phase, clock);
653 *phase ^= 1;
654 }
655 *n += clock;
656 }
657
658 static void stAskSimBit(int *n, uint8_t clock) {
659 uint8_t *dest = BigBuf_get_addr();
660 uint8_t halfClk = clock/2;
661 //ST = .5 high .5 low 1.5 high .5 low 1 high
662 memset(dest+(*n), 1, halfClk);
663 memset(dest+(*n) + halfClk, 0, halfClk);
664 memset(dest+(*n) + clock, 1, clock + halfClk);
665 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
666 memset(dest+(*n) + clock*3, 1, clock);
667 *n += clock*4;
668 }
669
670 // args clock, ask/man or askraw, invert, transmission separator
671 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
672 {
673 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
674 set_tracing(FALSE);
675
676 int ledcontrol = 1, n = 0, i = 0;
677 uint8_t clk = (arg1 >> 8) & 0xFF;
678 uint8_t encoding = arg1 & 0xFF;
679 uint8_t separator = arg2 & 1;
680 uint8_t invert = (arg2 >> 8) & 1;
681
682 if (encoding == 2){ //biphase
683 uint8_t phase = 0;
684 for (i=0; i<size; i++){
685 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
686 }
687 if (phase == 1) { //run a second set inverted to keep phase in check
688 for (i=0; i<size; i++){
689 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
690 }
691 }
692 } else { // ask/manchester || ask/raw
693 for (i=0; i<size; i++){
694 askSimBit(BitStream[i]^invert, &n, clk, encoding);
695 }
696 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
697 for (i=0; i<size; i++){
698 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
699 }
700 }
701 }
702 if (separator==1 && encoding == 1)
703 stAskSimBit(&n, clk);
704 else if (separator==1)
705 Dbprintf("sorry but separator option not yet available");
706
707 WDT_HIT();
708
709 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
710
711 if (ledcontrol) LED_A_ON();
712 SimulateTagLowFrequency(n, 0, ledcontrol);
713 if (ledcontrol) LED_A_OFF();
714 }
715
716 //carrier can be 2,4 or 8
717 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
718 {
719 uint8_t *dest = BigBuf_get_addr();
720 uint8_t halfWave = waveLen/2;
721 //uint8_t idx;
722 int i = 0;
723 if (phaseChg){
724 // write phase change
725 memset(dest+(*n), *curPhase^1, halfWave);
726 memset(dest+(*n) + halfWave, *curPhase, halfWave);
727 *n += waveLen;
728 *curPhase ^= 1;
729 i += waveLen;
730 }
731 //write each normal clock wave for the clock duration
732 for (; i < clk; i+=waveLen){
733 memset(dest+(*n), *curPhase, halfWave);
734 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
735 *n += waveLen;
736 }
737 }
738
739 // args clock, carrier, invert,
740 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
741 {
742 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
743 set_tracing(FALSE);
744
745 int ledcontrol = 1, n = 0, i = 0;
746 uint8_t clk = arg1 >> 8;
747 uint8_t carrier = arg1 & 0xFF;
748 uint8_t invert = arg2 & 0xFF;
749 uint8_t curPhase = 0;
750 for (i=0; i<size; i++){
751 if (BitStream[i] == curPhase){
752 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
753 } else {
754 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
755 }
756 }
757
758 WDT_HIT();
759
760 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
761
762 if (ledcontrol) LED_A_ON();
763 SimulateTagLowFrequency(n, 0, ledcontrol);
764 if (ledcontrol) LED_A_OFF();
765 }
766
767 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
768 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
769 {
770 uint8_t *dest = BigBuf_get_addr();
771 size_t size = 0;
772 uint32_t hi2=0, hi=0, lo=0;
773 int idx=0;
774 // Configure to go in 125Khz listen mode
775 LFSetupFPGAForADC(95, true);
776
777 //clear read buffer
778 BigBuf_Clear_keep_EM();
779
780 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
781
782 WDT_HIT();
783 if (ledcontrol) LED_A_ON();
784
785 DoAcquisition_default(-1,true);
786 // FSK demodulator
787 size = 50*128*2; //big enough to catch 2 sequences of largest format
788 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
789
790 if (idx>0 && lo>0 && (size==96 || size==192)){
791 // go over previously decoded manchester data and decode into usable tag ID
792 if (hi2 != 0){ //extra large HID tags 88/192 bits
793 Dbprintf("TAG ID: %x%08x%08x (%d)",
794 (unsigned int) hi2,
795 (unsigned int) hi,
796 (unsigned int) lo,
797 (unsigned int) (lo>>1) & 0xFFFF
798 );
799 } else { //standard HID tags 44/96 bits
800 uint8_t bitlen = 0;
801 uint32_t fc = 0;
802 uint32_t cardnum = 0;
803
804 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
805 uint32_t lo2=0;
806 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
807 uint8_t idx3 = 1;
808 while(lo2 > 1){ //find last bit set to 1 (format len bit)
809 lo2=lo2 >> 1;
810 idx3++;
811 }
812 bitlen = idx3+19;
813 fc =0;
814 cardnum=0;
815 if(bitlen == 26){
816 cardnum = (lo>>1)&0xFFFF;
817 fc = (lo>>17)&0xFF;
818 }
819 if(bitlen == 37){
820 cardnum = (lo>>1)&0x7FFFF;
821 fc = ((hi&0xF)<<12)|(lo>>20);
822 }
823 if(bitlen == 34){
824 cardnum = (lo>>1)&0xFFFF;
825 fc= ((hi&1)<<15)|(lo>>17);
826 }
827 if(bitlen == 35){
828 cardnum = (lo>>1)&0xFFFFF;
829 fc = ((hi&1)<<11)|(lo>>21);
830 }
831 }
832 else { //if bit 38 is not set then 37 bit format is used
833 bitlen= 37;
834 fc =0;
835 cardnum=0;
836 if(bitlen==37){
837 cardnum = (lo>>1)&0x7FFFF;
838 fc = ((hi&0xF)<<12)|(lo>>20);
839 }
840 }
841 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
842 (unsigned int) hi,
843 (unsigned int) lo,
844 (unsigned int) (lo>>1) & 0xFFFF,
845 (unsigned int) bitlen,
846 (unsigned int) fc,
847 (unsigned int) cardnum);
848 }
849 if (findone){
850 if (ledcontrol) LED_A_OFF();
851 *high = hi;
852 *low = lo;
853 return;
854 }
855 // reset
856 }
857 hi2 = hi = lo = idx = 0;
858 WDT_HIT();
859 }
860 DbpString("Stopped");
861 if (ledcontrol) LED_A_OFF();
862 }
863
864 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
865 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
866 {
867 uint8_t *dest = BigBuf_get_addr();
868 size_t size;
869 int idx=0;
870 //clear read buffer
871 BigBuf_Clear_keep_EM();
872 // Configure to go in 125Khz listen mode
873 LFSetupFPGAForADC(95, true);
874
875 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
876
877 WDT_HIT();
878 if (ledcontrol) LED_A_ON();
879
880 DoAcquisition_default(-1,true);
881 // FSK demodulator
882 size = 50*128*2; //big enough to catch 2 sequences of largest format
883 idx = AWIDdemodFSK(dest, &size);
884
885 if (idx<=0 || size!=96) continue;
886 // Index map
887 // 0 10 20 30 40 50 60
888 // | | | | | | |
889 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
890 // -----------------------------------------------------------------------------
891 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
892 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
893 // |---26 bit---| |-----117----||-------------142-------------|
894 // b = format bit len, o = odd parity of last 3 bits
895 // f = facility code, c = card number
896 // w = wiegand parity
897 // (26 bit format shown)
898
899 //get raw ID before removing parities
900 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
901 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
902 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
903
904 size = removeParity(dest, idx+8, 4, 1, 88);
905 if (size != 66) continue;
906
907 // Index map
908 // 0 10 20 30 40 50 60
909 // | | | | | | |
910 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
911 // -----------------------------------------------------------------------------
912 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
913 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
914 // |26 bit| |-117--| |-----142------|
915 //
916 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
917 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
918 // |50 bit| |----4000------||-----------2248975-------------|
919 //
920 // b = format bit len, o = odd parity of last 3 bits
921 // f = facility code, c = card number
922 // w = wiegand parity
923
924 uint32_t fc = 0;
925 uint32_t cardnum = 0;
926 uint32_t code1 = 0;
927 uint32_t code2 = 0;
928 uint8_t fmtLen = bytebits_to_byte(dest,8);
929 switch(fmtLen) {
930 case 26:
931 fc = bytebits_to_byte(dest + 9, 8);
932 cardnum = bytebits_to_byte(dest + 17, 16);
933 code1 = bytebits_to_byte(dest + 8,fmtLen);
934 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
935 break;
936 case 50:
937 fc = bytebits_to_byte(dest + 9, 16);
938 cardnum = bytebits_to_byte(dest + 25, 32);
939 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
940 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
941 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
942 break;
943 default:
944 if (fmtLen > 32 ) {
945 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
946 code1 = bytebits_to_byte(dest+8,fmtLen-32);
947 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
948 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
949 } else {
950 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
951 code1 = bytebits_to_byte(dest+8,fmtLen);
952 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
953 }
954 break;
955 }
956 if (findone){
957 if (ledcontrol) LED_A_OFF();
958 return;
959 }
960 idx = 0;
961 WDT_HIT();
962 }
963 DbpString("Stopped");
964 if (ledcontrol) LED_A_OFF();
965 }
966
967 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
968 {
969 uint8_t *dest = BigBuf_get_addr();
970
971 size_t size=0, idx=0;
972 int clk=0, invert=0, errCnt=0, maxErr=20;
973 uint32_t hi=0;
974 uint64_t lo=0;
975 //clear read buffer
976 BigBuf_Clear_keep_EM();
977 // Configure to go in 125Khz listen mode
978 LFSetupFPGAForADC(95, true);
979
980 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
981
982 WDT_HIT();
983 if (ledcontrol) LED_A_ON();
984
985 DoAcquisition_default(-1,true);
986 size = BigBuf_max_traceLen();
987 //askdemod and manchester decode
988 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
989 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
990 WDT_HIT();
991
992 if (errCnt<0) continue;
993
994 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
995 if (errCnt){
996 if (size>64){
997 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
998 hi,
999 (uint32_t)(lo>>32),
1000 (uint32_t)lo,
1001 (uint32_t)(lo&0xFFFF),
1002 (uint32_t)((lo>>16LL) & 0xFF),
1003 (uint32_t)(lo & 0xFFFFFF));
1004 } else {
1005 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1006 (uint32_t)(lo>>32),
1007 (uint32_t)lo,
1008 (uint32_t)(lo&0xFFFF),
1009 (uint32_t)((lo>>16LL) & 0xFF),
1010 (uint32_t)(lo & 0xFFFFFF));
1011 }
1012
1013 if (findone){
1014 if (ledcontrol) LED_A_OFF();
1015 *high=lo>>32;
1016 *low=lo & 0xFFFFFFFF;
1017 return;
1018 }
1019 }
1020 WDT_HIT();
1021 hi = lo = size = idx = 0;
1022 clk = invert = errCnt = 0;
1023 }
1024 DbpString("Stopped");
1025 if (ledcontrol) LED_A_OFF();
1026 }
1027
1028 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1029 {
1030 uint8_t *dest = BigBuf_get_addr();
1031 int idx=0;
1032 uint32_t code=0, code2=0;
1033 uint8_t version=0;
1034 uint8_t facilitycode=0;
1035 uint16_t number=0;
1036 uint8_t crc = 0;
1037 uint16_t calccrc = 0;
1038
1039 //clear read buffer
1040 BigBuf_Clear_keep_EM();
1041
1042 // Configure to go in 125Khz listen mode
1043 LFSetupFPGAForADC(95, true);
1044
1045 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1046 WDT_HIT();
1047 if (ledcontrol) LED_A_ON();
1048 DoAcquisition_default(-1,true);
1049 //fskdemod and get start index
1050 WDT_HIT();
1051 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1052 if (idx<0) continue;
1053 //valid tag found
1054
1055 //Index map
1056 //0 10 20 30 40 50 60
1057 //| | | | | | |
1058 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1059 //-----------------------------------------------------------------------------
1060 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1061 //
1062 //Checksum:
1063 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1064 //preamble F0 E0 01 03 B6 75
1065 // How to calc checksum,
1066 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1067 // F0 + E0 + 01 + 03 + B6 = 28A
1068 // 28A & FF = 8A
1069 // FF - 8A = 75
1070 // Checksum: 0x75
1071 //XSF(version)facility:codeone+codetwo
1072 //Handle the data
1073 if(findone){ //only print binary if we are doing one
1074 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1075 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1076 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1077 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1078 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1079 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1080 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1081 }
1082 code = bytebits_to_byte(dest+idx,32);
1083 code2 = bytebits_to_byte(dest+idx+32,32);
1084 version = bytebits_to_byte(dest+idx+27,8); //14,4
1085 facilitycode = bytebits_to_byte(dest+idx+18,8);
1086 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1087
1088 crc = bytebits_to_byte(dest+idx+54,8);
1089 for (uint8_t i=1; i<6; ++i)
1090 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1091 calccrc &= 0xff;
1092 calccrc = 0xff - calccrc;
1093
1094 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1095
1096 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1097 // if we're only looking for one tag
1098 if (findone){
1099 if (ledcontrol) LED_A_OFF();
1100 *high=code;
1101 *low=code2;
1102 return;
1103 }
1104 code=code2=0;
1105 version=facilitycode=0;
1106 number=0;
1107 idx=0;
1108
1109 WDT_HIT();
1110 }
1111 DbpString("Stopped");
1112 if (ledcontrol) LED_A_OFF();
1113 }
1114
1115 /*------------------------------
1116 * T5555/T5557/T5567/T5577 routines
1117 *------------------------------
1118 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1119 *
1120 * Relevant communication times in microsecond
1121 * To compensate antenna falling times shorten the write times
1122 * and enlarge the gap ones.
1123 * Q5 tags seems to have issues when these values changes.
1124 */
1125
1126 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
1127 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
1128 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
1129 #define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
1130 #define READ_GAP 15*8
1131
1132 // VALUES TAKEN FROM EM4x function: SendForward
1133 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1134 // WRITE_GAP = 128; (16*8)
1135 // WRITE_1 = 256 32*8; (32*8)
1136
1137 // These timings work for 4469/4269/4305 (with the 55*8 above)
1138 // WRITE_0 = 23*8 , 9*8
1139
1140 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1141 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1142 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1143 // T0 = TIMER_CLOCK1 / 125000 = 192
1144 // 1 Cycle = 8 microseconds(us) == 1 field clock
1145
1146 // new timer:
1147 // = 1us = 1.5ticks
1148 // 1fc = 8us = 12ticks
1149 void TurnReadLFOn(uint32_t delay) {
1150 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1151
1152 // measure antenna strength.
1153 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1154
1155 // Give it a bit of time for the resonant antenna to settle.
1156 WaitUS(delay);
1157 }
1158
1159 // Write one bit to card
1160 void T55xxWriteBit(int bit) {
1161 if (!bit)
1162 TurnReadLFOn(WRITE_0);
1163 else
1164 TurnReadLFOn(WRITE_1);
1165 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1166 WaitUS(WRITE_GAP);
1167 }
1168
1169 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1170 void T55xxResetRead(void) {
1171 LED_A_ON();
1172 //clear buffer now so it does not interfere with timing later
1173 BigBuf_Clear_keep_EM();
1174
1175 // Set up FPGA, 125kHz
1176 LFSetupFPGAForADC(95, true);
1177
1178 // Trigger T55x7 in mode.
1179 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1180 WaitUS(START_GAP);
1181
1182 // reset tag - op code 00
1183 T55xxWriteBit(0);
1184 T55xxWriteBit(0);
1185
1186 // Turn field on to read the response
1187 TurnReadLFOn(READ_GAP);
1188
1189 // Acquisition
1190 doT55x7Acquisition(BigBuf_max_traceLen());
1191
1192 // Turn the field off
1193 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1194 cmd_send(CMD_ACK,0,0,0,0,0);
1195 LED_A_OFF();
1196 }
1197
1198 // Write one card block in page 0, no lock
1199 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1200 LED_A_ON();
1201 bool PwdMode = arg & 0x1;
1202 uint8_t Page = (arg & 0x2)>>1;
1203 uint32_t i = 0;
1204
1205 // Set up FPGA, 125kHz
1206 LFSetupFPGAForADC(95, true);
1207
1208 // Trigger T55x7 in mode.
1209 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1210 WaitUS(START_GAP);
1211
1212 // Opcode 10
1213 T55xxWriteBit(1);
1214 T55xxWriteBit(Page); //Page 0
1215 if (PwdMode){
1216 // Send Pwd
1217 for (i = 0x80000000; i != 0; i >>= 1)
1218 T55xxWriteBit(Pwd & i);
1219 }
1220 // Send Lock bit
1221 T55xxWriteBit(0);
1222
1223 // Send Data
1224 for (i = 0x80000000; i != 0; i >>= 1)
1225 T55xxWriteBit(Data & i);
1226
1227 // Send Block number
1228 for (i = 0x04; i != 0; i >>= 1)
1229 T55xxWriteBit(Block & i);
1230
1231 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1232 // so wait a little more)
1233 TurnReadLFOn(20 * 1000);
1234
1235 //could attempt to do a read to confirm write took
1236 // as the tag should repeat back the new block
1237 // until it is reset, but to confirm it we would
1238 // need to know the current block 0 config mode
1239
1240 // turn field off
1241 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1242 LED_A_OFF();
1243 }
1244
1245 // Write one card block in page 0, no lock
1246 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1247 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1248 cmd_send(CMD_ACK,0,0,0,0,0);
1249 }
1250
1251 // Read one card block in page [page]
1252 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1253 LED_A_ON();
1254 bool PwdMode = arg0 & 0x1;
1255 uint8_t Page = (arg0 & 0x2) >> 1;
1256 uint32_t i = 0;
1257 bool RegReadMode = (Block == 0xFF);
1258
1259 //clear buffer now so it does not interfere with timing later
1260 BigBuf_Clear_keep_EM();
1261
1262 //make sure block is at max 7
1263 Block &= 0x7;
1264
1265 // Set up FPGA, 125kHz to power up the tag
1266 LFSetupFPGAForADC(95, true);
1267 SpinDelay(3);
1268
1269 // Trigger T55x7 Direct Access Mode with start gap
1270 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1271 WaitUS(START_GAP);
1272
1273 // Opcode 1[page]
1274 T55xxWriteBit(1);
1275 T55xxWriteBit(Page); //Page 0
1276
1277 if (PwdMode){
1278 // Send Pwd
1279 for (i = 0x80000000; i != 0; i >>= 1)
1280 T55xxWriteBit(Pwd & i);
1281 }
1282 // Send a zero bit separation
1283 T55xxWriteBit(0);
1284
1285 // Send Block number (if direct access mode)
1286 if (!RegReadMode)
1287 for (i = 0x04; i != 0; i >>= 1)
1288 T55xxWriteBit(Block & i);
1289
1290 // Turn field on to read the response
1291 TurnReadLFOn(READ_GAP);
1292
1293 // Acquisition
1294 doT55x7Acquisition(12000);
1295
1296 // Turn the field off
1297 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1298 cmd_send(CMD_ACK,0,0,0,0,0);
1299 LED_A_OFF();
1300 }
1301
1302 void T55xxWakeUp(uint32_t Pwd){
1303 LED_B_ON();
1304 uint32_t i = 0;
1305
1306 // Set up FPGA, 125kHz
1307 LFSetupFPGAForADC(95, true);
1308
1309 // Trigger T55x7 Direct Access Mode
1310 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1311 WaitUS(START_GAP);
1312
1313 // Opcode 10
1314 T55xxWriteBit(1);
1315 T55xxWriteBit(0); //Page 0
1316
1317 // Send Pwd
1318 for (i = 0x80000000; i != 0; i >>= 1)
1319 T55xxWriteBit(Pwd & i);
1320
1321 // Turn and leave field on to let the begin repeating transmission
1322 TurnReadLFOn(20*1000);
1323 }
1324
1325 /*-------------- Cloning routines -----------*/
1326 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1327 // write last block first and config block last (if included)
1328 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1329 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1330 }
1331
1332 // Copy HID id to card and setup block 0 config
1333 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1334 uint32_t data[] = {0,0,0,0,0,0,0};
1335 uint8_t last_block = 0;
1336
1337 if (longFMT){
1338 // Ensure no more than 84 bits supplied
1339 if (hi2 > 0xFFFFF) {
1340 DbpString("Tags can only have 84 bits.");
1341 return;
1342 }
1343 // Build the 6 data blocks for supplied 84bit ID
1344 last_block = 6;
1345 // load preamble (1D) & long format identifier (9E manchester encoded)
1346 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1347 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1348 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1349 data[3] = manchesterEncode2Bytes(hi >> 16);
1350 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1351 data[5] = manchesterEncode2Bytes(lo >> 16);
1352 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1353 } else {
1354 // Ensure no more than 44 bits supplied
1355 if (hi > 0xFFF) {
1356 DbpString("Tags can only have 44 bits.");
1357 return;
1358 }
1359 // Build the 3 data blocks for supplied 44bit ID
1360 last_block = 3;
1361 // load preamble
1362 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1363 data[2] = manchesterEncode2Bytes(lo >> 16);
1364 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1365 }
1366 // load chip config block
1367 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1368
1369 //TODO add selection of chip for Q5 or T55x7
1370 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1371
1372 LED_D_ON();
1373 // Program the data blocks for supplied ID
1374 // and the block 0 for HID format
1375 WriteT55xx(data, 0, last_block+1);
1376
1377 LED_D_OFF();
1378
1379 DbpString("DONE!");
1380 }
1381
1382 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1383 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1384 //TODO add selection of chip for Q5 or T55x7
1385 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1386 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1387
1388 LED_D_ON();
1389 // Program the data blocks for supplied ID
1390 // and the block 0 config
1391 WriteT55xx(data, 0, 3);
1392 LED_D_OFF();
1393 DbpString("DONE!");
1394 }
1395
1396 // Clone Indala 64-bit tag by UID to T55x7
1397 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1398 //Program the 2 data blocks for supplied 64bit UID
1399 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1400 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1401 //TODO add selection of chip for Q5 or T55x7
1402 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1403
1404 WriteT55xx(data, 0, 3);
1405 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1406 // T5567WriteBlock(0x603E1042,0);
1407 DbpString("DONE!");
1408 }
1409 // Clone Indala 224-bit tag by UID to T55x7
1410 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1411 //Program the 7 data blocks for supplied 224bit UID
1412 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1413 // and the block 0 for Indala224 format
1414 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1415 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1416 //TODO add selection of chip for Q5 or T55x7
1417 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1418 WriteT55xx(data, 0, 8);
1419 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1420 // T5567WriteBlock(0x603E10E2,0);
1421 DbpString("DONE!");
1422 }
1423 // clone viking tag to T55xx
1424 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1425 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1426 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1427 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1428 // Program the data blocks for supplied ID and the block 0 config
1429 WriteT55xx(data, 0, 3);
1430 LED_D_OFF();
1431 cmd_send(CMD_ACK,0,0,0,0,0);
1432 }
1433
1434 // Define 9bit header for EM410x tags
1435 #define EM410X_HEADER 0x1FF
1436 #define EM410X_ID_LENGTH 40
1437
1438 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1439 int i, id_bit;
1440 uint64_t id = EM410X_HEADER;
1441 uint64_t rev_id = 0; // reversed ID
1442 int c_parity[4]; // column parity
1443 int r_parity = 0; // row parity
1444 uint32_t clock = 0;
1445
1446 // Reverse ID bits given as parameter (for simpler operations)
1447 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1448 if (i < 32) {
1449 rev_id = (rev_id << 1) | (id_lo & 1);
1450 id_lo >>= 1;
1451 } else {
1452 rev_id = (rev_id << 1) | (id_hi & 1);
1453 id_hi >>= 1;
1454 }
1455 }
1456
1457 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1458 id_bit = rev_id & 1;
1459
1460 if (i % 4 == 0) {
1461 // Don't write row parity bit at start of parsing
1462 if (i)
1463 id = (id << 1) | r_parity;
1464 // Start counting parity for new row
1465 r_parity = id_bit;
1466 } else {
1467 // Count row parity
1468 r_parity ^= id_bit;
1469 }
1470
1471 // First elements in column?
1472 if (i < 4)
1473 // Fill out first elements
1474 c_parity[i] = id_bit;
1475 else
1476 // Count column parity
1477 c_parity[i % 4] ^= id_bit;
1478
1479 // Insert ID bit
1480 id = (id << 1) | id_bit;
1481 rev_id >>= 1;
1482 }
1483
1484 // Insert parity bit of last row
1485 id = (id << 1) | r_parity;
1486
1487 // Fill out column parity at the end of tag
1488 for (i = 0; i < 4; ++i)
1489 id = (id << 1) | c_parity[i];
1490
1491 // Add stop bit
1492 id <<= 1;
1493
1494 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1495 LED_D_ON();
1496
1497 // Write EM410x ID
1498 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1499
1500 clock = (card & 0xFF00) >> 8;
1501 clock = (clock == 0) ? 64 : clock;
1502 Dbprintf("Clock rate: %d", clock);
1503 if (card & 0xFF) { //t55x7
1504 clock = GetT55xxClockBit(clock);
1505 if (clock == 0) {
1506 Dbprintf("Invalid clock rate: %d", clock);
1507 return;
1508 }
1509 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1510 } else { //t5555 (Q5)
1511 clock = (clock-2)>>1; //n = (RF-2)/2
1512 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1513 }
1514
1515 WriteT55xx(data, 0, 3);
1516
1517 LED_D_OFF();
1518 Dbprintf("Tag %s written with 0x%08x%08x\n",
1519 card ? "T55x7":"T5555",
1520 (uint32_t)(id >> 32),
1521 (uint32_t)id);
1522 }
1523
1524 //-----------------------------------
1525 // EM4469 / EM4305 routines
1526 //-----------------------------------
1527 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1528 #define FWD_CMD_WRITE 0xA
1529 #define FWD_CMD_READ 0x9
1530 #define FWD_CMD_DISABLE 0x5
1531
1532 uint8_t forwardLink_data[64]; //array of forwarded bits
1533 uint8_t * forward_ptr; //ptr for forward message preparation
1534 uint8_t fwd_bit_sz; //forwardlink bit counter
1535 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1536
1537 //====================================================================
1538 // prepares command bits
1539 // see EM4469 spec
1540 //====================================================================
1541 //--------------------------------------------------------------------
1542 // VALUES TAKEN FROM EM4x function: SendForward
1543 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1544 // WRITE_GAP = 128; (16*8)
1545 // WRITE_1 = 256 32*8; (32*8)
1546
1547 // These timings work for 4469/4269/4305 (with the 55*8 above)
1548 // WRITE_0 = 23*8 , 9*8
1549
1550 uint8_t Prepare_Cmd( uint8_t cmd ) {
1551
1552 *forward_ptr++ = 0; //start bit
1553 *forward_ptr++ = 0; //second pause for 4050 code
1554
1555 *forward_ptr++ = cmd;
1556 cmd >>= 1;
1557 *forward_ptr++ = cmd;
1558 cmd >>= 1;
1559 *forward_ptr++ = cmd;
1560 cmd >>= 1;
1561 *forward_ptr++ = cmd;
1562
1563 return 6; //return number of emited bits
1564 }
1565
1566 //====================================================================
1567 // prepares address bits
1568 // see EM4469 spec
1569 //====================================================================
1570 uint8_t Prepare_Addr( uint8_t addr ) {
1571
1572 register uint8_t line_parity;
1573
1574 uint8_t i;
1575 line_parity = 0;
1576 for(i=0;i<6;i++) {
1577 *forward_ptr++ = addr;
1578 line_parity ^= addr;
1579 addr >>= 1;
1580 }
1581
1582 *forward_ptr++ = (line_parity & 1);
1583
1584 return 7; //return number of emited bits
1585 }
1586
1587 //====================================================================
1588 // prepares data bits intreleaved with parity bits
1589 // see EM4469 spec
1590 //====================================================================
1591 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1592
1593 register uint8_t line_parity;
1594 register uint8_t column_parity;
1595 register uint8_t i, j;
1596 register uint16_t data;
1597
1598 data = data_low;
1599 column_parity = 0;
1600
1601 for(i=0; i<4; i++) {
1602 line_parity = 0;
1603 for(j=0; j<8; j++) {
1604 line_parity ^= data;
1605 column_parity ^= (data & 1) << j;
1606 *forward_ptr++ = data;
1607 data >>= 1;
1608 }
1609 *forward_ptr++ = line_parity;
1610 if(i == 1)
1611 data = data_hi;
1612 }
1613
1614 for(j=0; j<8; j++) {
1615 *forward_ptr++ = column_parity;
1616 column_parity >>= 1;
1617 }
1618 *forward_ptr = 0;
1619
1620 return 45; //return number of emited bits
1621 }
1622
1623 //====================================================================
1624 // Forward Link send function
1625 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1626 // fwd_bit_count set with number of bits to be sent
1627 //====================================================================
1628 void SendForward(uint8_t fwd_bit_count) {
1629
1630 fwd_write_ptr = forwardLink_data;
1631 fwd_bit_sz = fwd_bit_count;
1632
1633 LED_D_ON();
1634
1635 // Set up FPGA, 125kHz
1636 LFSetupFPGAForADC(95, true);
1637
1638 // force 1st mod pulse (start gap must be longer for 4305)
1639 fwd_bit_sz--; //prepare next bit modulation
1640 fwd_write_ptr++;
1641 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1642 WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
1643 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1644 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1645
1646 // now start writting
1647 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1648 if(((*fwd_write_ptr++) & 1) == 1)
1649 WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1650 else {
1651 //These timings work for 4469/4269/4305 (with the 55*8 above)
1652 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1653 WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1654 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1655 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1656 }
1657 }
1658 }
1659
1660 void EM4xLogin(uint32_t Password) {
1661
1662 uint8_t fwd_bit_count;
1663 forward_ptr = forwardLink_data;
1664 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1665 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1666 SendForward(fwd_bit_count);
1667
1668 //Wait for command to complete
1669 WaitMS(20);
1670 }
1671
1672 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1673
1674 uint8_t fwd_bit_count;
1675 uint8_t *dest = BigBuf_get_addr();
1676 uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
1677 uint32_t i = 0;
1678
1679 // Clear destination buffer before sending the command
1680 BigBuf_Clear_ext(false);
1681
1682 //If password mode do login
1683 if (PwdMode == 1) EM4xLogin(Pwd);
1684
1685 forward_ptr = forwardLink_data;
1686 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1687 fwd_bit_count += Prepare_Addr( Address );
1688
1689 SendForward(fwd_bit_count);
1690
1691 // Now do the acquisition
1692 // ICEMAN, change to the one in lfsampling.c
1693 i = 0;
1694 for(;;) {
1695 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1696 AT91C_BASE_SSC->SSC_THR = 0x43;
1697 }
1698 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1699 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1700 ++i;
1701 if (i >= bufsize) break;
1702 }
1703 }
1704
1705 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1706 cmd_send(CMD_ACK,0,0,0,0,0);
1707 LED_D_OFF();
1708 }
1709
1710 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1711
1712 uint8_t fwd_bit_count;
1713
1714 //If password mode do login
1715 if (PwdMode == 1) EM4xLogin(Pwd);
1716
1717 forward_ptr = forwardLink_data;
1718 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1719 fwd_bit_count += Prepare_Addr( Address );
1720 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1721
1722 SendForward(fwd_bit_count);
1723
1724 //Wait for write to complete
1725 WaitMS(20);
1726 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1727 LED_D_OFF();
1728 }
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