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[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23
24 static uint32_t iso14a_timeout;
25 uint8_t *trace = (uint8_t *) BigBuf+TRACE_OFFSET;
26 int rsamples = 0;
27 int traceLen = 0;
28 int tracing = TRUE;
29 uint8_t trigger = 0;
30 // the block number for the ISO14443-4 PCB
31 static uint8_t iso14_pcb_blocknum = 0;
32
33 //
34 // ISO14443 timing:
35 //
36 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
37 #define REQUEST_GUARD_TIME (7000/16 + 1)
38 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
39 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
40 // bool LastCommandWasRequest = FALSE;
41
42 //
43 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
44 //
45 // When the PM acts as reader and is receiving tag data, it takes
46 // 3 ticks delay in the AD converter
47 // 16 ticks until the modulation detector completes and sets curbit
48 // 8 ticks until bit_to_arm is assigned from curbit
49 // 8*16 ticks for the transfer from FPGA to ARM
50 // 4*16 ticks until we measure the time
51 // - 8*16 ticks because we measure the time of the previous transfer
52 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
53
54 // When the PM acts as a reader and is sending, it takes
55 // 4*16 ticks until we can write data to the sending hold register
56 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
57 // 8 ticks until the first transfer starts
58 // 8 ticks later the FPGA samples the data
59 // 1 tick to assign mod_sig_coil
60 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
61
62 // When the PM acts as tag and is receiving it takes
63 // 2 ticks delay in the RF part (for the first falling edge),
64 // 3 ticks for the A/D conversion,
65 // 8 ticks on average until the start of the SSC transfer,
66 // 8 ticks until the SSC samples the first data
67 // 7*16 ticks to complete the transfer from FPGA to ARM
68 // 8 ticks until the next ssp_clk rising edge
69 // 4*16 ticks until we measure the time
70 // - 8*16 ticks because we measure the time of the previous transfer
71 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
72
73 // The FPGA will report its internal sending delay in
74 uint16_t FpgaSendQueueDelay;
75 // the 5 first bits are the number of bits buffered in mod_sig_buf
76 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
77 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
78
79 // When the PM acts as tag and is sending, it takes
80 // 4*16 ticks until we can write data to the sending hold register
81 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
82 // 8 ticks until the first transfer starts
83 // 8 ticks later the FPGA samples the data
84 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
85 // + 1 tick to assign mod_sig_coil
86 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
87
88 // When the PM acts as sniffer and is receiving tag data, it takes
89 // 3 ticks A/D conversion
90 // 14 ticks to complete the modulation detection
91 // 8 ticks (on average) until the result is stored in to_arm
92 // + the delays in transferring data - which is the same for
93 // sniffing reader and tag data and therefore not relevant
94 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
95
96 // When the PM acts as sniffer and is receiving reader data, it takes
97 // 2 ticks delay in analogue RF receiver (for the falling edge of the
98 // start bit, which marks the start of the communication)
99 // 3 ticks A/D conversion
100 // 8 ticks on average until the data is stored in to_arm.
101 // + the delays in transferring data - which is the same for
102 // sniffing reader and tag data and therefore not relevant
103 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
104
105 //variables used for timing purposes:
106 //these are in ssp_clk cycles:
107 static uint32_t NextTransferTime;
108 static uint32_t LastTimeProxToAirStart;
109 static uint32_t LastProxToAirDuration;
110
111
112
113 // CARD TO READER - manchester
114 // Sequence D: 11110000 modulation with subcarrier during first half
115 // Sequence E: 00001111 modulation with subcarrier during second half
116 // Sequence F: 00000000 no modulation with subcarrier
117 // READER TO CARD - miller
118 // Sequence X: 00001100 drop after half a period
119 // Sequence Y: 00000000 no drop
120 // Sequence Z: 11000000 drop at start
121 #define SEC_D 0xf0
122 #define SEC_E 0x0f
123 #define SEC_F 0x00
124 #define SEC_X 0x0c
125 #define SEC_Y 0x00
126 #define SEC_Z 0xc0
127
128 const uint8_t OddByteParity[256] = {
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
142 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
143 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
144 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
145 };
146
147
148 void iso14a_set_trigger(bool enable) {
149 trigger = enable;
150 }
151
152 void iso14a_clear_trace() {
153 memset(trace, 0x44, TRACE_SIZE);
154 traceLen = 0;
155 }
156
157 void iso14a_set_tracing(bool enable) {
158 tracing = enable;
159 }
160
161 void iso14a_set_timeout(uint32_t timeout) {
162 iso14a_timeout = timeout;
163 }
164
165 //-----------------------------------------------------------------------------
166 // Generate the parity value for a byte sequence
167 //
168 //-----------------------------------------------------------------------------
169 byte_t oddparity (const byte_t bt)
170 {
171 return OddByteParity[bt];
172 }
173
174 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
175 {
176 uint16_t paritybit_cnt = 0;
177 uint16_t paritybyte_cnt = 0;
178 uint8_t parityBits = 0;
179
180 for (uint16_t i = 0; i < iLen; i++) {
181 // Generate the parity bits
182 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
183 if (paritybit_cnt == 7) {
184 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
185 parityBits = 0; // and advance to next Parity Byte
186 paritybyte_cnt++;
187 paritybit_cnt = 0;
188 } else {
189 paritybit_cnt++;
190 }
191 }
192
193 // save remaining parity bits
194 par[paritybyte_cnt] = parityBits;
195
196 }
197
198 void AppendCrc14443a(uint8_t* data, int len)
199 {
200 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
201 }
202
203 // The function LogTrace() is also used by the iClass implementation in iClass.c
204 bool RAMFUNC LogTrace(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag)
205 {
206 if (!tracing) return FALSE;
207
208 uint16_t num_paritybytes = (iLen-1)/8 + 1; // number of valid paritybytes in *parity
209 uint16_t duration = timestamp_end - timestamp_start;
210
211 // Return when trace is full
212 if (traceLen + sizeof(iLen) + sizeof(timestamp_start) + sizeof(duration) + num_paritybytes + iLen >= TRACE_SIZE) {
213 tracing = FALSE; // don't trace any more
214 return FALSE;
215 }
216
217 // Traceformat:
218 // 32 bits timestamp (little endian)
219 // 16 bits duration (little endian)
220 // 16 bits data length (little endian, Highest Bit used as readerToTag flag)
221 // y Bytes data
222 // x Bytes parity (one byte per 8 bytes data)
223
224 // timestamp (start)
225 trace[traceLen++] = ((timestamp_start >> 0) & 0xff);
226 trace[traceLen++] = ((timestamp_start >> 8) & 0xff);
227 trace[traceLen++] = ((timestamp_start >> 16) & 0xff);
228 trace[traceLen++] = ((timestamp_start >> 24) & 0xff);
229
230 // duration
231 trace[traceLen++] = ((duration >> 0) & 0xff);
232 trace[traceLen++] = ((duration >> 8) & 0xff);
233
234 // data length
235 trace[traceLen++] = ((iLen >> 0) & 0xff);
236 trace[traceLen++] = ((iLen >> 8) & 0xff);
237
238 // readerToTag flag
239 if (!readerToTag) {
240 trace[traceLen - 1] |= 0x80;
241 }
242
243 // data bytes
244 if (btBytes != NULL && iLen != 0) {
245 memcpy(trace + traceLen, btBytes, iLen);
246 }
247 traceLen += iLen;
248
249 // parity bytes
250 if (parity != NULL && iLen != 0) {
251 memcpy(trace + traceLen, parity, num_paritybytes);
252 }
253 traceLen += num_paritybytes;
254
255 return TRUE;
256 }
257
258 //=============================================================================
259 // ISO 14443 Type A - Miller decoder
260 //=============================================================================
261 // Basics:
262 // This decoder is used when the PM3 acts as a tag.
263 // The reader will generate "pauses" by temporarily switching of the field.
264 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
265 // The FPGA does a comparison with a threshold and would deliver e.g.:
266 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
267 // The Miller decoder needs to identify the following sequences:
268 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
269 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
270 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
271 // Note 1: the bitstream may start at any time. We therefore need to sync.
272 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
273 //-----------------------------------------------------------------------------
274 static tUart Uart;
275
276 // Lookup-Table to decide if 4 raw bits are a modulation.
277 // We accept two or three consecutive "0" in any position with the rest "1"
278 const bool Mod_Miller_LUT[] = {
279 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
280 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
281 };
282 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
283 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
284
285 void UartReset()
286 {
287 Uart.state = STATE_UNSYNCD;
288 Uart.bitCount = 0;
289 Uart.len = 0; // number of decoded data bytes
290 Uart.parityLen = 0; // number of decoded parity bytes
291 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
292 Uart.parityBits = 0; // holds 8 parity bits
293 Uart.twoBits = 0x0000; // buffer for 2 Bits
294 Uart.highCnt = 0;
295 Uart.startTime = 0;
296 Uart.endTime = 0;
297 }
298
299 void UartInit(uint8_t *data, uint8_t *parity)
300 {
301 Uart.output = data;
302 Uart.parity = parity;
303 UartReset();
304 }
305
306 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
307 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
308 {
309
310 Uart.twoBits = (Uart.twoBits << 8) | bit;
311
312 if (Uart.state == STATE_UNSYNCD) { // not yet synced
313 if (Uart.highCnt < 7) { // wait for a stable unmodulated signal
314 if (Uart.twoBits == 0xffff) {
315 Uart.highCnt++;
316 } else {
317 Uart.highCnt = 0;
318 }
319 } else {
320 Uart.syncBit = 0xFFFF; // not set
321 // look for 00xx1111 (the start bit)
322 if ((Uart.twoBits & 0x6780) == 0x0780) Uart.syncBit = 7;
323 else if ((Uart.twoBits & 0x33C0) == 0x03C0) Uart.syncBit = 6;
324 else if ((Uart.twoBits & 0x19E0) == 0x01E0) Uart.syncBit = 5;
325 else if ((Uart.twoBits & 0x0CF0) == 0x00F0) Uart.syncBit = 4;
326 else if ((Uart.twoBits & 0x0678) == 0x0078) Uart.syncBit = 3;
327 else if ((Uart.twoBits & 0x033C) == 0x003C) Uart.syncBit = 2;
328 else if ((Uart.twoBits & 0x019E) == 0x001E) Uart.syncBit = 1;
329 else if ((Uart.twoBits & 0x00CF) == 0x000F) Uart.syncBit = 0;
330 if (Uart.syncBit != 0xFFFF) {
331 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
332 Uart.startTime -= Uart.syncBit;
333 Uart.endTime = Uart.startTime;
334 Uart.state = STATE_START_OF_COMMUNICATION;
335 }
336 }
337
338 } else {
339
340 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
341 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
342 UartReset();
343 Uart.highCnt = 6;
344 } else { // Modulation in first half = Sequence Z = logic "0"
345 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
346 UartReset();
347 Uart.highCnt = 6;
348 } else {
349 Uart.bitCount++;
350 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
351 Uart.state = STATE_MILLER_Z;
352 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
353 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
354 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
355 Uart.parityBits <<= 1; // make room for the parity bit
356 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
357 Uart.bitCount = 0;
358 Uart.shiftReg = 0;
359 if((Uart.len&0x0007) == 0) { // every 8 data bytes
360 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
361 Uart.parityBits = 0;
362 }
363 }
364 }
365 }
366 } else {
367 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
368 Uart.bitCount++;
369 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
370 Uart.state = STATE_MILLER_X;
371 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
372 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
373 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
374 Uart.parityBits <<= 1; // make room for the new parity bit
375 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
376 Uart.bitCount = 0;
377 Uart.shiftReg = 0;
378 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
379 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
380 Uart.parityBits = 0;
381 }
382 }
383 } else { // no modulation in both halves - Sequence Y
384 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
385 Uart.state = STATE_UNSYNCD;
386 Uart.bitCount--; // last "0" was part of EOC sequence
387 Uart.shiftReg <<= 1; // drop it
388 if(Uart.bitCount > 0) { // if we decoded some bits
389 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
390 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
391 Uart.parityBits <<= 1; // add a (void) parity bit
392 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
393 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
394 return TRUE;
395 } else if (Uart.len & 0x0007) { // there are some parity bits to store
396 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
397 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
398 }
399 if (Uart.len) {
400 return TRUE; // we are finished with decoding the raw data sequence
401 } else {
402 UartReset(); // Nothing received - try again
403 }
404 }
405 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
406 UartReset();
407 Uart.highCnt = 6;
408 } else { // a logic "0"
409 Uart.bitCount++;
410 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
411 Uart.state = STATE_MILLER_Y;
412 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
413 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
414 Uart.parityBits <<= 1; // make room for the parity bit
415 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
416 Uart.bitCount = 0;
417 Uart.shiftReg = 0;
418 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
419 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
420 Uart.parityBits = 0;
421 }
422 }
423 }
424 }
425 }
426
427 }
428
429 return FALSE; // not finished yet, need more data
430 }
431
432
433
434 //=============================================================================
435 // ISO 14443 Type A - Manchester decoder
436 //=============================================================================
437 // Basics:
438 // This decoder is used when the PM3 acts as a reader.
439 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
440 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
441 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
442 // The Manchester decoder needs to identify the following sequences:
443 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
444 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
445 // 8 ticks unmodulated: Sequence F = end of communication
446 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
447 // Note 1: the bitstream may start at any time. We therefore need to sync.
448 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
449 static tDemod Demod;
450
451 // Lookup-Table to decide if 4 raw bits are a modulation.
452 // We accept three or four "1" in any position
453 const bool Mod_Manchester_LUT[] = {
454 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
455 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
456 };
457
458 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
459 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
460
461
462 void DemodReset()
463 {
464 Demod.state = DEMOD_UNSYNCD;
465 Demod.len = 0; // number of decoded data bytes
466 Demod.parityLen = 0;
467 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
468 Demod.parityBits = 0; //
469 Demod.collisionPos = 0; // Position of collision bit
470 Demod.twoBits = 0xffff; // buffer for 2 Bits
471 Demod.highCnt = 0;
472 Demod.startTime = 0;
473 Demod.endTime = 0;
474 }
475
476
477 void DemodInit(uint8_t *data, uint8_t *parity)
478 {
479 Demod.output = data;
480 Demod.parity = parity;
481 DemodReset();
482 }
483
484 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
485 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
486 {
487
488 Demod.twoBits = (Demod.twoBits << 8) | bit;
489
490 if (Demod.state == DEMOD_UNSYNCD) {
491
492 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
493 if (Demod.twoBits == 0x0000) {
494 Demod.highCnt++;
495 } else {
496 Demod.highCnt = 0;
497 }
498 } else {
499 Demod.syncBit = 0xFFFF; // not set
500 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
501 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
502 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
503 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
504 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
505 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
506 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
507 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
508 if (Demod.syncBit != 0xFFFF) {
509 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
510 Demod.startTime -= Demod.syncBit;
511 Demod.bitCount = offset; // number of decoded data bits
512 Demod.state = DEMOD_MANCHESTER_DATA;
513 }
514 }
515
516 } else {
517
518 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
519 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
520 if (!Demod.collisionPos) {
521 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
522 }
523 } // modulation in first half only - Sequence D = 1
524 Demod.bitCount++;
525 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
526 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
527 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
528 Demod.parityBits <<= 1; // make room for the parity bit
529 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
530 Demod.bitCount = 0;
531 Demod.shiftReg = 0;
532 if((Demod.len&0x0007) == 0) { // every 8 data bytes
533 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
534 Demod.parityBits = 0;
535 }
536 }
537 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
538 } else { // no modulation in first half
539 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
540 Demod.bitCount++;
541 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
542 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
543 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
544 Demod.parityBits <<= 1; // make room for the new parity bit
545 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
546 Demod.bitCount = 0;
547 Demod.shiftReg = 0;
548 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
549 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
550 Demod.parityBits = 0;
551 }
552 }
553 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
554 } else { // no modulation in both halves - End of communication
555 if(Demod.bitCount > 0) { // there are some remaining data bits
556 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
557 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
558 Demod.parityBits <<= 1; // add a (void) parity bit
559 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
560 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
561 return TRUE;
562 } else if (Demod.len & 0x0007) { // there are some parity bits to store
563 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
564 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
565 }
566 if (Demod.len) {
567 return TRUE; // we are finished with decoding the raw data sequence
568 } else { // nothing received. Start over
569 DemodReset();
570 }
571 }
572 }
573
574 }
575
576 return FALSE; // not finished yet, need more data
577 }
578
579 //=============================================================================
580 // Finally, a `sniffer' for ISO 14443 Type A
581 // Both sides of communication!
582 //=============================================================================
583
584 //-----------------------------------------------------------------------------
585 // Record the sequence of commands sent by the reader to the tag, with
586 // triggering so that we start recording at the point that the tag is moved
587 // near the reader.
588 //-----------------------------------------------------------------------------
589 void RAMFUNC SnoopIso14443a(uint8_t param) {
590 // param:
591 // bit 0 - trigger from first card answer
592 // bit 1 - trigger from first reader 7-bit request
593
594 LEDsoff();
595 // init trace buffer
596 iso14a_clear_trace();
597 iso14a_set_tracing(TRUE);
598
599 // We won't start recording the frames that we acquire until we trigger;
600 // a good trigger condition to get started is probably when we see a
601 // response from the tag.
602 // triggered == FALSE -- to wait first for card
603 bool triggered = !(param & 0x03);
604
605 // The command (reader -> tag) that we're receiving.
606 // The length of a received command will in most cases be no more than 18 bytes.
607 // So 32 should be enough!
608 uint8_t *receivedCmd = ((uint8_t *)BigBuf) + RECV_CMD_OFFSET;
609 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
610
611 // The response (tag -> reader) that we're receiving.
612 uint8_t *receivedResponse = ((uint8_t *)BigBuf) + RECV_RESP_OFFSET;
613 uint8_t *receivedResponsePar = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
614
615 // As we receive stuff, we copy it from receivedCmd or receivedResponse
616 // into trace, along with its length and other annotations.
617 //uint8_t *trace = (uint8_t *)BigBuf;
618
619 // The DMA buffer, used to stream samples from the FPGA
620 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
621 uint8_t *data = dmaBuf;
622 uint8_t previous_data = 0;
623 int maxDataLen = 0;
624 int dataLen = 0;
625 bool TagIsActive = FALSE;
626 bool ReaderIsActive = FALSE;
627
628 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
629
630 // Set up the demodulator for tag -> reader responses.
631 DemodInit(receivedResponse, receivedResponsePar);
632
633 // Set up the demodulator for the reader -> tag commands
634 UartInit(receivedCmd, receivedCmdPar);
635
636 // Setup and start DMA.
637 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
638
639 // And now we loop, receiving samples.
640 for(uint32_t rsamples = 0; TRUE; ) {
641
642 if(BUTTON_PRESS()) {
643 DbpString("cancelled by button");
644 break;
645 }
646
647 LED_A_ON();
648 WDT_HIT();
649
650 int register readBufDataP = data - dmaBuf;
651 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
652 if (readBufDataP <= dmaBufDataP){
653 dataLen = dmaBufDataP - readBufDataP;
654 } else {
655 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
656 }
657 // test for length of buffer
658 if(dataLen > maxDataLen) {
659 maxDataLen = dataLen;
660 if(dataLen > 400) {
661 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
662 break;
663 }
664 }
665 if(dataLen < 1) continue;
666
667 // primary buffer was stopped( <-- we lost data!
668 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
669 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
670 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
671 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
672 }
673 // secondary buffer sets as primary, secondary buffer was stopped
674 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
675 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
676 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
677 }
678
679 LED_A_OFF();
680
681 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
682
683 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
684 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
685 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
686 LED_C_ON();
687
688 // check - if there is a short 7bit request from reader
689 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
690
691 if(triggered) {
692 if (!LogTrace(receivedCmd,
693 Uart.len,
694 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
695 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
696 Uart.parity,
697 TRUE)) break;
698 }
699 /* And ready to receive another command. */
700 UartReset();
701 /* And also reset the demod code, which might have been */
702 /* false-triggered by the commands from the reader. */
703 DemodReset();
704 LED_B_OFF();
705 }
706 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
707 }
708
709 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
710 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
711 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
712 LED_B_ON();
713
714 if (!LogTrace(receivedResponse,
715 Demod.len,
716 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
717 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
718 Demod.parity,
719 FALSE)) break;
720
721 if ((!triggered) && (param & 0x01)) triggered = TRUE;
722
723 // And ready to receive another response.
724 DemodReset();
725 LED_C_OFF();
726 }
727 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
728 }
729 }
730
731 previous_data = *data;
732 rsamples++;
733 data++;
734 if(data == dmaBuf + DMA_BUFFER_SIZE) {
735 data = dmaBuf;
736 }
737 } // main cycle
738
739 DbpString("COMMAND FINISHED");
740
741 FpgaDisableSscDma();
742 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
743 Dbprintf("traceLen=%d, Uart.output[0]=%08x", traceLen, (uint32_t)Uart.output[0]);
744 LEDsoff();
745 }
746
747 //-----------------------------------------------------------------------------
748 // Prepare tag messages
749 //-----------------------------------------------------------------------------
750 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
751 {
752 ToSendReset();
753
754 // Correction bit, might be removed when not needed
755 ToSendStuffBit(0);
756 ToSendStuffBit(0);
757 ToSendStuffBit(0);
758 ToSendStuffBit(0);
759 ToSendStuffBit(1); // 1
760 ToSendStuffBit(0);
761 ToSendStuffBit(0);
762 ToSendStuffBit(0);
763
764 // Send startbit
765 ToSend[++ToSendMax] = SEC_D;
766
767 LastProxToAirDuration = 8 * ToSendMax - 4;
768
769 for(uint16_t i = 0; i < len; i++) {
770 uint8_t b = cmd[i];
771
772 // Data bits
773 for(uint16_t j = 0; j < 8; j++) {
774 if(b & 1) {
775 ToSend[++ToSendMax] = SEC_D;
776 } else {
777 ToSend[++ToSendMax] = SEC_E;
778 }
779 b >>= 1;
780 }
781
782 // Get the parity bit
783 if (parity[i>>3] & (0x80>>(i&0x0007))) {
784 ToSend[++ToSendMax] = SEC_D;
785 LastProxToAirDuration = 8 * ToSendMax - 4;
786 } else {
787 ToSend[++ToSendMax] = SEC_E;
788 LastProxToAirDuration = 8 * ToSendMax;
789 }
790 }
791
792 // Send stopbit
793 ToSend[++ToSendMax] = SEC_F;
794
795 // Convert from last byte pos to length
796 ToSendMax++;
797 }
798
799 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
800 {
801 uint8_t par[MAX_PARITY_SIZE];
802
803 GetParity(cmd, len, par);
804 CodeIso14443aAsTagPar(cmd, len, par);
805 }
806
807
808 static void Code4bitAnswerAsTag(uint8_t cmd)
809 {
810 int i;
811
812 ToSendReset();
813
814 // Correction bit, might be removed when not needed
815 ToSendStuffBit(0);
816 ToSendStuffBit(0);
817 ToSendStuffBit(0);
818 ToSendStuffBit(0);
819 ToSendStuffBit(1); // 1
820 ToSendStuffBit(0);
821 ToSendStuffBit(0);
822 ToSendStuffBit(0);
823
824 // Send startbit
825 ToSend[++ToSendMax] = SEC_D;
826
827 uint8_t b = cmd;
828 for(i = 0; i < 4; i++) {
829 if(b & 1) {
830 ToSend[++ToSendMax] = SEC_D;
831 LastProxToAirDuration = 8 * ToSendMax - 4;
832 } else {
833 ToSend[++ToSendMax] = SEC_E;
834 LastProxToAirDuration = 8 * ToSendMax;
835 }
836 b >>= 1;
837 }
838
839 // Send stopbit
840 ToSend[++ToSendMax] = SEC_F;
841
842 // Convert from last byte pos to length
843 ToSendMax++;
844 }
845
846 //-----------------------------------------------------------------------------
847 // Wait for commands from reader
848 // Stop when button is pressed
849 // Or return TRUE when command is captured
850 //-----------------------------------------------------------------------------
851 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
852 {
853 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
854 // only, since we are receiving, not transmitting).
855 // Signal field is off with the appropriate LED
856 LED_D_OFF();
857 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
858
859 // Now run a `software UART' on the stream of incoming samples.
860 UartInit(received, parity);
861
862 // clear RXRDY:
863 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
864
865 for(;;) {
866 WDT_HIT();
867
868 if(BUTTON_PRESS()) return FALSE;
869
870 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
871 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
872 if(MillerDecoding(b, 0)) {
873 *len = Uart.len;
874 return TRUE;
875 }
876 }
877 }
878 }
879
880 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
881 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
882 int EmSend4bit(uint8_t resp);
883 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
884 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
885 int EmSendCmd(uint8_t *resp, uint16_t respLen);
886 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
887 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
888 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
889
890 static uint8_t* free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
891
892 typedef struct {
893 uint8_t* response;
894 size_t response_n;
895 uint8_t* modulation;
896 size_t modulation_n;
897 uint32_t ProxToAirDuration;
898 } tag_response_info_t;
899
900 void reset_free_buffer() {
901 free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
902 }
903
904 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
905 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
906 // This will need the following byte array for a modulation sequence
907 // 144 data bits (18 * 8)
908 // 18 parity bits
909 // 2 Start and stop
910 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
911 // 1 just for the case
912 // ----------- +
913 // 166 bytes, since every bit that needs to be send costs us a byte
914 //
915
916 // Prepare the tag modulation bits from the message
917 CodeIso14443aAsTag(response_info->response,response_info->response_n);
918
919 // Make sure we do not exceed the free buffer space
920 if (ToSendMax > max_buffer_size) {
921 Dbprintf("Out of memory, when modulating bits for tag answer:");
922 Dbhexdump(response_info->response_n,response_info->response,false);
923 return false;
924 }
925
926 // Copy the byte array, used for this modulation to the buffer position
927 memcpy(response_info->modulation,ToSend,ToSendMax);
928
929 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
930 response_info->modulation_n = ToSendMax;
931 response_info->ProxToAirDuration = LastProxToAirDuration;
932
933 return true;
934 }
935
936 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
937 // Retrieve and store the current buffer index
938 response_info->modulation = free_buffer_pointer;
939
940 // Determine the maximum size we can use from our buffer
941 size_t max_buffer_size = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + FREE_BUFFER_SIZE) - free_buffer_pointer;
942
943 // Forward the prepare tag modulation function to the inner function
944 if (prepare_tag_modulation(response_info,max_buffer_size)) {
945 // Update the free buffer offset
946 free_buffer_pointer += ToSendMax;
947 return true;
948 } else {
949 return false;
950 }
951 }
952
953 //-----------------------------------------------------------------------------
954 // Main loop of simulated tag: receive commands from reader, decide what
955 // response to send, and send it.
956 //-----------------------------------------------------------------------------
957 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
958 {
959 // Enable and clear the trace
960 iso14a_clear_trace();
961 iso14a_set_tracing(TRUE);
962
963 uint8_t sak;
964
965 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
966 uint8_t response1[2];
967
968 switch (tagType) {
969 case 1: { // MIFARE Classic
970 // Says: I am Mifare 1k - original line
971 response1[0] = 0x04;
972 response1[1] = 0x00;
973 sak = 0x08;
974 } break;
975 case 2: { // MIFARE Ultralight
976 // Says: I am a stupid memory tag, no crypto
977 response1[0] = 0x04;
978 response1[1] = 0x00;
979 sak = 0x00;
980 } break;
981 case 3: { // MIFARE DESFire
982 // Says: I am a DESFire tag, ph33r me
983 response1[0] = 0x04;
984 response1[1] = 0x03;
985 sak = 0x20;
986 } break;
987 case 4: { // ISO/IEC 14443-4
988 // Says: I am a javacard (JCOP)
989 response1[0] = 0x04;
990 response1[1] = 0x00;
991 sak = 0x28;
992 } break;
993 default: {
994 Dbprintf("Error: unkown tagtype (%d)",tagType);
995 return;
996 } break;
997 }
998
999 // The second response contains the (mandatory) first 24 bits of the UID
1000 uint8_t response2[5];
1001
1002 // Check if the uid uses the (optional) part
1003 uint8_t response2a[5];
1004 if (uid_2nd) {
1005 response2[0] = 0x88;
1006 num_to_bytes(uid_1st,3,response2+1);
1007 num_to_bytes(uid_2nd,4,response2a);
1008 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1009
1010 // Configure the ATQA and SAK accordingly
1011 response1[0] |= 0x40;
1012 sak |= 0x04;
1013 } else {
1014 num_to_bytes(uid_1st,4,response2);
1015 // Configure the ATQA and SAK accordingly
1016 response1[0] &= 0xBF;
1017 sak &= 0xFB;
1018 }
1019
1020 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1021 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1022
1023 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1024 uint8_t response3[3];
1025 response3[0] = sak;
1026 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1027
1028 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1029 uint8_t response3a[3];
1030 response3a[0] = sak & 0xFB;
1031 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1032
1033 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1034 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1035 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1036 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1037 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1038 // TC(1) = 0x02: CID supported, NAD not supported
1039 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1040
1041 #define TAG_RESPONSE_COUNT 7
1042 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1043 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1044 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1045 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1046 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1047 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1048 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1049 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1050 };
1051
1052 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1053 // Such a response is less time critical, so we can prepare them on the fly
1054 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1055 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1056 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1057 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1058 tag_response_info_t dynamic_response_info = {
1059 .response = dynamic_response_buffer,
1060 .response_n = 0,
1061 .modulation = dynamic_modulation_buffer,
1062 .modulation_n = 0
1063 };
1064
1065 // Reset the offset pointer of the free buffer
1066 reset_free_buffer();
1067
1068 // Prepare the responses of the anticollision phase
1069 // there will be not enough time to do this at the moment the reader sends it REQA
1070 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1071 prepare_allocated_tag_modulation(&responses[i]);
1072 }
1073
1074 int len = 0;
1075
1076 // To control where we are in the protocol
1077 int order = 0;
1078 int lastorder;
1079
1080 // Just to allow some checks
1081 int happened = 0;
1082 int happened2 = 0;
1083 int cmdsRecvd = 0;
1084
1085 // We need to listen to the high-frequency, peak-detected path.
1086 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1087
1088 // buffers used on software Uart:
1089 uint8_t *receivedCmd = ((uint8_t *)BigBuf) + RECV_CMD_OFFSET;
1090 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
1091
1092 cmdsRecvd = 0;
1093 tag_response_info_t* p_response;
1094
1095 LED_A_ON();
1096 for(;;) {
1097 // Clean receive command buffer
1098
1099 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1100 DbpString("Button press");
1101 break;
1102 }
1103
1104 p_response = NULL;
1105
1106 // Okay, look at the command now.
1107 lastorder = order;
1108 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1109 p_response = &responses[0]; order = 1;
1110 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1111 p_response = &responses[0]; order = 6;
1112 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1113 p_response = &responses[1]; order = 2;
1114 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1115 p_response = &responses[2]; order = 20;
1116 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1117 p_response = &responses[3]; order = 3;
1118 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1119 p_response = &responses[4]; order = 30;
1120 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1121 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1122 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1123 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1124 p_response = NULL;
1125 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1126 // DbpString("Reader requested we HALT!:");
1127 if (tracing) {
1128 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1129 }
1130 p_response = NULL;
1131 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1132 p_response = &responses[5]; order = 7;
1133 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1134 if (tagType == 1 || tagType == 2) { // RATS not supported
1135 EmSend4bit(CARD_NACK_NA);
1136 p_response = NULL;
1137 } else {
1138 p_response = &responses[6]; order = 70;
1139 }
1140 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1141 if (tracing) {
1142 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1143 }
1144 uint32_t nr = bytes_to_num(receivedCmd,4);
1145 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1146 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1147 } else {
1148 // Check for ISO 14443A-4 compliant commands, look at left nibble
1149 switch (receivedCmd[0]) {
1150
1151 case 0x0B:
1152 case 0x0A: { // IBlock (command)
1153 dynamic_response_info.response[0] = receivedCmd[0];
1154 dynamic_response_info.response[1] = 0x00;
1155 dynamic_response_info.response[2] = 0x90;
1156 dynamic_response_info.response[3] = 0x00;
1157 dynamic_response_info.response_n = 4;
1158 } break;
1159
1160 case 0x1A:
1161 case 0x1B: { // Chaining command
1162 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1163 dynamic_response_info.response_n = 2;
1164 } break;
1165
1166 case 0xaa:
1167 case 0xbb: {
1168 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1169 dynamic_response_info.response_n = 2;
1170 } break;
1171
1172 case 0xBA: { //
1173 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1174 dynamic_response_info.response_n = 2;
1175 } break;
1176
1177 case 0xCA:
1178 case 0xC2: { // Readers sends deselect command
1179 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1180 dynamic_response_info.response_n = 2;
1181 } break;
1182
1183 default: {
1184 // Never seen this command before
1185 if (tracing) {
1186 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1187 }
1188 Dbprintf("Received unknown command (len=%d):",len);
1189 Dbhexdump(len,receivedCmd,false);
1190 // Do not respond
1191 dynamic_response_info.response_n = 0;
1192 } break;
1193 }
1194
1195 if (dynamic_response_info.response_n > 0) {
1196 // Copy the CID from the reader query
1197 dynamic_response_info.response[1] = receivedCmd[1];
1198
1199 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1200 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1201 dynamic_response_info.response_n += 2;
1202
1203 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1204 Dbprintf("Error preparing tag response");
1205 if (tracing) {
1206 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1207 }
1208 break;
1209 }
1210 p_response = &dynamic_response_info;
1211 }
1212 }
1213
1214 // Count number of wakeups received after a halt
1215 if(order == 6 && lastorder == 5) { happened++; }
1216
1217 // Count number of other messages after a halt
1218 if(order != 6 && lastorder == 5) { happened2++; }
1219
1220 if(cmdsRecvd > 999) {
1221 DbpString("1000 commands later...");
1222 break;
1223 }
1224 cmdsRecvd++;
1225
1226 if (p_response != NULL) {
1227 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1228 // do the tracing for the previous reader request and this tag answer:
1229 uint8_t par[MAX_PARITY_SIZE];
1230 GetParity(p_response->response, p_response->response_n, par);
1231 EmLogTrace(Uart.output,
1232 Uart.len,
1233 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1234 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1235 Uart.parity,
1236 p_response->response,
1237 p_response->response_n,
1238 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1239 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1240 par);
1241 }
1242
1243 if (!tracing) {
1244 Dbprintf("Trace Full. Simulation stopped.");
1245 break;
1246 }
1247 }
1248
1249 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1250 LED_A_OFF();
1251 }
1252
1253
1254 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1255 // of bits specified in the delay parameter.
1256 void PrepareDelayedTransfer(uint16_t delay)
1257 {
1258 uint8_t bitmask = 0;
1259 uint8_t bits_to_shift = 0;
1260 uint8_t bits_shifted = 0;
1261
1262 delay &= 0x07;
1263 if (delay) {
1264 for (uint16_t i = 0; i < delay; i++) {
1265 bitmask |= (0x01 << i);
1266 }
1267 ToSend[ToSendMax++] = 0x00;
1268 for (uint16_t i = 0; i < ToSendMax; i++) {
1269 bits_to_shift = ToSend[i] & bitmask;
1270 ToSend[i] = ToSend[i] >> delay;
1271 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1272 bits_shifted = bits_to_shift;
1273 }
1274 }
1275 }
1276
1277
1278 //-------------------------------------------------------------------------------------
1279 // Transmit the command (to the tag) that was placed in ToSend[].
1280 // Parameter timing:
1281 // if NULL: transfer at next possible time, taking into account
1282 // request guard time and frame delay time
1283 // if == 0: transfer immediately and return time of transfer
1284 // if != 0: delay transfer until time specified
1285 //-------------------------------------------------------------------------------------
1286 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1287 {
1288
1289 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1290
1291 uint32_t ThisTransferTime = 0;
1292
1293 if (timing) {
1294 if(*timing == 0) { // Measure time
1295 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1296 } else {
1297 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1298 }
1299 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1300 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1301 LastTimeProxToAirStart = *timing;
1302 } else {
1303 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1304 while(GetCountSspClk() < ThisTransferTime);
1305 LastTimeProxToAirStart = ThisTransferTime;
1306 }
1307
1308 // clear TXRDY
1309 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1310
1311 // for(uint16_t c = 0; c < 10;) { // standard delay for each transfer (allow tag to be ready after last transmission)
1312 // if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1313 // AT91C_BASE_SSC->SSC_THR = SEC_Y;
1314 // c++;
1315 // }
1316 // }
1317
1318 uint16_t c = 0;
1319 for(;;) {
1320 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1321 AT91C_BASE_SSC->SSC_THR = cmd[c];
1322 c++;
1323 if(c >= len) {
1324 break;
1325 }
1326 }
1327 }
1328
1329 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1330
1331 }
1332
1333
1334 //-----------------------------------------------------------------------------
1335 // Prepare reader command (in bits, support short frames) to send to FPGA
1336 //-----------------------------------------------------------------------------
1337 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1338 {
1339 int i, j;
1340 int last;
1341 uint8_t b;
1342
1343 ToSendReset();
1344
1345 // Start of Communication (Seq. Z)
1346 ToSend[++ToSendMax] = SEC_Z;
1347 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1348 last = 0;
1349
1350 size_t bytecount = nbytes(bits);
1351 // Generate send structure for the data bits
1352 for (i = 0; i < bytecount; i++) {
1353 // Get the current byte to send
1354 b = cmd[i];
1355 size_t bitsleft = MIN((bits-(i*8)),8);
1356
1357 for (j = 0; j < bitsleft; j++) {
1358 if (b & 1) {
1359 // Sequence X
1360 ToSend[++ToSendMax] = SEC_X;
1361 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1362 last = 1;
1363 } else {
1364 if (last == 0) {
1365 // Sequence Z
1366 ToSend[++ToSendMax] = SEC_Z;
1367 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1368 } else {
1369 // Sequence Y
1370 ToSend[++ToSendMax] = SEC_Y;
1371 last = 0;
1372 }
1373 }
1374 b >>= 1;
1375 }
1376
1377 // Only transmit parity bit if we transmitted a complete byte
1378 if (j == 8) {
1379 // Get the parity bit
1380 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1381 // Sequence X
1382 ToSend[++ToSendMax] = SEC_X;
1383 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1384 last = 1;
1385 } else {
1386 if (last == 0) {
1387 // Sequence Z
1388 ToSend[++ToSendMax] = SEC_Z;
1389 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1390 } else {
1391 // Sequence Y
1392 ToSend[++ToSendMax] = SEC_Y;
1393 last = 0;
1394 }
1395 }
1396 }
1397 }
1398
1399 // End of Communication: Logic 0 followed by Sequence Y
1400 if (last == 0) {
1401 // Sequence Z
1402 ToSend[++ToSendMax] = SEC_Z;
1403 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1404 } else {
1405 // Sequence Y
1406 ToSend[++ToSendMax] = SEC_Y;
1407 last = 0;
1408 }
1409 ToSend[++ToSendMax] = SEC_Y;
1410
1411 // Convert to length of command:
1412 ToSendMax++;
1413 }
1414
1415 //-----------------------------------------------------------------------------
1416 // Prepare reader command to send to FPGA
1417 //-----------------------------------------------------------------------------
1418 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1419 {
1420 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1421 }
1422
1423 //-----------------------------------------------------------------------------
1424 // Wait for commands from reader
1425 // Stop when button is pressed (return 1) or field was gone (return 2)
1426 // Or return 0 when command is captured
1427 //-----------------------------------------------------------------------------
1428 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1429 {
1430 *len = 0;
1431
1432 uint32_t timer = 0, vtime = 0;
1433 int analogCnt = 0;
1434 int analogAVG = 0;
1435
1436 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1437 // only, since we are receiving, not transmitting).
1438 // Signal field is off with the appropriate LED
1439 LED_D_OFF();
1440 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1441
1442 // Set ADC to read field strength
1443 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1444 AT91C_BASE_ADC->ADC_MR =
1445 ADC_MODE_PRESCALE(32) |
1446 ADC_MODE_STARTUP_TIME(16) |
1447 ADC_MODE_SAMPLE_HOLD_TIME(8);
1448 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1449 // start ADC
1450 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1451
1452 // Now run a 'software UART' on the stream of incoming samples.
1453 UartInit(received, parity);
1454
1455 // Clear RXRDY:
1456 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1457
1458 for(;;) {
1459 WDT_HIT();
1460
1461 if (BUTTON_PRESS()) return 1;
1462
1463 // test if the field exists
1464 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1465 analogCnt++;
1466 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1467 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1468 if (analogCnt >= 32) {
1469 if ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1470 vtime = GetTickCount();
1471 if (!timer) timer = vtime;
1472 // 50ms no field --> card to idle state
1473 if (vtime - timer > 50) return 2;
1474 } else
1475 if (timer) timer = 0;
1476 analogCnt = 0;
1477 analogAVG = 0;
1478 }
1479 }
1480
1481 // receive and test the miller decoding
1482 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1483 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1484 if(MillerDecoding(b, 0)) {
1485 *len = Uart.len;
1486 return 0;
1487 }
1488 }
1489
1490 }
1491 }
1492
1493
1494 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1495 {
1496 uint8_t b;
1497 uint16_t i = 0;
1498 uint32_t ThisTransferTime;
1499
1500 // Modulate Manchester
1501 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1502
1503 // include correction bit if necessary
1504 if (Uart.parityBits & 0x01) {
1505 correctionNeeded = TRUE;
1506 }
1507 if(correctionNeeded) {
1508 // 1236, so correction bit needed
1509 i = 0;
1510 } else {
1511 i = 1;
1512 }
1513
1514 // clear receiving shift register and holding register
1515 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1516 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1517 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1518 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1519
1520 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1521 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1522 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1523 if (AT91C_BASE_SSC->SSC_RHR) break;
1524 }
1525
1526 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1527
1528 // Clear TXRDY:
1529 AT91C_BASE_SSC->SSC_THR = SEC_F;
1530
1531 // send cycle
1532 for(; i <= respLen; ) {
1533 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1534 AT91C_BASE_SSC->SSC_THR = resp[i++];
1535 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1536 }
1537
1538 if(BUTTON_PRESS()) {
1539 break;
1540 }
1541 }
1542
1543 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1544 for (i = 0; i < 2 ; ) {
1545 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1546 AT91C_BASE_SSC->SSC_THR = SEC_F;
1547 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1548 i++;
1549 }
1550 }
1551
1552 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1553
1554 return 0;
1555 }
1556
1557 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1558 Code4bitAnswerAsTag(resp);
1559 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1560 // do the tracing for the previous reader request and this tag answer:
1561 uint8_t par[1];
1562 GetParity(&resp, 1, par);
1563 EmLogTrace(Uart.output,
1564 Uart.len,
1565 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1566 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1567 Uart.parity,
1568 &resp,
1569 1,
1570 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1571 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1572 par);
1573 return res;
1574 }
1575
1576 int EmSend4bit(uint8_t resp){
1577 return EmSend4bitEx(resp, false);
1578 }
1579
1580 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1581 CodeIso14443aAsTagPar(resp, respLen, par);
1582 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1583 // do the tracing for the previous reader request and this tag answer:
1584 EmLogTrace(Uart.output,
1585 Uart.len,
1586 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1587 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1588 Uart.parity,
1589 resp,
1590 respLen,
1591 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1592 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1593 par);
1594 return res;
1595 }
1596
1597 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1598 uint8_t par[MAX_PARITY_SIZE];
1599 GetParity(resp, respLen, par);
1600 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1601 }
1602
1603 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1604 uint8_t par[MAX_PARITY_SIZE];
1605 GetParity(resp, respLen, par);
1606 return EmSendCmdExPar(resp, respLen, false, par);
1607 }
1608
1609 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1610 return EmSendCmdExPar(resp, respLen, false, par);
1611 }
1612
1613 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1614 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1615 {
1616 if (tracing) {
1617 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1618 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1619 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1620 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1621 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1622 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1623 reader_EndTime = tag_StartTime - exact_fdt;
1624 reader_StartTime = reader_EndTime - reader_modlen;
1625 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1626 return FALSE;
1627 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1628 } else {
1629 return TRUE;
1630 }
1631 }
1632
1633 //-----------------------------------------------------------------------------
1634 // Wait a certain time for tag response
1635 // If a response is captured return TRUE
1636 // If it takes too long return FALSE
1637 //-----------------------------------------------------------------------------
1638 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1639 {
1640 uint32_t c;
1641
1642 // Set FPGA mode to "reader listen mode", no modulation (listen
1643 // only, since we are receiving, not transmitting).
1644 // Signal field is on with the appropriate LED
1645 LED_D_ON();
1646 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1647
1648 // Now get the answer from the card
1649 DemodInit(receivedResponse, receivedResponsePar);
1650
1651 // clear RXRDY:
1652 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1653
1654 c = 0;
1655 for(;;) {
1656 WDT_HIT();
1657
1658 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1659 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1660 if(ManchesterDecoding(b, offset, 0)) {
1661 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1662 return TRUE;
1663 } else if (c++ > iso14a_timeout) {
1664 return FALSE;
1665 }
1666 }
1667 }
1668 }
1669
1670 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1671 {
1672
1673 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1674
1675 // Send command to tag
1676 TransmitFor14443a(ToSend, ToSendMax, timing);
1677 if(trigger)
1678 LED_A_ON();
1679
1680 // Log reader command in trace buffer
1681 if (tracing) {
1682 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1683 }
1684 }
1685
1686 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1687 {
1688 ReaderTransmitBitsPar(frame, len*8, par, timing);
1689 }
1690
1691 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1692 {
1693 // Generate parity and redirect
1694 uint8_t par[MAX_PARITY_SIZE];
1695 GetParity(frame, len/8, par);
1696 ReaderTransmitBitsPar(frame, len, par, timing);
1697 }
1698
1699 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1700 {
1701 // Generate parity and redirect
1702 uint8_t par[MAX_PARITY_SIZE];
1703 GetParity(frame, len, par);
1704 ReaderTransmitBitsPar(frame, len*8, par, timing);
1705 }
1706
1707 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1708 {
1709 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1710 if (tracing) {
1711 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1712 }
1713 return Demod.len;
1714 }
1715
1716 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1717 {
1718 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1719 if (tracing) {
1720 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1721 }
1722 return Demod.len;
1723 }
1724
1725 /* performs iso14443a anticollision procedure
1726 * fills the uid pointer unless NULL
1727 * fills resp_data unless NULL */
1728 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1729 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1730 uint8_t sel_all[] = { 0x93,0x20 };
1731 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1732 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1733 uint8_t *resp = ((uint8_t *)BigBuf) + RECV_RESP_OFFSET;
1734 uint8_t *resp_par = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
1735 byte_t uid_resp[4];
1736 size_t uid_resp_len;
1737
1738 uint8_t sak = 0x04; // cascade uid
1739 int cascade_level = 0;
1740 int len;
1741
1742 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1743 ReaderTransmitBitsPar(wupa,7,0, NULL);
1744
1745 // Receive the ATQA
1746 if(!ReaderReceive(resp, resp_par)) return 0;
1747 //Dbprintf("atqa: %02x %02x",resp[1],resp[0]);
1748
1749 if(p_hi14a_card) {
1750 memcpy(p_hi14a_card->atqa, resp, 2);
1751 p_hi14a_card->uidlen = 0;
1752 memset(p_hi14a_card->uid,0,10);
1753 }
1754
1755 // clear uid
1756 if (uid_ptr) {
1757 memset(uid_ptr,0,10);
1758 }
1759
1760 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1761 // which case we need to make a cascade 2 request and select - this is a long UID
1762 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1763 for(; sak & 0x04; cascade_level++) {
1764 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1765 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1766
1767 // SELECT_ALL
1768 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1769 if (!ReaderReceive(resp, resp_par)) return 0;
1770
1771 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1772 memset(uid_resp, 0, 4);
1773 uint16_t uid_resp_bits = 0;
1774 uint16_t collision_answer_offset = 0;
1775 // anti-collision-loop:
1776 while (Demod.collisionPos) {
1777 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1778 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1779 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1780 uid_resp[uid_resp_bits & 0xf8] |= UIDbit << (uid_resp_bits % 8);
1781 }
1782 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1783 uid_resp_bits++;
1784 // construct anticollosion command:
1785 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1786 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1787 sel_uid[2+i] = uid_resp[i];
1788 }
1789 collision_answer_offset = uid_resp_bits%8;
1790 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1791 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1792 }
1793 // finally, add the last bits and BCC of the UID
1794 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1795 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1796 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1797 }
1798
1799 } else { // no collision, use the response to SELECT_ALL as current uid
1800 memcpy(uid_resp, resp, 4);
1801 }
1802 uid_resp_len = 4;
1803 //Dbprintf("uid: %02x %02x %02x %02x",uid_resp[0],uid_resp[1],uid_resp[2],uid_resp[3]);
1804
1805 // calculate crypto UID. Always use last 4 Bytes.
1806 if(cuid_ptr) {
1807 *cuid_ptr = bytes_to_num(uid_resp, 4);
1808 }
1809
1810 // Construct SELECT UID command
1811 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1812 memcpy(sel_uid+2, uid_resp, 4); // the UID
1813 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1814 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1815 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1816
1817 // Receive the SAK
1818 if (!ReaderReceive(resp, resp_par)) return 0;
1819 sak = resp[0];
1820
1821 // Test if more parts of the uid are comming
1822 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1823 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1824 // http://www.nxp.com/documents/application_note/AN10927.pdf
1825 // This was earlier:
1826 //memcpy(uid_resp, uid_resp + 1, 3);
1827 // But memcpy should not be used for overlapping arrays,
1828 // and memmove appears to not be available in the arm build.
1829 // Therefore:
1830 uid_resp[0] = uid_resp[1];
1831 uid_resp[1] = uid_resp[2];
1832 uid_resp[2] = uid_resp[3];
1833
1834 uid_resp_len = 3;
1835 }
1836
1837 if(uid_ptr) {
1838 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1839 }
1840
1841 if(p_hi14a_card) {
1842 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1843 p_hi14a_card->uidlen += uid_resp_len;
1844 }
1845 }
1846
1847 if(p_hi14a_card) {
1848 p_hi14a_card->sak = sak;
1849 p_hi14a_card->ats_len = 0;
1850 }
1851
1852 if( (sak & 0x20) == 0) {
1853 return 2; // non iso14443a compliant tag
1854 }
1855
1856 // Request for answer to select
1857 AppendCrc14443a(rats, 2);
1858 ReaderTransmit(rats, sizeof(rats), NULL);
1859
1860 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1861
1862 if(p_hi14a_card) {
1863 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1864 p_hi14a_card->ats_len = len;
1865 }
1866
1867 // reset the PCB block number
1868 iso14_pcb_blocknum = 0;
1869
1870 return 1;
1871 }
1872
1873 void iso14443a_setup(uint8_t fpga_minor_mode) {
1874 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1875 // Set up the synchronous serial port
1876 FpgaSetupSsc();
1877 // connect Demodulated Signal to ADC:
1878 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1879
1880 // Signal field is on with the appropriate LED
1881 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1882 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1883 LED_D_ON();
1884 } else {
1885 LED_D_OFF();
1886 }
1887 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1888
1889 // Start the timer
1890 StartCountSspClk();
1891
1892 DemodReset();
1893 UartReset();
1894 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1895 iso14a_set_timeout(1050); // 10ms default
1896 }
1897
1898 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1899 uint8_t parity[MAX_PARITY_SIZE];
1900 uint8_t real_cmd[cmd_len+4];
1901 real_cmd[0] = 0x0a; //I-Block
1902 // put block number into the PCB
1903 real_cmd[0] |= iso14_pcb_blocknum;
1904 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1905 memcpy(real_cmd+2, cmd, cmd_len);
1906 AppendCrc14443a(real_cmd,cmd_len+2);
1907
1908 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1909 size_t len = ReaderReceive(data, parity);
1910 uint8_t *data_bytes = (uint8_t *) data;
1911 if (!len)
1912 return 0; //DATA LINK ERROR
1913 // if we received an I- or R(ACK)-Block with a block number equal to the
1914 // current block number, toggle the current block number
1915 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1916 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1917 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1918 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1919 {
1920 iso14_pcb_blocknum ^= 1;
1921 }
1922
1923 return len;
1924 }
1925
1926 //-----------------------------------------------------------------------------
1927 // Read an ISO 14443a tag. Send out commands and store answers.
1928 //
1929 //-----------------------------------------------------------------------------
1930 void ReaderIso14443a(UsbCommand *c)
1931 {
1932 iso14a_command_t param = c->arg[0];
1933 uint8_t *cmd = c->d.asBytes;
1934 size_t len = c->arg[1];
1935 size_t lenbits = c->arg[2];
1936 uint32_t arg0 = 0;
1937 byte_t buf[USB_CMD_DATA_SIZE];
1938 uint8_t par[MAX_PARITY_SIZE];
1939
1940 if(param & ISO14A_CONNECT) {
1941 iso14a_clear_trace();
1942 }
1943
1944 iso14a_set_tracing(TRUE);
1945
1946 if(param & ISO14A_REQUEST_TRIGGER) {
1947 iso14a_set_trigger(TRUE);
1948 }
1949
1950 if(param & ISO14A_CONNECT) {
1951 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1952 if(!(param & ISO14A_NO_SELECT)) {
1953 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1954 arg0 = iso14443a_select_card(NULL,card,NULL);
1955 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1956 }
1957 }
1958
1959 if(param & ISO14A_SET_TIMEOUT) {
1960 iso14a_timeout = c->arg[2];
1961 }
1962
1963 if(param & ISO14A_APDU) {
1964 arg0 = iso14_apdu(cmd, len, buf);
1965 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1966 }
1967
1968 if(param & ISO14A_RAW) {
1969 if(param & ISO14A_APPEND_CRC) {
1970 AppendCrc14443a(cmd,len);
1971 len += 2;
1972 if (lenbits) lenbits += 16;
1973 }
1974 if(lenbits>0) {
1975 GetParity(cmd, lenbits/8, par);
1976 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
1977 } else {
1978 ReaderTransmit(cmd,len, NULL);
1979 }
1980 arg0 = ReaderReceive(buf, par);
1981 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1982 }
1983
1984 if(param & ISO14A_REQUEST_TRIGGER) {
1985 iso14a_set_trigger(FALSE);
1986 }
1987
1988 if(param & ISO14A_NO_DISCONNECT) {
1989 return;
1990 }
1991
1992 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1993 LEDsoff();
1994 }
1995
1996
1997 // Determine the distance between two nonces.
1998 // Assume that the difference is small, but we don't know which is first.
1999 // Therefore try in alternating directions.
2000 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2001
2002 uint16_t i;
2003 uint32_t nttmp1, nttmp2;
2004
2005 if (nt1 == nt2) return 0;
2006
2007 nttmp1 = nt1;
2008 nttmp2 = nt2;
2009
2010 for (i = 1; i < 32768; i++) {
2011 nttmp1 = prng_successor(nttmp1, 1);
2012 if (nttmp1 == nt2) return i;
2013 nttmp2 = prng_successor(nttmp2, 1);
2014 if (nttmp2 == nt1) return -i;
2015 }
2016
2017 return(-99999); // either nt1 or nt2 are invalid nonces
2018 }
2019
2020
2021 //-----------------------------------------------------------------------------
2022 // Recover several bits of the cypher stream. This implements (first stages of)
2023 // the algorithm described in "The Dark Side of Security by Obscurity and
2024 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2025 // (article by Nicolas T. Courtois, 2009)
2026 //-----------------------------------------------------------------------------
2027 void ReaderMifare(bool first_try)
2028 {
2029 // Mifare AUTH
2030 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2031 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2032 static uint8_t mf_nr_ar3;
2033
2034 uint8_t* receivedAnswer = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
2035 uint8_t* receivedAnswerPar = (((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET);
2036
2037 iso14a_clear_trace();
2038 iso14a_set_tracing(TRUE);
2039
2040 byte_t nt_diff = 0;
2041 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2042 static byte_t par_low = 0;
2043 bool led_on = TRUE;
2044 uint8_t uid[10] ={0};
2045 uint32_t cuid;
2046
2047 uint32_t nt = 0;
2048 uint32_t previous_nt = 0;
2049 static uint32_t nt_attacked = 0;
2050 byte_t par_list[8] = {0,0,0,0,0,0,0,0};
2051 byte_t ks_list[8] = {0,0,0,0,0,0,0,0};
2052
2053 static uint32_t sync_time;
2054 static uint32_t sync_cycles;
2055 int catch_up_cycles = 0;
2056 int last_catch_up = 0;
2057 uint16_t consecutive_resyncs = 0;
2058 int isOK = 0;
2059
2060
2061
2062 if (first_try) {
2063 mf_nr_ar3 = 0;
2064 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2065 sync_time = GetCountSspClk() & 0xfffffff8;
2066 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2067 nt_attacked = 0;
2068 nt = 0;
2069 par[0] = 0;
2070 }
2071 else {
2072 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2073 mf_nr_ar3++;
2074 mf_nr_ar[3] = mf_nr_ar3;
2075 par[0] = par_low;
2076 }
2077
2078 LED_A_ON();
2079 LED_B_OFF();
2080 LED_C_OFF();
2081
2082
2083 for(uint16_t i = 0; TRUE; i++) {
2084
2085 WDT_HIT();
2086
2087 // Test if the action was cancelled
2088 if(BUTTON_PRESS()) {
2089 break;
2090 }
2091
2092 LED_C_ON();
2093
2094 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2095 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2096 continue;
2097 }
2098
2099 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2100 catch_up_cycles = 0;
2101
2102 // if we missed the sync time already, advance to the next nonce repeat
2103 while(GetCountSspClk() > sync_time) {
2104 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2105 }
2106
2107 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2108 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2109
2110 // Receive the (4 Byte) "random" nonce
2111 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2112 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2113 continue;
2114 }
2115
2116 previous_nt = nt;
2117 nt = bytes_to_num(receivedAnswer, 4);
2118
2119 // Transmit reader nonce with fake par
2120 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2121
2122 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2123 int nt_distance = dist_nt(previous_nt, nt);
2124 if (nt_distance == 0) {
2125 nt_attacked = nt;
2126 }
2127 else {
2128 if (nt_distance == -99999) { // invalid nonce received, try again
2129 continue;
2130 }
2131 sync_cycles = (sync_cycles - nt_distance);
2132 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2133 continue;
2134 }
2135 }
2136
2137 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2138 catch_up_cycles = -dist_nt(nt_attacked, nt);
2139 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2140 catch_up_cycles = 0;
2141 continue;
2142 }
2143 if (catch_up_cycles == last_catch_up) {
2144 consecutive_resyncs++;
2145 }
2146 else {
2147 last_catch_up = catch_up_cycles;
2148 consecutive_resyncs = 0;
2149 }
2150 if (consecutive_resyncs < 3) {
2151 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2152 }
2153 else {
2154 sync_cycles = sync_cycles + catch_up_cycles;
2155 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2156 }
2157 continue;
2158 }
2159
2160 consecutive_resyncs = 0;
2161
2162 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2163 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
2164 {
2165 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2166
2167 if (nt_diff == 0)
2168 {
2169 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2170 }
2171
2172 led_on = !led_on;
2173 if(led_on) LED_B_ON(); else LED_B_OFF();
2174
2175 par_list[nt_diff] = SwapBits(par[0], 8);
2176 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2177
2178 // Test if the information is complete
2179 if (nt_diff == 0x07) {
2180 isOK = 1;
2181 break;
2182 }
2183
2184 nt_diff = (nt_diff + 1) & 0x07;
2185 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2186 par[0] = par_low;
2187 } else {
2188 if (nt_diff == 0 && first_try)
2189 {
2190 par[0]++;
2191 } else {
2192 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2193 }
2194 }
2195 }
2196
2197
2198 mf_nr_ar[3] &= 0x1F;
2199
2200 byte_t buf[28];
2201 memcpy(buf + 0, uid, 4);
2202 num_to_bytes(nt, 4, buf + 4);
2203 memcpy(buf + 8, par_list, 8);
2204 memcpy(buf + 16, ks_list, 8);
2205 memcpy(buf + 24, mf_nr_ar, 4);
2206
2207 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2208
2209 // Thats it...
2210 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2211 LEDsoff();
2212
2213 iso14a_set_tracing(FALSE);
2214 }
2215
2216 /**
2217 *MIFARE 1K simulate.
2218 *
2219 *@param flags :
2220 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2221 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2222 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2223 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2224 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2225 */
2226 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2227 {
2228 int cardSTATE = MFEMUL_NOFIELD;
2229 int _7BUID = 0;
2230 int vHf = 0; // in mV
2231 int res;
2232 uint32_t selTimer = 0;
2233 uint32_t authTimer = 0;
2234 uint16_t len = 0;
2235 uint8_t cardWRBL = 0;
2236 uint8_t cardAUTHSC = 0;
2237 uint8_t cardAUTHKEY = 0xff; // no authentication
2238 uint32_t cardRr = 0;
2239 uint32_t cuid = 0;
2240 //uint32_t rn_enc = 0;
2241 uint32_t ans = 0;
2242 uint32_t cardINTREG = 0;
2243 uint8_t cardINTBLOCK = 0;
2244 struct Crypto1State mpcs = {0, 0};
2245 struct Crypto1State *pcs;
2246 pcs = &mpcs;
2247 uint32_t numReads = 0;//Counts numer of times reader read a block
2248 uint8_t* receivedCmd = get_bigbufptr_recvcmdbuf();
2249 uint8_t* receivedCmd_par = receivedCmd + MAX_FRAME_SIZE;
2250 uint8_t* response = get_bigbufptr_recvrespbuf();
2251 uint8_t* response_par = response + MAX_FRAME_SIZE;
2252
2253 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2254 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2255 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2256 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2257 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2258
2259 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2260 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2261
2262 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2263 // This can be used in a reader-only attack.
2264 // (it can also be retrieved via 'hf 14a list', but hey...
2265 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2266 uint8_t ar_nr_collected = 0;
2267
2268 // clear trace
2269 iso14a_clear_trace();
2270 iso14a_set_tracing(TRUE);
2271
2272 // Authenticate response - nonce
2273 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2274
2275 //-- Determine the UID
2276 // Can be set from emulator memory, incoming data
2277 // and can be 7 or 4 bytes long
2278 if (flags & FLAG_4B_UID_IN_DATA)
2279 {
2280 // 4B uid comes from data-portion of packet
2281 memcpy(rUIDBCC1,datain,4);
2282 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2283
2284 } else if (flags & FLAG_7B_UID_IN_DATA) {
2285 // 7B uid comes from data-portion of packet
2286 memcpy(&rUIDBCC1[1],datain,3);
2287 memcpy(rUIDBCC2, datain+3, 4);
2288 _7BUID = true;
2289 } else {
2290 // get UID from emul memory
2291 emlGetMemBt(receivedCmd, 7, 1);
2292 _7BUID = !(receivedCmd[0] == 0x00);
2293 if (!_7BUID) { // ---------- 4BUID
2294 emlGetMemBt(rUIDBCC1, 0, 4);
2295 } else { // ---------- 7BUID
2296 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2297 emlGetMemBt(rUIDBCC2, 3, 4);
2298 }
2299 }
2300
2301 /*
2302 * Regardless of what method was used to set the UID, set fifth byte and modify
2303 * the ATQA for 4 or 7-byte UID
2304 */
2305 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2306 if (_7BUID) {
2307 rATQA[0] = 0x44;
2308 rUIDBCC1[0] = 0x88;
2309 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2310 }
2311
2312 // We need to listen to the high-frequency, peak-detected path.
2313 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2314
2315
2316 if (MF_DBGLEVEL >= 1) {
2317 if (!_7BUID) {
2318 Dbprintf("4B UID: %02x%02x%02x%02x",
2319 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2320 } else {
2321 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2322 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2323 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2324 }
2325 }
2326
2327 bool finished = FALSE;
2328 while (!BUTTON_PRESS() && !finished) {
2329 WDT_HIT();
2330
2331 // find reader field
2332 // Vref = 3300mV, and an 10:1 voltage divider on the input
2333 // can measure voltages up to 33000 mV
2334 if (cardSTATE == MFEMUL_NOFIELD) {
2335 vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;
2336 if (vHf > MF_MINFIELDV) {
2337 cardSTATE_TO_IDLE();
2338 LED_A_ON();
2339 }
2340 }
2341 if(cardSTATE == MFEMUL_NOFIELD) continue;
2342
2343 //Now, get data
2344
2345 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2346 if (res == 2) { //Field is off!
2347 cardSTATE = MFEMUL_NOFIELD;
2348 LEDsoff();
2349 continue;
2350 } else if (res == 1) {
2351 break; //return value 1 means button press
2352 }
2353
2354 // REQ or WUP request in ANY state and WUP in HALTED state
2355 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2356 selTimer = GetTickCount();
2357 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2358 cardSTATE = MFEMUL_SELECT1;
2359
2360 // init crypto block
2361 LED_B_OFF();
2362 LED_C_OFF();
2363 crypto1_destroy(pcs);
2364 cardAUTHKEY = 0xff;
2365 continue;
2366 }
2367
2368 switch (cardSTATE) {
2369 case MFEMUL_NOFIELD:
2370 case MFEMUL_HALTED:
2371 case MFEMUL_IDLE:{
2372 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2373 break;
2374 }
2375 case MFEMUL_SELECT1:{
2376 // select all
2377 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2378 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2379 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2380 break;
2381 }
2382
2383 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2384 {
2385 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2386 }
2387 // select card
2388 if (len == 9 &&
2389 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2390 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2391 cuid = bytes_to_num(rUIDBCC1, 4);
2392 if (!_7BUID) {
2393 cardSTATE = MFEMUL_WORK;
2394 LED_B_ON();
2395 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2396 break;
2397 } else {
2398 cardSTATE = MFEMUL_SELECT2;
2399 }
2400 }
2401 break;
2402 }
2403 case MFEMUL_AUTH1:{
2404 if( len != 8)
2405 {
2406 cardSTATE_TO_IDLE();
2407 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2408 break;
2409 }
2410 uint32_t ar = bytes_to_num(receivedCmd, 4);
2411 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2412
2413 //Collect AR/NR
2414 if(ar_nr_collected < 2){
2415 if(ar_nr_responses[2] != ar)
2416 {// Avoid duplicates... probably not necessary, ar should vary.
2417 ar_nr_responses[ar_nr_collected*4] = cuid;
2418 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2419 ar_nr_responses[ar_nr_collected*4+2] = ar;
2420 ar_nr_responses[ar_nr_collected*4+3] = nr;
2421 ar_nr_collected++;
2422 }
2423 }
2424
2425 // --- crypto
2426 crypto1_word(pcs, ar , 1);
2427 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2428
2429 // test if auth OK
2430 if (cardRr != prng_successor(nonce, 64)){
2431 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2432 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2433 cardRr, prng_successor(nonce, 64));
2434 // Shouldn't we respond anything here?
2435 // Right now, we don't nack or anything, which causes the
2436 // reader to do a WUPA after a while. /Martin
2437 // -- which is the correct response. /piwi
2438 cardSTATE_TO_IDLE();
2439 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2440 break;
2441 }
2442
2443 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2444
2445 num_to_bytes(ans, 4, rAUTH_AT);
2446 // --- crypto
2447 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2448 LED_C_ON();
2449 cardSTATE = MFEMUL_WORK;
2450 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2451 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2452 GetTickCount() - authTimer);
2453 break;
2454 }
2455 case MFEMUL_SELECT2:{
2456 if (!len) {
2457 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2458 break;
2459 }
2460 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2461 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2462 break;
2463 }
2464
2465 // select 2 card
2466 if (len == 9 &&
2467 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2468 EmSendCmd(rSAK, sizeof(rSAK));
2469 cuid = bytes_to_num(rUIDBCC2, 4);
2470 cardSTATE = MFEMUL_WORK;
2471 LED_B_ON();
2472 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2473 break;
2474 }
2475
2476 // i guess there is a command). go into the work state.
2477 if (len != 4) {
2478 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2479 break;
2480 }
2481 cardSTATE = MFEMUL_WORK;
2482 //goto lbWORK;
2483 //intentional fall-through to the next case-stmt
2484 }
2485
2486 case MFEMUL_WORK:{
2487 if (len == 0) {
2488 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2489 break;
2490 }
2491
2492 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2493
2494 if(encrypted_data) {
2495 // decrypt seqence
2496 mf_crypto1_decrypt(pcs, receivedCmd, len);
2497 }
2498
2499 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2500 authTimer = GetTickCount();
2501 cardAUTHSC = receivedCmd[1] / 4; // received block num
2502 cardAUTHKEY = receivedCmd[0] - 0x60;
2503 crypto1_destroy(pcs);//Added by martin
2504 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2505
2506 if (!encrypted_data) { // first authentication
2507 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2508
2509 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2510 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2511 } else { // nested authentication
2512 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2513 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2514 num_to_bytes(ans, 4, rAUTH_AT);
2515 }
2516 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2517 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2518 cardSTATE = MFEMUL_AUTH1;
2519 break;
2520 }
2521
2522 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2523 // BUT... ACK --> NACK
2524 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2525 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2526 break;
2527 }
2528
2529 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2530 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2531 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2532 break;
2533 }
2534
2535 if(len != 4) {
2536 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2537 break;
2538 }
2539
2540 if(receivedCmd[0] == 0x30 // read block
2541 || receivedCmd[0] == 0xA0 // write block
2542 || receivedCmd[0] == 0xC0 // inc
2543 || receivedCmd[0] == 0xC1 // dec
2544 || receivedCmd[0] == 0xC2 // restore
2545 || receivedCmd[0] == 0xB0) { // transfer
2546 if (receivedCmd[1] >= 16 * 4) {
2547 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2548 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2549 break;
2550 }
2551
2552 if (receivedCmd[1] / 4 != cardAUTHSC) {
2553 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2554 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2555 break;
2556 }
2557 }
2558 // read block
2559 if (receivedCmd[0] == 0x30) {
2560 if (MF_DBGLEVEL >= 4) {
2561 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2562 }
2563 emlGetMem(response, receivedCmd[1], 1);
2564 AppendCrc14443a(response, 16);
2565 mf_crypto1_encrypt(pcs, response, 18, response_par);
2566 EmSendCmdPar(response, 18, response_par);
2567 numReads++;
2568 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2569 Dbprintf("%d reads done, exiting", numReads);
2570 finished = true;
2571 }
2572 break;
2573 }
2574 // write block
2575 if (receivedCmd[0] == 0xA0) {
2576 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2577 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2578 cardSTATE = MFEMUL_WRITEBL2;
2579 cardWRBL = receivedCmd[1];
2580 break;
2581 }
2582 // increment, decrement, restore
2583 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2584 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2585 if (emlCheckValBl(receivedCmd[1])) {
2586 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2587 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2588 break;
2589 }
2590 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2591 if (receivedCmd[0] == 0xC1)
2592 cardSTATE = MFEMUL_INTREG_INC;
2593 if (receivedCmd[0] == 0xC0)
2594 cardSTATE = MFEMUL_INTREG_DEC;
2595 if (receivedCmd[0] == 0xC2)
2596 cardSTATE = MFEMUL_INTREG_REST;
2597 cardWRBL = receivedCmd[1];
2598 break;
2599 }
2600 // transfer
2601 if (receivedCmd[0] == 0xB0) {
2602 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2603 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2604 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2605 else
2606 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2607 break;
2608 }
2609 // halt
2610 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2611 LED_B_OFF();
2612 LED_C_OFF();
2613 cardSTATE = MFEMUL_HALTED;
2614 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2615 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2616 break;
2617 }
2618 // RATS
2619 if (receivedCmd[0] == 0xe0) {//RATS
2620 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2621 break;
2622 }
2623 // command not allowed
2624 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2625 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2626 break;
2627 }
2628 case MFEMUL_WRITEBL2:{
2629 if (len == 18){
2630 mf_crypto1_decrypt(pcs, receivedCmd, len);
2631 emlSetMem(receivedCmd, cardWRBL, 1);
2632 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2633 cardSTATE = MFEMUL_WORK;
2634 } else {
2635 cardSTATE_TO_IDLE();
2636 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2637 }
2638 break;
2639 }
2640
2641 case MFEMUL_INTREG_INC:{
2642 mf_crypto1_decrypt(pcs, receivedCmd, len);
2643 memcpy(&ans, receivedCmd, 4);
2644 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2645 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2646 cardSTATE_TO_IDLE();
2647 break;
2648 }
2649 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2650 cardINTREG = cardINTREG + ans;
2651 cardSTATE = MFEMUL_WORK;
2652 break;
2653 }
2654 case MFEMUL_INTREG_DEC:{
2655 mf_crypto1_decrypt(pcs, receivedCmd, len);
2656 memcpy(&ans, receivedCmd, 4);
2657 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2658 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2659 cardSTATE_TO_IDLE();
2660 break;
2661 }
2662 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2663 cardINTREG = cardINTREG - ans;
2664 cardSTATE = MFEMUL_WORK;
2665 break;
2666 }
2667 case MFEMUL_INTREG_REST:{
2668 mf_crypto1_decrypt(pcs, receivedCmd, len);
2669 memcpy(&ans, receivedCmd, 4);
2670 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2671 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2672 cardSTATE_TO_IDLE();
2673 break;
2674 }
2675 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2676 cardSTATE = MFEMUL_WORK;
2677 break;
2678 }
2679 }
2680 }
2681
2682 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2683 LEDsoff();
2684
2685 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2686 {
2687 //May just aswell send the collected ar_nr in the response aswell
2688 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2689 }
2690
2691 if(flags & FLAG_NR_AR_ATTACK)
2692 {
2693 if(ar_nr_collected > 1) {
2694 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2695 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2696 ar_nr_responses[0], // UID
2697 ar_nr_responses[1], //NT
2698 ar_nr_responses[2], //AR1
2699 ar_nr_responses[3], //NR1
2700 ar_nr_responses[6], //AR2
2701 ar_nr_responses[7] //NR2
2702 );
2703 } else {
2704 Dbprintf("Failed to obtain two AR/NR pairs!");
2705 if(ar_nr_collected >0) {
2706 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2707 ar_nr_responses[0], // UID
2708 ar_nr_responses[1], //NT
2709 ar_nr_responses[2], //AR1
2710 ar_nr_responses[3] //NR1
2711 );
2712 }
2713 }
2714 }
2715 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen);
2716 }
2717
2718
2719
2720 //-----------------------------------------------------------------------------
2721 // MIFARE sniffer.
2722 //
2723 //-----------------------------------------------------------------------------
2724 void RAMFUNC SniffMifare(uint8_t param) {
2725 // param:
2726 // bit 0 - trigger from first card answer
2727 // bit 1 - trigger from first reader 7-bit request
2728
2729 // C(red) A(yellow) B(green)
2730 LEDsoff();
2731 // init trace buffer
2732 iso14a_clear_trace();
2733 iso14a_set_tracing(TRUE);
2734
2735 // The command (reader -> tag) that we're receiving.
2736 // The length of a received command will in most cases be no more than 18 bytes.
2737 // So 32 should be enough!
2738 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
2739 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
2740 // The response (tag -> reader) that we're receiving.
2741 uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
2742 uint8_t *receivedResponsePar = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
2743
2744 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2745 // into trace, along with its length and other annotations.
2746 //uint8_t *trace = (uint8_t *)BigBuf;
2747
2748 // The DMA buffer, used to stream samples from the FPGA
2749 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
2750 uint8_t *data = dmaBuf;
2751 uint8_t previous_data = 0;
2752 int maxDataLen = 0;
2753 int dataLen = 0;
2754 bool ReaderIsActive = FALSE;
2755 bool TagIsActive = FALSE;
2756
2757 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2758
2759 // Set up the demodulator for tag -> reader responses.
2760 DemodInit(receivedResponse, receivedResponsePar);
2761
2762 // Set up the demodulator for the reader -> tag commands
2763 UartInit(receivedCmd, receivedCmdPar);
2764
2765 // Setup for the DMA.
2766 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2767
2768 LED_D_OFF();
2769
2770 // init sniffer
2771 MfSniffInit();
2772
2773 // And now we loop, receiving samples.
2774 for(uint32_t sniffCounter = 0; TRUE; ) {
2775
2776 if(BUTTON_PRESS()) {
2777 DbpString("cancelled by button");
2778 break;
2779 }
2780
2781 LED_A_ON();
2782 WDT_HIT();
2783
2784 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2785 // check if a transaction is completed (timeout after 2000ms).
2786 // if yes, stop the DMA transfer and send what we have so far to the client
2787 if (MfSniffSend(2000)) {
2788 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2789 sniffCounter = 0;
2790 data = dmaBuf;
2791 maxDataLen = 0;
2792 ReaderIsActive = FALSE;
2793 TagIsActive = FALSE;
2794 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2795 }
2796 }
2797
2798 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2799 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2800 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2801 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2802 } else {
2803 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2804 }
2805 // test for length of buffer
2806 if(dataLen > maxDataLen) { // we are more behind than ever...
2807 maxDataLen = dataLen;
2808 if(dataLen > 400) {
2809 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2810 break;
2811 }
2812 }
2813 if(dataLen < 1) continue;
2814
2815 // primary buffer was stopped ( <-- we lost data!
2816 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2817 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2818 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2819 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2820 }
2821 // secondary buffer sets as primary, secondary buffer was stopped
2822 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2823 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2824 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2825 }
2826
2827 LED_A_OFF();
2828
2829 if (sniffCounter & 0x01) {
2830
2831 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2832 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2833 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2834 LED_C_INV();
2835 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
2836
2837 /* And ready to receive another command. */
2838 UartReset();
2839
2840 /* And also reset the demod code */
2841 DemodReset();
2842 }
2843 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2844 }
2845
2846 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2847 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2848 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2849 LED_C_INV();
2850
2851 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
2852
2853 // And ready to receive another response.
2854 DemodReset();
2855 }
2856 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2857 }
2858 }
2859
2860 previous_data = *data;
2861 sniffCounter++;
2862 data++;
2863 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2864 data = dmaBuf;
2865 }
2866
2867 } // main cycle
2868
2869 DbpString("COMMAND FINISHED");
2870
2871 FpgaDisableSscDma();
2872 MfSniffEnd();
2873
2874 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2875 LEDsoff();
2876 }
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