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FIX: The T55x7ReadBlock method, should not have the startgap since it indicats...
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "usb_cdc.h"
20
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76 /* blank r/w tag data stream
77 ...0000000000000000 01111111
78 1010101010101010101010101010101010101010101010101010101010101010
79 0011010010100001
80 01111111
81 101010101010101[0]000...
82
83 [5555fe852c5555555555555555fe0000]
84 */
85 void ReadTItag(void)
86 {
87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
94
95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
178 if (shift3 & (1<<15) ) {
179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x",
206 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
207 if (crc != (shift2&0xffff)) {
208 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
209 } else {
210 DbpString("Info: CRC is good");
211 }
212 }
213 }
214
215 void WriteTIbyte(uint8_t b)
216 {
217 int i = 0;
218
219 // modulate 8 bits out to the antenna
220 for (i=0; i<8; i++)
221 {
222 if (b&(1<<i)) {
223 // stop modulating antenna
224 LOW(GPIO_SSC_DOUT);
225 SpinDelayUs(1000);
226 // modulate antenna
227 HIGH(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 } else {
230 // stop modulating antenna
231 LOW(GPIO_SSC_DOUT);
232 SpinDelayUs(300);
233 // modulate antenna
234 HIGH(GPIO_SSC_DOUT);
235 SpinDelayUs(1700);
236 }
237 }
238 }
239
240 void AcquireTiType(void)
241 {
242 int i, j, n;
243 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
244 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
245 #define TIBUFLEN 1250
246
247 // clear buffer
248 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
249 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
250
251 // Set up the synchronous serial port
252 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
253 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
254
255 // steal this pin from the SSP and use it to control the modulation
256 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
257 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
258
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
261
262 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
263 // 48/2 = 24 MHz clock must be divided by 12
264 AT91C_BASE_SSC->SSC_CMR = 12;
265
266 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
267 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
268 AT91C_BASE_SSC->SSC_TCMR = 0;
269 AT91C_BASE_SSC->SSC_TFMR = 0;
270
271 LED_D_ON();
272
273 // modulate antenna
274 HIGH(GPIO_SSC_DOUT);
275
276 // Charge TI tag for 50ms.
277 SpinDelay(50);
278
279 // stop modulating antenna and listen
280 LOW(GPIO_SSC_DOUT);
281
282 LED_D_OFF();
283
284 i = 0;
285 for(;;) {
286 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
287 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
288 i++; if(i >= TIBUFLEN) break;
289 }
290 WDT_HIT();
291 }
292
293 // return stolen pin to SSP
294 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
295 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
296
297 char *dest = (char *)BigBuf_get_addr();
298 n = TIBUFLEN*32;
299 // unpack buffer
300 for (i=TIBUFLEN-1; i>=0; i--) {
301 for (j=0; j<32; j++) {
302 if(BigBuf[i] & (1 << j)) {
303 dest[--n] = 1;
304 } else {
305 dest[--n] = -1;
306 }
307 }
308 }
309 }
310
311 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
312 // if crc provided, it will be written with the data verbatim (even if bogus)
313 // if not provided a valid crc will be computed from the data and written.
314 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
315 {
316 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
317 if(crc == 0) {
318 crc = update_crc16(crc, (idlo)&0xff);
319 crc = update_crc16(crc, (idlo>>8)&0xff);
320 crc = update_crc16(crc, (idlo>>16)&0xff);
321 crc = update_crc16(crc, (idlo>>24)&0xff);
322 crc = update_crc16(crc, (idhi)&0xff);
323 crc = update_crc16(crc, (idhi>>8)&0xff);
324 crc = update_crc16(crc, (idhi>>16)&0xff);
325 crc = update_crc16(crc, (idhi>>24)&0xff);
326 }
327 Dbprintf("Writing to tag: %x%08x, crc=%x",
328 (unsigned int) idhi, (unsigned int) idlo, crc);
329
330 // TI tags charge at 134.2Khz
331 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
332 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
333 // connects to SSP_DIN and the SSP_DOUT logic level controls
334 // whether we're modulating the antenna (high)
335 // or listening to the antenna (low)
336 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
337 LED_A_ON();
338
339 // steal this pin from the SSP and use it to control the modulation
340 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
341 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
342
343 // writing algorithm:
344 // a high bit consists of a field off for 1ms and field on for 1ms
345 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
346 // initiate a charge time of 50ms (field on) then immediately start writing bits
347 // start by writing 0xBB (keyword) and 0xEB (password)
348 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
349 // finally end with 0x0300 (write frame)
350 // all data is sent lsb firts
351 // finish with 15ms programming time
352
353 // modulate antenna
354 HIGH(GPIO_SSC_DOUT);
355 SpinDelay(50); // charge time
356
357 WriteTIbyte(0xbb); // keyword
358 WriteTIbyte(0xeb); // password
359 WriteTIbyte( (idlo )&0xff );
360 WriteTIbyte( (idlo>>8 )&0xff );
361 WriteTIbyte( (idlo>>16)&0xff );
362 WriteTIbyte( (idlo>>24)&0xff );
363 WriteTIbyte( (idhi )&0xff );
364 WriteTIbyte( (idhi>>8 )&0xff );
365 WriteTIbyte( (idhi>>16)&0xff );
366 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
367 WriteTIbyte( (crc )&0xff ); // crc lo
368 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
369 WriteTIbyte(0x00); // write frame lo
370 WriteTIbyte(0x03); // write frame hi
371 HIGH(GPIO_SSC_DOUT);
372 SpinDelay(50); // programming time
373
374 LED_A_OFF();
375
376 // get TI tag data into the buffer
377 AcquireTiType();
378
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
380 DbpString("Now use 'lf ti read' to check");
381 }
382
383 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
384 {
385 int i;
386 uint8_t *tab = BigBuf_get_addr();
387
388 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
389 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
390
391 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
392
393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
395
396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
398
399 i = 0;
400 for(;;) {
401 //wait until SSC_CLK goes HIGH
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409 if (ledcontrol)
410 LED_D_ON();
411
412 if(tab[i])
413 OPEN_COIL();
414 else
415 SHORT_COIL();
416
417 if (ledcontrol)
418 LED_D_OFF();
419 //wait until SSC_CLK goes LOW
420 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
421 if(BUTTON_PRESS()) {
422 DbpString("Stopped");
423 return;
424 }
425 WDT_HIT();
426 }
427
428 i++;
429 if(i == period) {
430
431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
438 }
439
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor, int t0)
442 {
443 }
444
445 // compose fc/8 fc/10 waveform (FSK2)
446 static void fc(int c, int *n)
447 {
448 uint8_t *dest = BigBuf_get_addr();
449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
462
463 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
477 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 }
491 }
492 }
493 // compose fc/X fc/Y waveform (FSKx)
494 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
495 {
496 uint8_t *dest = BigBuf_get_addr();
497 uint8_t halfFC = fc/2;
498 uint8_t wavesPerClock = clock/fc;
499 uint8_t mod = clock % fc; //modifier
500 uint8_t modAdj = fc/mod; //how often to apply modifier
501 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
502 // loop through clock - step field clock
503 for (uint8_t idx=0; idx < wavesPerClock; idx++){
504 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
506 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
507 *n += fc;
508 }
509 if (mod>0) (*modCnt)++;
510 if ((mod>0) && modAdjOk){ //fsk2
511 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
512 memset(dest+(*n), 0, fc-halfFC);
513 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
514 *n += fc;
515 }
516 }
517 if (mod>0 && !modAdjOk){ //fsk1
518 memset(dest+(*n), 0, mod-(mod/2));
519 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
520 *n += mod;
521 }
522 }
523
524 // prepare a waveform pattern in the buffer based on the ID given then
525 // simulate a HID tag until the button is pressed
526 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
527 {
528 int n=0, i=0;
529 /*
530 HID tag bitstream format
531 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
532 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
533 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
534 A fc8 is inserted before every 4 bits
535 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
536 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
537 */
538
539 if (hi>0xFFF) {
540 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
541 return;
542 }
543 fc(0,&n);
544 // special start of frame marker containing invalid bit sequences
545 fc(8, &n); fc(8, &n); // invalid
546 fc(8, &n); fc(10, &n); // logical 0
547 fc(10, &n); fc(10, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549
550 WDT_HIT();
551 // manchester encode bits 43 to 32
552 for (i=11; i>=0; i--) {
553 if ((i%4)==3) fc(0,&n);
554 if ((hi>>i)&1) {
555 fc(10, &n); fc(8, &n); // low-high transition
556 } else {
557 fc(8, &n); fc(10, &n); // high-low transition
558 }
559 }
560
561 WDT_HIT();
562 // manchester encode bits 31 to 0
563 for (i=31; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((lo>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 if (ledcontrol)
573 LED_A_ON();
574 SimulateTagLowFrequency(n, 0, ledcontrol);
575
576 if (ledcontrol)
577 LED_A_OFF();
578 }
579
580 // prepare a waveform pattern in the buffer based on the ID given then
581 // simulate a FSK tag until the button is pressed
582 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
583 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
584 {
585 int ledcontrol=1;
586 int n=0, i=0;
587 uint8_t fcHigh = arg1 >> 8;
588 uint8_t fcLow = arg1 & 0xFF;
589 uint16_t modCnt = 0;
590 uint8_t clk = arg2 & 0xFF;
591 uint8_t invert = (arg2 >> 8) & 1;
592
593 for (i=0; i<size; i++){
594 if (BitStream[i] == invert){
595 fcAll(fcLow, &n, clk, &modCnt);
596 } else {
597 fcAll(fcHigh, &n, clk, &modCnt);
598 }
599 }
600 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
601 /*Dbprintf("DEBUG: First 32:");
602 uint8_t *dest = BigBuf_get_addr();
603 i=0;
604 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
605 i+=16;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 */
608 if (ledcontrol)
609 LED_A_ON();
610
611 SimulateTagLowFrequency(n, 0, ledcontrol);
612
613 if (ledcontrol)
614 LED_A_OFF();
615 }
616
617 // compose ask waveform for one bit(ASK)
618 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
619 {
620 uint8_t *dest = BigBuf_get_addr();
621 uint8_t halfClk = clock/2;
622 // c = current bit 1 or 0
623 if (manchester==1){
624 memset(dest+(*n), c, halfClk);
625 memset(dest+(*n) + halfClk, c^1, halfClk);
626 } else {
627 memset(dest+(*n), c, clock);
628 }
629 *n += clock;
630 }
631
632 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
633 {
634 uint8_t *dest = BigBuf_get_addr();
635 uint8_t halfClk = clock/2;
636 if (c){
637 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
638 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
639 } else {
640 memset(dest+(*n), c ^ *phase, clock);
641 *phase ^= 1;
642 }
643
644 }
645
646 // args clock, ask/man or askraw, invert, transmission separator
647 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
648 {
649 int ledcontrol = 1;
650 int n=0, i=0;
651 uint8_t clk = (arg1 >> 8) & 0xFF;
652 uint8_t encoding = arg1 & 0xFF;
653 uint8_t separator = arg2 & 1;
654 uint8_t invert = (arg2 >> 8) & 1;
655
656 if (encoding==2){ //biphase
657 uint8_t phase=0;
658 for (i=0; i<size; i++){
659 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
660 }
661 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
662 for (i=0; i<size; i++){
663 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
664 }
665 }
666 } else { // ask/manchester || ask/raw
667 for (i=0; i<size; i++){
668 askSimBit(BitStream[i]^invert, &n, clk, encoding);
669 }
670 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
671 for (i=0; i<size; i++){
672 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
673 }
674 }
675 }
676
677 if (separator==1) Dbprintf("sorry but separator option not yet available");
678
679 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
680 //DEBUG
681 //Dbprintf("First 32:");
682 //uint8_t *dest = BigBuf_get_addr();
683 //i=0;
684 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
685 //i+=16;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687
688 if (ledcontrol)
689 LED_A_ON();
690
691 SimulateTagLowFrequency(n, 0, ledcontrol);
692
693 if (ledcontrol)
694 LED_A_OFF();
695 }
696
697 //carrier can be 2,4 or 8
698 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
699 {
700 uint8_t *dest = BigBuf_get_addr();
701 uint8_t halfWave = waveLen/2;
702 //uint8_t idx;
703 int i = 0;
704 if (phaseChg){
705 // write phase change
706 memset(dest+(*n), *curPhase^1, halfWave);
707 memset(dest+(*n) + halfWave, *curPhase, halfWave);
708 *n += waveLen;
709 *curPhase ^= 1;
710 i += waveLen;
711 }
712 //write each normal clock wave for the clock duration
713 for (; i < clk; i+=waveLen){
714 memset(dest+(*n), *curPhase, halfWave);
715 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
716 *n += waveLen;
717 }
718 }
719
720 // args clock, carrier, invert,
721 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
722 {
723 int ledcontrol=1;
724 int n=0, i=0;
725 uint8_t clk = arg1 >> 8;
726 uint8_t carrier = arg1 & 0xFF;
727 uint8_t invert = arg2 & 0xFF;
728 uint8_t curPhase = 0;
729 for (i=0; i<size; i++){
730 if (BitStream[i] == curPhase){
731 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
732 } else {
733 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
734 }
735 }
736 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
737 //Dbprintf("DEBUG: First 32:");
738 //uint8_t *dest = BigBuf_get_addr();
739 //i=0;
740 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
741 //i+=16;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743
744 if (ledcontrol)
745 LED_A_ON();
746 SimulateTagLowFrequency(n, 0, ledcontrol);
747
748 if (ledcontrol)
749 LED_A_OFF();
750 }
751
752 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
753 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
754 {
755 uint8_t *dest = BigBuf_get_addr();
756 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
757 size_t size = 0;
758 uint32_t hi2=0, hi=0, lo=0;
759 int idx=0;
760 // Configure to go in 125Khz listen mode
761 LFSetupFPGAForADC(95, true);
762
763 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
764
765 WDT_HIT();
766 if (ledcontrol) LED_A_ON();
767
768 DoAcquisition_default(-1,true);
769 // FSK demodulator
770 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
771 size = 50*128*2; //big enough to catch 2 sequences of largest format
772 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
773
774 if (idx>0 && lo>0 && (size==96 || size==192)){
775 // go over previously decoded manchester data and decode into usable tag ID
776 if (hi2 != 0){ //extra large HID tags 88/192 bits
777 Dbprintf("TAG ID: %x%08x%08x (%d)",
778 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
779 }else { //standard HID tags 44/96 bits
780 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
781 uint8_t bitlen = 0;
782 uint32_t fc = 0;
783 uint32_t cardnum = 0;
784 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
785 uint32_t lo2=0;
786 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
787 uint8_t idx3 = 1;
788 while(lo2 > 1){ //find last bit set to 1 (format len bit)
789 lo2=lo2 >> 1;
790 idx3++;
791 }
792 bitlen = idx3+19;
793 fc =0;
794 cardnum=0;
795 if(bitlen == 26){
796 cardnum = (lo>>1)&0xFFFF;
797 fc = (lo>>17)&0xFF;
798 }
799 if(bitlen == 37){
800 cardnum = (lo>>1)&0x7FFFF;
801 fc = ((hi&0xF)<<12)|(lo>>20);
802 }
803 if(bitlen == 34){
804 cardnum = (lo>>1)&0xFFFF;
805 fc= ((hi&1)<<15)|(lo>>17);
806 }
807 if(bitlen == 35){
808 cardnum = (lo>>1)&0xFFFFF;
809 fc = ((hi&1)<<11)|(lo>>21);
810 }
811 }
812 else { //if bit 38 is not set then 37 bit format is used
813 bitlen= 37;
814 fc =0;
815 cardnum=0;
816 if(bitlen==37){
817 cardnum = (lo>>1)&0x7FFFF;
818 fc = ((hi&0xF)<<12)|(lo>>20);
819 }
820 }
821 //Dbprintf("TAG ID: %x%08x (%d)",
822 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
823 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
824 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
825 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
826 }
827 if (findone){
828 if (ledcontrol) LED_A_OFF();
829 *high = hi;
830 *low = lo;
831 return;
832 }
833 // reset
834 }
835 hi2 = hi = lo = idx = 0;
836 WDT_HIT();
837 }
838 DbpString("Stopped");
839 if (ledcontrol) LED_A_OFF();
840 }
841
842 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
843 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
844 {
845 uint8_t *dest = BigBuf_get_addr();
846 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
847 size_t size;
848 int idx=0;
849 // Configure to go in 125Khz listen mode
850 LFSetupFPGAForADC(95, true);
851
852 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
853
854 WDT_HIT();
855 if (ledcontrol) LED_A_ON();
856
857 DoAcquisition_default(-1,true);
858 // FSK demodulator
859 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
860 size = 50*128*2; //big enough to catch 2 sequences of largest format
861 idx = AWIDdemodFSK(dest, &size);
862
863 if (idx>0 && size==96){
864 // Index map
865 // 0 10 20 30 40 50 60
866 // | | | | | | |
867 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
868 // -----------------------------------------------------------------------------
869 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
870 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
871 // |---26 bit---| |-----117----||-------------142-------------|
872 // b = format bit len, o = odd parity of last 3 bits
873 // f = facility code, c = card number
874 // w = wiegand parity
875 // (26 bit format shown)
876
877 //get raw ID before removing parities
878 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
879 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
880 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
881
882 size = removeParity(dest, idx+8, 4, 1, 88);
883 // ok valid card found!
884
885 // Index map
886 // 0 10 20 30 40 50 60
887 // | | | | | | |
888 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
889 // -----------------------------------------------------------------------------
890 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
891 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
892 // |26 bit| |-117--| |-----142------|
893 // b = format bit len, o = odd parity of last 3 bits
894 // f = facility code, c = card number
895 // w = wiegand parity
896 // (26 bit format shown)
897
898 uint32_t fc = 0;
899 uint32_t cardnum = 0;
900 uint32_t code1 = 0;
901 uint32_t code2 = 0;
902 uint8_t fmtLen = bytebits_to_byte(dest,8);
903 if (fmtLen==26){
904 fc = bytebits_to_byte(dest+9, 8);
905 cardnum = bytebits_to_byte(dest+17, 16);
906 code1 = bytebits_to_byte(dest+8,fmtLen);
907 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
908 } else {
909 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
910 if (fmtLen>32){
911 code1 = bytebits_to_byte(dest+8,fmtLen-32);
912 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
913 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
914 } else{
915 code1 = bytebits_to_byte(dest+8,fmtLen);
916 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
917 }
918 }
919 if (findone){
920 if (ledcontrol) LED_A_OFF();
921 return;
922 }
923 // reset
924 }
925 idx = 0;
926 WDT_HIT();
927 }
928 DbpString("Stopped");
929 if (ledcontrol) LED_A_OFF();
930 }
931
932 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
933 {
934 uint8_t *dest = BigBuf_get_addr();
935
936 size_t size=0, idx=0;
937 int clk=0, invert=0, errCnt=0, maxErr=20;
938 uint32_t hi=0;
939 uint64_t lo=0;
940 // Configure to go in 125Khz listen mode
941 LFSetupFPGAForADC(95, true);
942
943 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
944
945 WDT_HIT();
946 if (ledcontrol) LED_A_ON();
947
948 DoAcquisition_default(-1,true);
949 size = BigBuf_max_traceLen();
950 //askdemod and manchester decode
951 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
952 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
953 WDT_HIT();
954
955 if (errCnt<0) continue;
956
957 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
958 if (errCnt){
959 if (size>64){
960 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
961 hi,
962 (uint32_t)(lo>>32),
963 (uint32_t)lo,
964 (uint32_t)(lo&0xFFFF),
965 (uint32_t)((lo>>16LL) & 0xFF),
966 (uint32_t)(lo & 0xFFFFFF));
967 } else {
968 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
969 (uint32_t)(lo>>32),
970 (uint32_t)lo,
971 (uint32_t)(lo&0xFFFF),
972 (uint32_t)((lo>>16LL) & 0xFF),
973 (uint32_t)(lo & 0xFFFFFF));
974 }
975
976 if (findone){
977 if (ledcontrol) LED_A_OFF();
978 *high=lo>>32;
979 *low=lo & 0xFFFFFFFF;
980 return;
981 }
982 }
983 WDT_HIT();
984 hi = lo = size = idx = 0;
985 clk = invert = errCnt = 0;
986 }
987 DbpString("Stopped");
988 if (ledcontrol) LED_A_OFF();
989 }
990
991 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
992 {
993 uint8_t *dest = BigBuf_get_addr();
994 int idx=0;
995 uint32_t code=0, code2=0;
996 uint8_t version=0;
997 uint8_t facilitycode=0;
998 uint16_t number=0;
999 uint8_t crc = 0;
1000 uint16_t calccrc = 0;
1001 // Configure to go in 125Khz listen mode
1002 LFSetupFPGAForADC(95, true);
1003
1004 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1005 WDT_HIT();
1006 if (ledcontrol) LED_A_ON();
1007 DoAcquisition_default(-1,true);
1008 //fskdemod and get start index
1009 WDT_HIT();
1010 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1011 if (idx<0) continue;
1012 //valid tag found
1013
1014 //Index map
1015 //0 10 20 30 40 50 60
1016 //| | | | | | |
1017 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1018 //-----------------------------------------------------------------------------
1019 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1020 //
1021 //Checksum:
1022 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1023 //preamble F0 E0 01 03 B6 75
1024 // How to calc checksum,
1025 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1026 // F0 + E0 + 01 + 03 + B6 = 28A
1027 // 28A & FF = 8A
1028 // FF - 8A = 75
1029 // Checksum: 0x75
1030 //XSF(version)facility:codeone+codetwo
1031 //Handle the data
1032 if(findone){ //only print binary if we are doing one
1033 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1034 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1035 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1036 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1037 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1038 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1039 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1040 }
1041 code = bytebits_to_byte(dest+idx,32);
1042 code2 = bytebits_to_byte(dest+idx+32,32);
1043 version = bytebits_to_byte(dest+idx+27,8); //14,4
1044 facilitycode = bytebits_to_byte(dest+idx+18,8);
1045 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1046
1047 crc = bytebits_to_byte(dest+idx+54,8);
1048 for (uint8_t i=1; i<6; ++i)
1049 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1050 calccrc &= 0xff;
1051 calccrc = 0xff - calccrc;
1052
1053 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1054
1055 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1056 // if we're only looking for one tag
1057 if (findone){
1058 if (ledcontrol) LED_A_OFF();
1059 //LED_A_OFF();
1060 *high=code;
1061 *low=code2;
1062 return;
1063 }
1064 code=code2=0;
1065 version=facilitycode=0;
1066 number=0;
1067 idx=0;
1068
1069 WDT_HIT();
1070 }
1071 DbpString("Stopped");
1072 if (ledcontrol) LED_A_OFF();
1073 }
1074
1075 /*------------------------------
1076 * T5555/T5557/T5567 routines
1077 *------------------------------
1078 */
1079
1080 /* T55x7 configuration register definitions */
1081 #define T55x7_POR_DELAY 0x00000001
1082 #define T55x7_ST_TERMINATOR 0x00000008
1083 #define T55x7_PWD 0x00000010
1084 #define T55x7_MAXBLOCK_SHIFT 5
1085 #define T55x7_AOR 0x00000200
1086 #define T55x7_PSKCF_RF_2 0
1087 #define T55x7_PSKCF_RF_4 0x00000400
1088 #define T55x7_PSKCF_RF_8 0x00000800
1089 #define T55x7_MODULATION_DIRECT 0
1090 #define T55x7_MODULATION_PSK1 0x00001000
1091 #define T55x7_MODULATION_PSK2 0x00002000
1092 #define T55x7_MODULATION_PSK3 0x00003000
1093 #define T55x7_MODULATION_FSK1 0x00004000
1094 #define T55x7_MODULATION_FSK2 0x00005000
1095 #define T55x7_MODULATION_FSK1a 0x00006000
1096 #define T55x7_MODULATION_FSK2a 0x00007000
1097 #define T55x7_MODULATION_MANCHESTER 0x00008000
1098 #define T55x7_MODULATION_BIPHASE 0x00010000
1099 //#define T55x7_MODULATION_BIPHASE57 0x00011000
1100 #define T55x7_BITRATE_RF_8 0
1101 #define T55x7_BITRATE_RF_16 0x00040000
1102 #define T55x7_BITRATE_RF_32 0x00080000
1103 #define T55x7_BITRATE_RF_40 0x000C0000
1104 #define T55x7_BITRATE_RF_50 0x00100000
1105 #define T55x7_BITRATE_RF_64 0x00140000
1106 #define T55x7_BITRATE_RF_100 0x00180000
1107 #define T55x7_BITRATE_RF_128 0x001C0000
1108
1109 /* T5555 (Q5) configuration register definitions */
1110 #define T5555_ST_TERMINATOR 0x00000001
1111 #define T5555_MAXBLOCK_SHIFT 0x00000001
1112 #define T5555_MODULATION_MANCHESTER 0
1113 #define T5555_MODULATION_PSK1 0x00000010
1114 #define T5555_MODULATION_PSK2 0x00000020
1115 #define T5555_MODULATION_PSK3 0x00000030
1116 #define T5555_MODULATION_FSK1 0x00000040
1117 #define T5555_MODULATION_FSK2 0x00000050
1118 #define T5555_MODULATION_BIPHASE 0x00000060
1119 #define T5555_MODULATION_DIRECT 0x00000070
1120 #define T5555_INVERT_OUTPUT 0x00000080
1121 #define T5555_PSK_RF_2 0
1122 #define T5555_PSK_RF_4 0x00000100
1123 #define T5555_PSK_RF_8 0x00000200
1124 #define T5555_USE_PWD 0x00000400
1125 #define T5555_USE_AOR 0x00000800
1126 #define T5555_BITRATE_SHIFT 12
1127 #define T5555_FAST_WRITE 0x00004000
1128 #define T5555_PAGE_SELECT 0x00008000
1129
1130 /*
1131 * Relevant times in microsecond
1132 * To compensate antenna falling times shorten the write times
1133 * and enlarge the gap ones.
1134 */
1135
1136 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1137 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1138 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1139 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1140
1141 // VALUES TAKEN FROM EM4x function: SendForward
1142 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1143 // WRITE_GAP = 128; (16*8)
1144 // WRITE_1 = 256 32*8; (32*8)
1145
1146 // These timings work for 4469/4269/4305 (with the 55*8 above)
1147 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1148
1149 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1150 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1151 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1152 // T0 = TIMER_CLOCK1 / 125000 = 192
1153 // 1 Cycle = 8 microseconds(us)
1154
1155 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1156
1157 // Write one bit to card
1158 void T55xxWriteBit(int bit)
1159 {
1160 //FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1161 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1162 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1163 if (!bit)
1164 SpinDelayUs(WRITE_0);
1165 else
1166 SpinDelayUs(WRITE_1);
1167 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1168 SpinDelayUs(WRITE_GAP);
1169 }
1170
1171 // Write one card block in page 0, no lock
1172 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1173 {
1174 uint32_t i = 0;
1175
1176 // Set up FPGA, 125kHz
1177 // Wait for config.. (192+8190xPOW)x8 == 67ms
1178 LFSetupFPGAForADC(0, true);
1179
1180 // Now start writting
1181 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1182 SpinDelayUs(START_GAP);
1183
1184 // Opcode
1185 T55xxWriteBit(1);
1186 T55xxWriteBit(0); //Page 0
1187 if (PwdMode == 1){
1188 // Pwd
1189 for (i = 0x80000000; i != 0; i >>= 1)
1190 T55xxWriteBit(Pwd & i);
1191 }
1192 // Lock bit
1193 T55xxWriteBit(0);
1194
1195 // Data
1196 for (i = 0x80000000; i != 0; i >>= 1)
1197 T55xxWriteBit(Data & i);
1198
1199 // Block
1200 for (i = 0x04; i != 0; i >>= 1)
1201 T55xxWriteBit(Block & i);
1202
1203 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1204 // so wait a little more)
1205 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1206 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1207 SpinDelay(20);
1208 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1209 }
1210
1211 void TurnReadLFOn(){
1212 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1213 // Give it a bit of time for the resonant antenna to settle.
1214 SpinDelayUs(300);
1215 }
1216
1217
1218 // Read one card block in page 0
1219 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1220 {
1221 uint32_t i = 0;
1222 uint8_t *dest = BigBuf_get_addr();
1223 uint16_t bufferlength = BigBuf_max_traceLen();
1224 if ( bufferlength > T55xx_SAMPLES_SIZE )
1225 bufferlength = T55xx_SAMPLES_SIZE;
1226
1227 // Clear destination buffer before sending the command
1228 memset(dest, 0x80, bufferlength);
1229
1230 // Set up FPGA, 125kHz
1231 // Wait for config.. (192+8190xPOW)x8 == 67ms
1232 //LFSetupFPGAForADC(0, true);
1233 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1234 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1235 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1236
1237 // Connect the A/D to the peak-detected low-frequency path.
1238 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1239
1240 // Now set up the SSC to get the ADC samples that are now streaming at us.
1241 FpgaSetupSsc();
1242
1243 // Give it a bit of time for the resonant antenna to settle.
1244 //SpinDelayUs(8*200); //192FC
1245 SpinDelay(50);
1246
1247 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1248 //SpinDelayUs(START_GAP);
1249
1250 // Opcode
1251 T55xxWriteBit(1);
1252 T55xxWriteBit(0); //Page 0
1253 if (PwdMode == 1){
1254 // Pwd
1255 for (i = 0x80000000; i != 0; i >>= 1)
1256 T55xxWriteBit(Pwd & i);
1257 }
1258 // Lock bit
1259 T55xxWriteBit(0);
1260 // Block
1261 for (i = 0x04; i != 0; i >>= 1)
1262 T55xxWriteBit(Block & i);
1263
1264 // Turn field on to read the response
1265 TurnReadLFOn();
1266 // Now do the acquisition
1267 i = 0;
1268 for(;;) {
1269 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1270 AT91C_BASE_SSC->SSC_THR = 0x43;
1271 LED_D_ON();
1272 }
1273 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1274 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1275 i++;
1276 LED_D_OFF();
1277 if (i >= bufferlength) break;
1278 }
1279 }
1280
1281 cmd_send(CMD_ACK,0,0,0,0,0);
1282 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1283 LED_D_OFF();
1284 }
1285
1286 // Read card traceability data (page 1)
1287 void T55xxReadTrace(void){
1288
1289 uint32_t i = 0;
1290 uint8_t *dest = BigBuf_get_addr();
1291 uint16_t bufferlength = BigBuf_max_traceLen();
1292 if ( bufferlength > T55xx_SAMPLES_SIZE )
1293 bufferlength= T55xx_SAMPLES_SIZE;
1294
1295 // Clear destination buffer before sending the command
1296 memset(dest, 0x80, bufferlength);
1297
1298 LFSetupFPGAForADC(0, true);
1299 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1300 SpinDelayUs(START_GAP);
1301
1302 // Opcode
1303 T55xxWriteBit(1);
1304 T55xxWriteBit(1); //Page 1
1305
1306 // Turn field on to read the response
1307 TurnReadLFOn();
1308
1309 // Now do the acquisition
1310 for(;;) {
1311 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1312 AT91C_BASE_SSC->SSC_THR = 0x43;
1313 LED_D_ON();
1314 }
1315 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1316 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1317 i++;
1318 LED_D_OFF();
1319
1320 if (i >= bufferlength) break;
1321 }
1322 }
1323
1324 cmd_send(CMD_ACK,0,0,0,0,0);
1325 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1326 LED_D_OFF();
1327 }
1328
1329 /*-------------- Cloning routines -----------*/
1330 // Copy HID id to card and setup block 0 config
1331 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1332 {
1333 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1334 int last_block = 0;
1335
1336 if (longFMT){
1337 // Ensure no more than 84 bits supplied
1338 if (hi2>0xFFFFF) {
1339 DbpString("Tags can only have 84 bits.");
1340 return;
1341 }
1342 // Build the 6 data blocks for supplied 84bit ID
1343 last_block = 6;
1344 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1345 for (int i=0;i<4;i++) {
1346 if (hi2 & (1<<(19-i)))
1347 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1348 else
1349 data1 |= (1<<((3-i)*2)); // 0 -> 01
1350 }
1351
1352 data2 = 0;
1353 for (int i=0;i<16;i++) {
1354 if (hi2 & (1<<(15-i)))
1355 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1356 else
1357 data2 |= (1<<((15-i)*2)); // 0 -> 01
1358 }
1359
1360 data3 = 0;
1361 for (int i=0;i<16;i++) {
1362 if (hi & (1<<(31-i)))
1363 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1364 else
1365 data3 |= (1<<((15-i)*2)); // 0 -> 01
1366 }
1367
1368 data4 = 0;
1369 for (int i=0;i<16;i++) {
1370 if (hi & (1<<(15-i)))
1371 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1372 else
1373 data4 |= (1<<((15-i)*2)); // 0 -> 01
1374 }
1375
1376 data5 = 0;
1377 for (int i=0;i<16;i++) {
1378 if (lo & (1<<(31-i)))
1379 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1380 else
1381 data5 |= (1<<((15-i)*2)); // 0 -> 01
1382 }
1383
1384 data6 = 0;
1385 for (int i=0;i<16;i++) {
1386 if (lo & (1<<(15-i)))
1387 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1388 else
1389 data6 |= (1<<((15-i)*2)); // 0 -> 01
1390 }
1391 }
1392 else {
1393 // Ensure no more than 44 bits supplied
1394 if (hi>0xFFF) {
1395 DbpString("Tags can only have 44 bits.");
1396 return;
1397 }
1398
1399 // Build the 3 data blocks for supplied 44bit ID
1400 last_block = 3;
1401
1402 data1 = 0x1D000000; // load preamble
1403
1404 for (int i=0;i<12;i++) {
1405 if (hi & (1<<(11-i)))
1406 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1407 else
1408 data1 |= (1<<((11-i)*2)); // 0 -> 01
1409 }
1410
1411 data2 = 0;
1412 for (int i=0;i<16;i++) {
1413 if (lo & (1<<(31-i)))
1414 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1415 else
1416 data2 |= (1<<((15-i)*2)); // 0 -> 01
1417 }
1418
1419 data3 = 0;
1420 for (int i=0;i<16;i++) {
1421 if (lo & (1<<(15-i)))
1422 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1423 else
1424 data3 |= (1<<((15-i)*2)); // 0 -> 01
1425 }
1426 }
1427
1428 LED_D_ON();
1429 // Program the data blocks for supplied ID
1430 // and the block 0 for HID format
1431 T55xxWriteBlock(data1,1,0,0);
1432 T55xxWriteBlock(data2,2,0,0);
1433 T55xxWriteBlock(data3,3,0,0);
1434
1435 if (longFMT) { // if long format there are 6 blocks
1436 T55xxWriteBlock(data4,4,0,0);
1437 T55xxWriteBlock(data5,5,0,0);
1438 T55xxWriteBlock(data6,6,0,0);
1439 }
1440
1441 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1442 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1443 T55x7_MODULATION_FSK2a |
1444 last_block << T55x7_MAXBLOCK_SHIFT,
1445 0,0,0);
1446
1447 LED_D_OFF();
1448
1449 DbpString("DONE!");
1450 }
1451
1452 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1453 {
1454 int data1=0, data2=0; //up to six blocks for long format
1455
1456 data1 = hi; // load preamble
1457 data2 = lo;
1458
1459 LED_D_ON();
1460 // Program the data blocks for supplied ID
1461 // and the block 0 for HID format
1462 T55xxWriteBlock(data1,1,0,0);
1463 T55xxWriteBlock(data2,2,0,0);
1464
1465 //Config Block
1466 T55xxWriteBlock(0x00147040,0,0,0);
1467 LED_D_OFF();
1468
1469 DbpString("DONE!");
1470 }
1471
1472 // Define 9bit header for EM410x tags
1473 #define EM410X_HEADER 0x1FF
1474 #define EM410X_ID_LENGTH 40
1475
1476 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1477 {
1478 int i, id_bit;
1479 uint64_t id = EM410X_HEADER;
1480 uint64_t rev_id = 0; // reversed ID
1481 int c_parity[4]; // column parity
1482 int r_parity = 0; // row parity
1483 uint32_t clock = 0;
1484
1485 // Reverse ID bits given as parameter (for simpler operations)
1486 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1487 if (i < 32) {
1488 rev_id = (rev_id << 1) | (id_lo & 1);
1489 id_lo >>= 1;
1490 } else {
1491 rev_id = (rev_id << 1) | (id_hi & 1);
1492 id_hi >>= 1;
1493 }
1494 }
1495
1496 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1497 id_bit = rev_id & 1;
1498
1499 if (i % 4 == 0) {
1500 // Don't write row parity bit at start of parsing
1501 if (i)
1502 id = (id << 1) | r_parity;
1503 // Start counting parity for new row
1504 r_parity = id_bit;
1505 } else {
1506 // Count row parity
1507 r_parity ^= id_bit;
1508 }
1509
1510 // First elements in column?
1511 if (i < 4)
1512 // Fill out first elements
1513 c_parity[i] = id_bit;
1514 else
1515 // Count column parity
1516 c_parity[i % 4] ^= id_bit;
1517
1518 // Insert ID bit
1519 id = (id << 1) | id_bit;
1520 rev_id >>= 1;
1521 }
1522
1523 // Insert parity bit of last row
1524 id = (id << 1) | r_parity;
1525
1526 // Fill out column parity at the end of tag
1527 for (i = 0; i < 4; ++i)
1528 id = (id << 1) | c_parity[i];
1529
1530 // Add stop bit
1531 id <<= 1;
1532
1533 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1534 LED_D_ON();
1535
1536 // Write EM410x ID
1537 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1538 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1539
1540 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1541 if (card) {
1542 // Clock rate is stored in bits 8-15 of the card value
1543 clock = (card & 0xFF00) >> 8;
1544 Dbprintf("Clock rate: %d", clock);
1545 switch (clock)
1546 {
1547 case 32:
1548 clock = T55x7_BITRATE_RF_32;
1549 break;
1550 case 16:
1551 clock = T55x7_BITRATE_RF_16;
1552 break;
1553 case 0:
1554 // A value of 0 is assumed to be 64 for backwards-compatibility
1555 // Fall through...
1556 case 64:
1557 clock = T55x7_BITRATE_RF_64;
1558 break;
1559 default:
1560 Dbprintf("Invalid clock rate: %d", clock);
1561 return;
1562 }
1563
1564 // Writing configuration for T55x7 tag
1565 T55xxWriteBlock(clock |
1566 T55x7_MODULATION_MANCHESTER |
1567 2 << T55x7_MAXBLOCK_SHIFT,
1568 0, 0, 0);
1569 }
1570 else
1571 // Writing configuration for T5555(Q5) tag
1572 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1573 T5555_MODULATION_MANCHESTER |
1574 2 << T5555_MAXBLOCK_SHIFT,
1575 0, 0, 0);
1576
1577 LED_D_OFF();
1578 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1579 (uint32_t)(id >> 32), (uint32_t)id);
1580 }
1581
1582 // Clone Indala 64-bit tag by UID to T55x7
1583 void CopyIndala64toT55x7(int hi, int lo)
1584 {
1585
1586 //Program the 2 data blocks for supplied 64bit UID
1587 // and the block 0 for Indala64 format
1588 T55xxWriteBlock(hi,1,0,0);
1589 T55xxWriteBlock(lo,2,0,0);
1590 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1591 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1592 T55x7_MODULATION_PSK1 |
1593 2 << T55x7_MAXBLOCK_SHIFT,
1594 0, 0, 0);
1595 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1596 // T5567WriteBlock(0x603E1042,0);
1597
1598 DbpString("DONE!");
1599
1600 }
1601
1602 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1603 {
1604
1605 //Program the 7 data blocks for supplied 224bit UID
1606 // and the block 0 for Indala224 format
1607 T55xxWriteBlock(uid1,1,0,0);
1608 T55xxWriteBlock(uid2,2,0,0);
1609 T55xxWriteBlock(uid3,3,0,0);
1610 T55xxWriteBlock(uid4,4,0,0);
1611 T55xxWriteBlock(uid5,5,0,0);
1612 T55xxWriteBlock(uid6,6,0,0);
1613 T55xxWriteBlock(uid7,7,0,0);
1614 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1615 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1616 T55x7_MODULATION_PSK1 |
1617 7 << T55x7_MAXBLOCK_SHIFT,
1618 0,0,0);
1619 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1620 // T5567WriteBlock(0x603E10E2,0);
1621
1622 DbpString("DONE!");
1623
1624 }
1625
1626 //-----------------------------------
1627 // EM4469 / EM4305 routines
1628 //-----------------------------------
1629 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1630 #define FWD_CMD_WRITE 0xA
1631 #define FWD_CMD_READ 0x9
1632 #define FWD_CMD_DISABLE 0x5
1633
1634
1635 uint8_t forwardLink_data[64]; //array of forwarded bits
1636 uint8_t * forward_ptr; //ptr for forward message preparation
1637 uint8_t fwd_bit_sz; //forwardlink bit counter
1638 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1639
1640 //====================================================================
1641 // prepares command bits
1642 // see EM4469 spec
1643 //====================================================================
1644 //--------------------------------------------------------------------
1645 uint8_t Prepare_Cmd( uint8_t cmd ) {
1646 //--------------------------------------------------------------------
1647
1648 *forward_ptr++ = 0; //start bit
1649 *forward_ptr++ = 0; //second pause for 4050 code
1650
1651 *forward_ptr++ = cmd;
1652 cmd >>= 1;
1653 *forward_ptr++ = cmd;
1654 cmd >>= 1;
1655 *forward_ptr++ = cmd;
1656 cmd >>= 1;
1657 *forward_ptr++ = cmd;
1658
1659 return 6; //return number of emited bits
1660 }
1661
1662 //====================================================================
1663 // prepares address bits
1664 // see EM4469 spec
1665 //====================================================================
1666
1667 //--------------------------------------------------------------------
1668 uint8_t Prepare_Addr( uint8_t addr ) {
1669 //--------------------------------------------------------------------
1670
1671 register uint8_t line_parity;
1672
1673 uint8_t i;
1674 line_parity = 0;
1675 for(i=0;i<6;i++) {
1676 *forward_ptr++ = addr;
1677 line_parity ^= addr;
1678 addr >>= 1;
1679 }
1680
1681 *forward_ptr++ = (line_parity & 1);
1682
1683 return 7; //return number of emited bits
1684 }
1685
1686 //====================================================================
1687 // prepares data bits intreleaved with parity bits
1688 // see EM4469 spec
1689 //====================================================================
1690
1691 //--------------------------------------------------------------------
1692 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1693 //--------------------------------------------------------------------
1694
1695 register uint8_t line_parity;
1696 register uint8_t column_parity;
1697 register uint8_t i, j;
1698 register uint16_t data;
1699
1700 data = data_low;
1701 column_parity = 0;
1702
1703 for(i=0; i<4; i++) {
1704 line_parity = 0;
1705 for(j=0; j<8; j++) {
1706 line_parity ^= data;
1707 column_parity ^= (data & 1) << j;
1708 *forward_ptr++ = data;
1709 data >>= 1;
1710 }
1711 *forward_ptr++ = line_parity;
1712 if(i == 1)
1713 data = data_hi;
1714 }
1715
1716 for(j=0; j<8; j++) {
1717 *forward_ptr++ = column_parity;
1718 column_parity >>= 1;
1719 }
1720 *forward_ptr = 0;
1721
1722 return 45; //return number of emited bits
1723 }
1724
1725 //====================================================================
1726 // Forward Link send function
1727 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1728 // fwd_bit_count set with number of bits to be sent
1729 //====================================================================
1730 void SendForward(uint8_t fwd_bit_count) {
1731
1732 fwd_write_ptr = forwardLink_data;
1733 fwd_bit_sz = fwd_bit_count;
1734
1735 LED_D_ON();
1736
1737 //Field on
1738 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1739 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1740 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1741
1742 // Give it a bit of time for the resonant antenna to settle.
1743 // And for the tag to fully power up
1744 SpinDelay(150);
1745
1746 // force 1st mod pulse (start gap must be longer for 4305)
1747 fwd_bit_sz--; //prepare next bit modulation
1748 fwd_write_ptr++;
1749 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1750 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1751 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1752 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1753 SpinDelayUs(16*8); //16 cycles on (8us each)
1754
1755 // now start writting
1756 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1757 if(((*fwd_write_ptr++) & 1) == 1)
1758 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1759 else {
1760 //These timings work for 4469/4269/4305 (with the 55*8 above)
1761 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1762 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1763 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1764 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1765 SpinDelayUs(9*8); //16 cycles on (8us each)
1766 }
1767 }
1768 }
1769
1770 void EM4xLogin(uint32_t Password) {
1771
1772 uint8_t fwd_bit_count;
1773
1774 forward_ptr = forwardLink_data;
1775 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1776 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1777
1778 SendForward(fwd_bit_count);
1779
1780 //Wait for command to complete
1781 SpinDelay(20);
1782
1783 }
1784
1785 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1786
1787 uint8_t *dest = BigBuf_get_addr();
1788 uint16_t bufferlength = BigBuf_max_traceLen();
1789 uint32_t i = 0;
1790
1791 // Clear destination buffer before sending the command 0x80 = average.
1792 memset(dest, 0x80, bufferlength);
1793
1794 uint8_t fwd_bit_count;
1795
1796 //If password mode do login
1797 if (PwdMode == 1) EM4xLogin(Pwd);
1798
1799 forward_ptr = forwardLink_data;
1800 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1801 fwd_bit_count += Prepare_Addr( Address );
1802
1803 // Connect the A/D to the peak-detected low-frequency path.
1804 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1805 // Now set up the SSC to get the ADC samples that are now streaming at us.
1806 FpgaSetupSsc();
1807
1808 SendForward(fwd_bit_count);
1809
1810 // Now do the acquisition
1811 i = 0;
1812 for(;;) {
1813 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1814 AT91C_BASE_SSC->SSC_THR = 0x43;
1815 }
1816 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1817 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1818 ++i;
1819 if (i >= bufferlength) break;
1820 }
1821 }
1822
1823 cmd_send(CMD_ACK,0,0,0,0,0);
1824 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1825 LED_D_OFF();
1826 }
1827
1828 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1829
1830 uint8_t fwd_bit_count;
1831
1832 //If password mode do login
1833 if (PwdMode == 1) EM4xLogin(Pwd);
1834
1835 forward_ptr = forwardLink_data;
1836 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1837 fwd_bit_count += Prepare_Addr( Address );
1838 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1839
1840 SendForward(fwd_bit_count);
1841
1842 //Wait for write to complete
1843 SpinDelay(20);
1844 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1845 LED_D_OFF();
1846 }
1847
1848 void CopyViKingtoT55x7(uint32_t block1,uint32_t block2) {
1849 LED_D_ON();
1850 T55xxWriteBlock(block1,1,0,0);
1851 T55xxWriteBlock(block2,2,0,0);
1852
1853 T55xxWriteBlock(T55x7_MODULATION_MANCHESTER | T55x7_BITRATE_RF_32 | 2 << T5555_MAXBLOCK_SHIFT,0,0,1);
1854 LED_D_OFF();
1855 DbpString("DONE!");
1856 }
1857
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