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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, Sept 2005
3 // Iceman, Sept 2016
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // Timers, Clocks functions used in LF or Legic where you would need detailed time.
10 //-----------------------------------------------------------------------------
11 #include "ticks.h"
12
13 // attempt at high resolution microsecond timer
14 // beware: timer counts in 21.3uS increments (1024/48Mhz)
15 void SpinDelayUs(int us) {
16 int ticks = (48 * us) >> 10;
17
18 // Borrow a PWM unit for my real-time clock
19 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
20
21 // 48 MHz / 1024 gives 46.875 kHz
22 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
23 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
24 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
25
26 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
27
28 for(;;) {
29 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
30 if (now == (uint16_t)(start + ticks))
31 return;
32
33 WDT_HIT();
34 }
35 }
36
37 void SpinDelay(int ms) {
38 // convert to uS and call microsecond delay function
39 SpinDelayUs(ms*1000);
40 }
41 // -------------------------------------------------------------------------
42 // timer lib
43 // -------------------------------------------------------------------------
44 // test procedure:
45 //
46 // ti = GetTickCount();
47 // SpinDelay(1000);
48 // ti = GetTickCount() - ti;
49 // Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
50 void StartTickCount(void) {
51 // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
52 // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
53 uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
54 // set RealTimeCounter divider to count at 1kHz:
55 AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
56 // note: worst case precision is approx 2.5%
57 }
58
59 /*
60 * Get the current count.
61 */
62 uint32_t RAMFUNC GetTickCount(void){
63 return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
64 }
65
66 // -------------------------------------------------------------------------
67 // microseconds timer
68 // -------------------------------------------------------------------------
69 void StartCountUS(void) {
70 AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14);
71 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
72
73 // fast clock
74 // tick=1.5mks
75 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
76 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
77 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
78 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
79 AT91C_BASE_TC0->TC_RA = 1;
80 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
81
82 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
83 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
84
85 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
86 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
87 AT91C_BASE_TCB->TCB_BCR = 1;
88
89 while (AT91C_BASE_TC1->TC_CV >= 1);
90 }
91
92 uint32_t RAMFUNC GetCountUS(void){
93 //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
94 // By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
95 return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
96 }
97
98
99 // -------------------------------------------------------------------------
100 // Timer for iso14443 commands. Uses ssp_clk from FPGA
101 // -------------------------------------------------------------------------
102 void StartCountSspClk(void) {
103 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
104 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
105 | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
106 | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
107
108 // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
109 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
110 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
111 | AT91C_TC_CPCSTOP // Stop clock on RC compare
112 | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
113 | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
114 | AT91C_TC_ENETRG // Enable external trigger event
115 | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
116 | AT91C_TC_WAVE // Waveform Mode
117 | AT91C_TC_AEEVT_SET // Set TIOA1 on external event
118 | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
119 AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
120
121 // use TC0 to count TIOA1 pulses
122 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
123 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
124 | AT91C_TC_WAVE // Waveform Mode
125 | AT91C_TC_WAVESEL_UP // just count
126 | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
127 | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
128 AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
129 AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
130
131 // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
132 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
133 AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
134 | AT91C_TC_WAVE // Waveform Mode
135 | AT91C_TC_WAVESEL_UP; // just count
136
137 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC0
138 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC1
139 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // enable and reset TC2
140
141 // synchronize the counter with the ssp_frame signal.
142 // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present
143 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
144 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
145 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
146
147 // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
148 // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
149 AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
150 // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
151 // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
152 // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
153 // (just started with the transfer of the 4th Bit).
154
155 // The high word of the counter (TC2) will not reset until the low word (TC0) overflows.
156 // Therefore need to wait quite some time before we can use the counter.
157 while (AT91C_BASE_TC2->TC_CV >= 1);
158 }
159 void ResetSspClk(void) {
160 //enable clock of timer and software trigger
161 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
162 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
163 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
164 while (AT91C_BASE_TC2->TC_CV >= 1);
165 }
166
167 uint32_t RAMFUNC GetCountSspClk(void) {
168 uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
169 if ((tmp_count & 0x0000ffff) == 0) //small chance that we may have missed an increment in TC2
170 return (AT91C_BASE_TC2->TC_CV << 16);
171 return tmp_count;
172 }
173
174
175 // -------------------------------------------------------------------------
176 // Timer for bitbanging, or LF stuff when you need a very precis timer
177 // 1us = 1.5ticks
178 // -------------------------------------------------------------------------
179 void StartTicks(void){
180 //initialization of the timer
181 // tc1 is higher 0xFFFF0000
182 // tc0 is lower 0x0000FFFF
183 AT91C_BASE_PMC->PMC_PCER |= (1 << 12) | (1 << 13) | (1 << 14);
184 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
185 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
186 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
187 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
188 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
189 AT91C_BASE_TC0->TC_RA = 1;
190 AT91C_BASE_TC0->TC_RC = 0;
191
192 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
193 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from TC0
194
195 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
196 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
197 AT91C_BASE_TCB->TCB_BCR = 1;
198
199 // wait until timer becomes zero.
200 while (AT91C_BASE_TC1->TC_CV >= 1);
201 }
202 // Wait - Spindelay in ticks.
203 // if called with a high number, this will trigger the WDT...
204 void WaitTicks(uint32_t ticks){
205 if ( ticks == 0 ) return;
206 ticks += GET_TICKS;
207 while (GET_TICKS < ticks);
208 }
209 // Wait / Spindelay in us (microseconds)
210 // 1us = 1.5ticks.
211 void WaitUS(uint16_t us){
212 if ( us == 0 ) return;
213 WaitTicks( (uint32_t)(us * 1.5) );
214 }
215 void WaitMS(uint16_t ms){
216 if (ms == 0) return;
217 WaitTicks( (uint32_t)(ms * 1500) );
218 }
219 // Starts Clock and waits until its reset
220 void ResetTicks(void){
221 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
222 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
223 while (AT91C_BASE_TC1->TC_CV >= 1);
224 }
225 void ResetTimer(AT91PS_TC timer){
226 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
227 while(timer->TC_CV >= 1) ;
228 }
229 // stop clock
230 void StopTicks(void){
231 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
232 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
233 }
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