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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to support ISO 14443B. This includes both the reader software and
9 // the `fake tag' modes.
10 //-----------------------------------------------------------------------------
11 #include "iso14443b.h"
12
13 #ifndef FWT_TIMEOUT_14B
14 // defaults to 2000ms
15 # define FWT_TIMEOUT_14B 35312
16 #endif
17 #ifndef ISO14443B_DMA_BUFFER_SIZE
18 # define ISO14443B_DMA_BUFFER_SIZE 256
19 #endif
20 #ifndef RECEIVE_MASK
21 # define RECEIVE_MASK (ISO14443B_DMA_BUFFER_SIZE-1)
22 #endif
23
24 // Guard Time (per 14443-2)
25 #ifndef TR0
26 # define TR0 0
27 #endif
28
29 // Synchronization time (per 14443-2)
30 #ifndef TR1
31 # define TR1 0
32 #endif
33 // Frame Delay Time PICC to PCD (per 14443-3 Amendment 1)
34 #ifndef TR2
35 # define TR2 0
36 #endif
37
38 // 4sample
39 #define SEND4STUFFBIT(x) ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);
40 //#define SEND4STUFFBIT(x) ToSendStuffBit(x);
41 // iceman, this threshold value, what makes 8 a good amplituted for this IQ values?
42 #ifndef SUBCARRIER_DETECT_THRESHOLD
43 # define SUBCARRIER_DETECT_THRESHOLD 6
44 #endif
45
46 static void iso14b_set_timeout(uint32_t timeout);
47 static void iso14b_set_maxframesize(uint16_t size);
48 static void switch_off(void);
49
50 // the block number for the ISO14443-4 PCB (used with APDUs)
51 static uint8_t pcb_blocknum = 0;
52 static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
53
54
55 //=============================================================================
56 // An ISO 14443 Type B tag. We listen for commands from the reader, using
57 // a UART kind of thing that's implemented in software. When we get a
58 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
59 // If it's good, then we can do something appropriate with it, and send
60 // a response.
61 //=============================================================================
62
63
64 //-----------------------------------------------------------------------------
65 // The software UART that receives commands from the reader, and its state variables.
66 //-----------------------------------------------------------------------------
67 static struct {
68 enum {
69 STATE_UNSYNCD,
70 STATE_GOT_FALLING_EDGE_OF_SOF,
71 STATE_AWAITING_START_BIT,
72 STATE_RECEIVING_DATA
73 } state;
74 uint16_t shiftReg;
75 int bitCnt;
76 int byteCnt;
77 int byteCntMax;
78 int posCnt;
79 uint8_t *output;
80 } Uart;
81
82 static void UartReset() {
83 Uart.state = STATE_UNSYNCD;
84 Uart.shiftReg = 0;
85 Uart.bitCnt = 0;
86 Uart.byteCnt = 0;
87 Uart.byteCntMax = MAX_FRAME_SIZE;
88 Uart.posCnt = 0;
89 }
90
91 static void UartInit(uint8_t *data) {
92 Uart.output = data;
93 UartReset();
94 // memset(Uart.output, 0x00, MAX_FRAME_SIZE);
95 }
96
97 //-----------------------------------------------------------------------------
98 // The software Demod that receives commands from the tag, and its state variables.
99 //-----------------------------------------------------------------------------
100 static struct {
101 enum {
102 DEMOD_UNSYNCD,
103 DEMOD_PHASE_REF_TRAINING,
104 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
105 DEMOD_GOT_FALLING_EDGE_OF_SOF,
106 DEMOD_AWAITING_START_BIT,
107 DEMOD_RECEIVING_DATA
108 } state;
109 uint16_t bitCount;
110 int posCount;
111 int thisBit;
112 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
113 int metric;
114 int metricN;
115 */
116 uint16_t shiftReg;
117 uint8_t *output;
118 uint16_t len;
119 int sumI;
120 int sumQ;
121 uint32_t startTime, endTime;
122 } Demod;
123
124 // Clear out the state of the "UART" that receives from the tag.
125 static void DemodReset() {
126 Demod.state = DEMOD_UNSYNCD;
127 Demod.bitCount = 0;
128 Demod.posCount = 0;
129 Demod.thisBit = 0;
130 Demod.shiftReg = 0;
131 Demod.len = 0;
132 Demod.sumI = 0;
133 Demod.sumQ = 0;
134 Demod.startTime = 0;
135 Demod.endTime = 0;
136 }
137
138 static void DemodInit(uint8_t *data) {
139 Demod.output = data;
140 DemodReset();
141 // memset(Demod.output, 0x00, MAX_FRAME_SIZE);
142 }
143
144
145 /*
146 * 9.4395 us = 1 ETU and clock is about 1.5 us
147 * 13560000Hz
148 * 1000ms/s
149 * timeout in ETUs (time to transfer 1 bit, 9.4395 us)
150 *
151 * Formula to calculate FWT (in ETUs) by timeout (in ms):
152 * fwt = 13560000 * 1000 / (8*16) * timeout;
153 * Sample: 3sec == 3000ms
154 * 13560000 * 1000 / (8*16) * 3000 ==
155 * 13560000000 / 384000 = 35312 FWT
156 * @param timeout is in frame wait time, fwt, measured in ETUs
157 */
158 static void iso14b_set_timeout(uint32_t timeout) {
159 #define MAX_TIMEOUT 40542464 // 13560000Hz * 1000ms / (2^32-1) * (8*16)
160 if(timeout > MAX_TIMEOUT)
161 timeout = MAX_TIMEOUT;
162
163 iso14b_timeout = timeout;
164 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443B Timeout set to %ld fwt", iso14b_timeout);
165 }
166 static void iso14b_set_maxframesize(uint16_t size) {
167 if (size > 256)
168 size = MAX_FRAME_SIZE;
169
170 Uart.byteCntMax = size;
171 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443B Max frame size set to %d bytes", Uart.byteCntMax);
172 }
173 static void switch_off(void){
174 if (MF_DBGLEVEL > 3) Dbprintf("switch_off");
175 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
176 SpinDelay(100);
177 FpgaDisableSscDma();
178 set_tracing(FALSE);
179 LEDsoff();
180 }
181
182 void AppendCrc14443b(uint8_t* data, int len) {
183 ComputeCrc14443(CRC_14443_B, data, len, data+len, data+len+1);
184 }
185
186 //-----------------------------------------------------------------------------
187 // Code up a string of octets at layer 2 (including CRC, we don't generate
188 // that here) so that they can be transmitted to the reader. Doesn't transmit
189 // them yet, just leaves them ready to send in ToSend[].
190 //-----------------------------------------------------------------------------
191 static void CodeIso14443bAsTag(const uint8_t *cmd, int len) {
192 /* ISO 14443 B
193 *
194 * Reader to card | ASK - Amplitude Shift Keying Modulation (PCD to PICC for Type B) (NRZ-L encodig)
195 * Card to reader | BPSK - Binary Phase Shift Keying Modulation, (PICC to PCD for Type B)
196 *
197 * fc - carrier frequency 13.56mHz
198 * TR0 - Guard Time per 14443-2
199 * TR1 - Synchronization Time per 14443-2
200 * TR2 - PICC to PCD Frame Delay Time (per 14443-3 Amendment 1)
201 *
202 * Elementary Time Unit (ETU) is
203 * - 128 Carrier Cycles (9.4395 µS) = 8 Subcarrier Units
204 * - 1 ETU = 1 bit
205 * - 10 ETU = 1 startbit, 8 databits, 1 stopbit (10bits length)
206 * - startbit is a 0
207 * - stopbit is a 1
208 *
209 * Start of frame (SOF) is
210 * - [10-11] ETU of ZEROS, unmodulated time
211 * - [2-3] ETU of ONES,
212 *
213 * End of frame (EOF) is
214 * - [10-11] ETU of ZEROS, unmodulated time
215 *
216 * -TO VERIFY THIS BELOW-
217 * The mode FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK which we use to simulate tag
218 * works like this:
219 * - A 1-bit input to the FPGA becomes 8 pulses at 847.5kHz (9.44µS)
220 * - A 0-bit input to the FPGA becomes an unmodulated time of 9.44µS
221 *
222 *
223 *
224 * Card sends data ub 847.e kHz subcarrier
225 * 848k = 9.44µS = 128 fc
226 * 424k = 18.88µS = 256 fc
227 * 212k = 37.76µS = 512 fc
228 * 106k = 75.52µS = 1024 fc
229 *
230 * Reader data transmission:
231 * - no modulation ONES
232 * - SOF
233 * - Command, data and CRC_B
234 * - EOF
235 * - no modulation ONES
236 *
237 * Card data transmission
238 * - TR1
239 * - SOF
240 * - data (each bytes is: 1startbit,8bits, 1stopbit)
241 * - CRC_B
242 * - EOF
243 *
244 * FPGA implementation :
245 * At this point only Type A is implemented. This means that we are using a
246 * bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
247 * things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
248 *
249 */
250
251 int i,j;
252 uint8_t b;
253
254 ToSendReset();
255
256 // Transmit a burst of ones, as the initial thing that lets the
257 // reader get phase sync.
258 // This loop is TR1, per specification
259 // TR1 minimum must be > 80/fs
260 // TR1 maximum 200/fs
261 // 80/fs < TR1 < 200/fs
262 // 10 ETU < TR1 < 24 ETU
263
264 // Send SOF.
265 // 10-11 ETU * 4times samples ZEROS
266 for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
267 //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
268
269 // 2-3 ETU * 4times samples ONES
270 for(i = 0; i < 3; i++) { SEND4STUFFBIT(1); }
271 //for(i = 0; i < 3; i++) { ToSendStuffBit(1); }
272
273 // data
274 for(i = 0; i < len; ++i) {
275
276 // Start bit
277 SEND4STUFFBIT(0);
278 //ToSendStuffBit(0);
279
280 // Data bits
281 b = cmd[i];
282 for(j = 0; j < 8; ++j) {
283 if(b & 1) {
284 SEND4STUFFBIT(1);
285 //ToSendStuffBit(1);
286 } else {
287 SEND4STUFFBIT(0);
288 //ToSendStuffBit(0);
289 }
290 b >>= 1;
291 }
292
293 // Stop bit
294 SEND4STUFFBIT(1);
295 //ToSendStuffBit(1);
296
297 // Extra Guard bit
298 // For PICC it ranges 0-18us (1etu = 9us)
299 SEND4STUFFBIT(1);
300 //ToSendStuffBit(1);
301 }
302
303 // Send EOF.
304 // 10-11 ETU * 4 sample rate = ZEROS
305 for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
306 //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
307
308 // why this?
309 for(i = 0; i < 40; i++) { SEND4STUFFBIT(1); }
310 //for(i = 0; i < 40; i++) { ToSendStuffBit(1); }
311
312 // Convert from last byte pos to length
313 ++ToSendMax;
314 }
315
316
317 /* Receive & handle a bit coming from the reader.
318 *
319 * This function is called 4 times per bit (every 2 subcarrier cycles).
320 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
321 *
322 * LED handling:
323 * LED A -> ON once we have received the SOF and are expecting the rest.
324 * LED A -> OFF once we have received EOF or are in error state or unsynced
325 *
326 * Returns: true if we received a EOF
327 * false if we are still waiting for some more
328 */
329 static RAMFUNC int Handle14443bReaderUartBit(uint8_t bit) {
330 switch (Uart.state) {
331 case STATE_UNSYNCD:
332 if (!bit) {
333 // we went low, so this could be the beginning of an SOF
334 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
335 Uart.posCnt = 0;
336 Uart.bitCnt = 0;
337 }
338 break;
339
340 case STATE_GOT_FALLING_EDGE_OF_SOF:
341 Uart.posCnt++;
342 if (Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
343 if (bit) {
344 if (Uart.bitCnt > 9) {
345 // we've seen enough consecutive
346 // zeros that it's a valid SOF
347 Uart.posCnt = 0;
348 Uart.byteCnt = 0;
349 Uart.state = STATE_AWAITING_START_BIT;
350 LED_A_ON(); // Indicate we got a valid SOF
351 } else {
352 // didn't stay down long enough before going high, error
353 Uart.state = STATE_UNSYNCD;
354 }
355 } else {
356 // do nothing, keep waiting
357 }
358 Uart.bitCnt++;
359 }
360 if (Uart.posCnt >= 4) Uart.posCnt = 0;
361 if (Uart.bitCnt > 12) {
362 // Give up if we see too many zeros without a one, too.
363 LED_A_OFF();
364 Uart.state = STATE_UNSYNCD;
365 }
366 break;
367
368 case STATE_AWAITING_START_BIT:
369 Uart.posCnt++;
370 if (bit) {
371 if (Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
372 // stayed high for too long between characters, error
373 Uart.state = STATE_UNSYNCD;
374 }
375 } else {
376 // falling edge, this starts the data byte
377 Uart.posCnt = 0;
378 Uart.bitCnt = 0;
379 Uart.shiftReg = 0;
380 Uart.state = STATE_RECEIVING_DATA;
381 }
382 break;
383
384 case STATE_RECEIVING_DATA:
385 Uart.posCnt++;
386 if (Uart.posCnt == 2) {
387 // time to sample a bit
388 Uart.shiftReg >>= 1;
389 if (bit) {
390 Uart.shiftReg |= 0x200;
391 }
392 Uart.bitCnt++;
393 }
394 if (Uart.posCnt >= 4) {
395 Uart.posCnt = 0;
396 }
397 if (Uart.bitCnt == 10) {
398 if ((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
399 {
400 // this is a data byte, with correct
401 // start and stop bits
402 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
403 Uart.byteCnt++;
404
405 if (Uart.byteCnt >= Uart.byteCntMax) {
406 // Buffer overflowed, give up
407 LED_A_OFF();
408 Uart.state = STATE_UNSYNCD;
409 } else {
410 // so get the next byte now
411 Uart.posCnt = 0;
412 Uart.state = STATE_AWAITING_START_BIT;
413 }
414 } else if (Uart.shiftReg == 0x000) {
415 // this is an EOF byte
416 LED_A_OFF(); // Finished receiving
417 Uart.state = STATE_UNSYNCD;
418 if (Uart.byteCnt != 0)
419 return TRUE;
420
421 } else {
422 // this is an error
423 LED_A_OFF();
424 Uart.state = STATE_UNSYNCD;
425 }
426 }
427 break;
428
429 default:
430 LED_A_OFF();
431 Uart.state = STATE_UNSYNCD;
432 break;
433 }
434 return FALSE;
435 }
436
437 //-----------------------------------------------------------------------------
438 // Receive a command (from the reader to us, where we are the simulated tag),
439 // and store it in the given buffer, up to the given maximum length. Keeps
440 // spinning, waiting for a well-framed command, until either we get one
441 // (returns TRUE) or someone presses the pushbutton on the board (FALSE).
442 //
443 // Assume that we're called with the SSC (to the FPGA) and ADC path set
444 // correctly.
445 //-----------------------------------------------------------------------------
446 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len) {
447 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
448 // only, since we are receiving, not transmitting).
449 // Signal field is off with the appropriate LED
450 LED_D_OFF();
451 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
452
453 StartCountSspClk();
454
455 volatile uint8_t b;
456
457 // clear receiving shift register and holding register
458 // What does this loop do? Is it TR1?
459 for(uint8_t c = 0; c < 10;) {
460 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
461 AT91C_BASE_SSC->SSC_THR = 0xFF;
462 ++c;
463 }
464 }
465
466 // Now run a `software UART' on the stream of incoming samples.
467 UartInit(received);
468
469 b = 0;
470 uint8_t mask;
471 while( !BUTTON_PRESS() ) {
472 WDT_HIT();
473
474 if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) {
475 b = (uint8_t) AT91C_BASE_SSC->SSC_RHR;
476 for ( mask = 0x80; mask != 0; mask >>= 1) {
477 if ( Handle14443bReaderUartBit(b & mask)) {
478 *len = Uart.byteCnt;
479 return TRUE;
480 }
481 }
482 }
483 }
484 return FALSE;
485 }
486
487 void ClearFpgaShiftingRegisters(void){
488
489 volatile uint8_t b;
490
491 // clear receiving shift register and holding register
492 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
493
494 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
495
496 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
497
498 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
499
500
501 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
502 for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
503 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
504 if (AT91C_BASE_SSC->SSC_RHR) break;
505 }
506
507 // Clear TXRDY:
508 //AT91C_BASE_SSC->SSC_THR = 0xFF;
509 }
510
511 void WaitForFpgaDelayQueueIsEmpty( uint16_t delay ){
512 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
513 uint8_t fpga_queued_bits = delay >> 3; // twich /8 ?? >>3,
514 for (uint8_t i = 0; i <= fpga_queued_bits/8 + 1; ) {
515 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
516 AT91C_BASE_SSC->SSC_THR = 0xFF;
517 i++;
518 }
519 }
520 }
521
522 static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
523
524 volatile uint32_t b;
525
526 // Signal field is off with the appropriate LED
527 LED_D_OFF();
528 //uint16_t fpgasendQueueDelay = 0;
529
530 // Modulate BPSK
531 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
532 SpinDelay(40);
533
534 ClearFpgaShiftingRegisters();
535
536 FpgaSetupSsc();
537
538 // Transmit the response.
539 for(uint16_t i = 0; i < len;) {
540 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
541 AT91C_BASE_SSC->SSC_THR = response[++i];
542 }
543 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
544 b = AT91C_BASE_SSC->SSC_RHR;
545 (void)b;
546 }
547 }
548
549 //WaitForFpgaDelayQueueIsEmpty(fpgasendQueueDelay);
550 AT91C_BASE_SSC->SSC_THR = 0xFF;
551 }
552 //-----------------------------------------------------------------------------
553 // Main loop of simulated tag: receive commands from reader, decide what
554 // response to send, and send it.
555 //-----------------------------------------------------------------------------
556 void SimulateIso14443bTag(uint32_t pupi) {
557
558 ///////////// setup device.
559 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
560
561 // allocate command receive buffer
562 BigBuf_free();
563 BigBuf_Clear_ext(false);
564 clear_trace(); //sim
565 set_tracing(TRUE);
566
567 // connect Demodulated Signal to ADC:
568 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
569
570 // Set up the synchronous serial port
571 FpgaSetupSsc();
572 /////////////
573
574 uint16_t len, cmdsReceived = 0;
575 int cardSTATE = SIM_NOFIELD;
576 int vHf = 0; // in mV
577 // uint32_t time_0 = 0;
578 // uint32_t t2r_time = 0;
579 // uint32_t r2t_time = 0;
580 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
581
582 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
583 // static const uint8_t cmdWUPB[] = { ISO14443B_REQB, 0x00, 0x08, 0x39, 0x73 }; // WUPB
584 // ... and REQB, AFI=0, Normal Request, N=1:
585 // static const uint8_t cmdREQB[] = { ISO14443B_REQB, 0x00, 0x00, 0x71, 0xFF }; // REQB
586 // ... and ATTRIB
587 // static const uint8_t cmdATTRIB[] = { ISO14443B_ATTRIB, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
588
589 // ... if not PUPI/UID is supplied we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
590 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
591 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
592 uint8_t respATQB[] = { 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19,
593 0x22, 0x00, 0x21, 0x85, 0x5e, 0xd7 };
594
595 // response to HLTB and ATTRIB
596 static const uint8_t respOK[] = {0x00, 0x78, 0xF0};
597
598 // ...PUPI/UID supplied from user. Adjust ATQB response accordingly
599 if ( pupi > 0 ) {
600 uint8_t len = sizeof(respATQB);
601 num_to_bytes(pupi, 4, respATQB+1);
602 ComputeCrc14443(CRC_14443_B, respATQB, 12, &respATQB[len-2], &respATQB[len-1]);
603 }
604
605 // prepare "ATQB" tag answer (encoded):
606 CodeIso14443bAsTag(respATQB, sizeof(respATQB));
607 uint8_t *encodedATQB = BigBuf_malloc(ToSendMax);
608 uint16_t encodedATQBLen = ToSendMax;
609 memcpy(encodedATQB, ToSend, ToSendMax);
610
611
612 // prepare "OK" tag answer (encoded):
613 CodeIso14443bAsTag(respOK, sizeof(respOK));
614 uint8_t *encodedOK = BigBuf_malloc(ToSendMax);
615 uint16_t encodedOKLen = ToSendMax;
616 memcpy(encodedOK, ToSend, ToSendMax);
617
618 // Simulation loop
619 while (!BUTTON_PRESS() && !usb_poll_validate_length()) {
620 WDT_HIT();
621
622 // find reader field
623 if (cardSTATE == SIM_NOFIELD) {
624 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
625 if ( vHf > MF_MINFIELDV ) {
626 cardSTATE = SIM_IDLE;
627 LED_A_ON();
628 }
629 }
630 if (cardSTATE == SIM_NOFIELD) continue;
631
632 // Get reader command
633 if (!GetIso14443bCommandFromReader(receivedCmd, &len)) {
634 Dbprintf("button pressed, received %d commands", cmdsReceived);
635 break;
636 }
637
638 // ISO14443-B protocol states:
639 // REQ or WUP request in ANY state
640 // WUP in HALTED state
641 if (len == 5 ) {
642 if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE == SIM_HALTED) ||
643 receivedCmd[0] == ISO14443B_REQB ){
644 LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
645 cardSTATE = SIM_SELECTING;
646 }
647 }
648
649 /*
650 * How should this flow go?
651 * REQB or WUPB
652 * send response ( waiting for Attrib)
653 * ATTRIB
654 * send response ( waiting for commands 7816)
655 * HALT
656 send halt response ( waiting for wupb )
657 */
658
659 switch (cardSTATE) {
660 case SIM_NOFIELD:
661 case SIM_HALTED:
662 case SIM_IDLE: {
663 LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
664 break;
665 }
666 case SIM_SELECTING: {
667 TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
668 LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
669 cardSTATE = SIM_WORK;
670 break;
671 }
672 case SIM_HALTING: {
673 TransmitFor14443b_AsTag( encodedOK, encodedOKLen );
674 LogTrace(respOK, sizeof(respOK), 0, 0, NULL, FALSE);
675 cardSTATE = SIM_HALTED;
676 break;
677 }
678 case SIM_ACKNOWLEDGE: {
679 TransmitFor14443b_AsTag( encodedOK, encodedOKLen );
680 LogTrace(respOK, sizeof(respOK), 0, 0, NULL, FALSE);
681 cardSTATE = SIM_IDLE;
682 break;
683 }
684 case SIM_WORK: {
685 if ( len == 7 && receivedCmd[0] == ISO14443B_HALT ) {
686 cardSTATE = SIM_HALTED;
687 } else if ( len == 11 && receivedCmd[0] == ISO14443B_ATTRIB ) {
688 cardSTATE = SIM_ACKNOWLEDGE;
689 } else {
690 // Todo:
691 // - SLOT MARKER
692 // - ISO7816
693 // - emulate with a memory dump
694 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsReceived);
695
696 // CRC Check
697 uint8_t b1, b2;
698 if (len >= 3){ // if crc exists
699 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
700 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1])
701 DbpString("+++CRC fail");
702 else
703 DbpString("CRC passes");
704 }
705 cardSTATE = SIM_IDLE;
706 }
707 break;
708 }
709 default: break;
710 }
711
712 ++cmdsReceived;
713 // iceman, could add a switch to turn this on/off (if off, no logging?)
714 if(cmdsReceived > 1000) {
715 DbpString("14B Simulate, 1000 commands later...");
716 break;
717 }
718 }
719 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
720 switch_off(); //simulate
721 }
722
723 //=============================================================================
724 // An ISO 14443 Type B reader. We take layer two commands, code them
725 // appropriately, and then send them to the tag. We then listen for the
726 // tag's response, which we leave in the buffer to be demodulated on the
727 // PC side.
728 //=============================================================================
729
730 /*
731 * Handles reception of a bit from the tag
732 *
733 * This function is called 2 times per bit (every 4 subcarrier cycles).
734 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
735 *
736 * LED handling:
737 * LED C -> ON once we have received the SOF and are expecting the rest.
738 * LED C -> OFF once we have received EOF or are unsynced
739 *
740 * Returns: true if we received a EOF
741 * false if we are still waiting for some more
742 *
743 */
744 static RAMFUNC int Handle14443bTagSamplesDemod(int ci, int cq) {
745 int v = 0, myI = ABS(ci), myQ = ABS(cq);
746
747 // The soft decision on the bit uses an estimate of just the
748 // quadrant of the reference angle, not the exact angle.
749 #define MAKE_SOFT_DECISION() { \
750 if(Demod.sumI > 0) { \
751 v = ci; \
752 } else { \
753 v = -ci; \
754 } \
755 if(Demod.sumQ > 0) { \
756 v += cq; \
757 } else { \
758 v -= cq; \
759 } \
760 }
761
762 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
763 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
764 #define CHECK_FOR_SUBCARRIER_old() { \
765 if(ci < 0) { \
766 if(cq < 0) { /* ci < 0, cq < 0 */ \
767 if (cq < ci) { \
768 v = -cq - (ci >> 1); \
769 } else { \
770 v = -ci - (cq >> 1); \
771 } \
772 } else { /* ci < 0, cq >= 0 */ \
773 if (cq < -ci) { \
774 v = -ci + (cq >> 1); \
775 } else { \
776 v = cq - (ci >> 1); \
777 } \
778 } \
779 } else { \
780 if(cq < 0) { /* ci >= 0, cq < 0 */ \
781 if (-cq < ci) { \
782 v = ci - (cq >> 1); \
783 } else { \
784 v = -cq + (ci >> 1); \
785 } \
786 } else { /* ci >= 0, cq >= 0 */ \
787 if (cq < ci) { \
788 v = ci + (cq >> 1); \
789 } else { \
790 v = cq + (ci >> 1); \
791 } \
792 } \
793 } \
794 }
795
796 //note: couldn't we just use MAX(ABS(ci),ABS(cq)) + (MIN(ABS(ci),ABS(cq))/2) from common.h - marshmellow
797 #define CHECK_FOR_SUBCARRIER() { \
798 v = MAX(myI, myQ) + (MIN(myI, myQ) >> 1); \
799 }
800
801 switch(Demod.state) {
802 case DEMOD_UNSYNCD:
803
804 CHECK_FOR_SUBCARRIER();
805 if (MF_DBGLEVEL >= 3) { Dbprintf("Demod.state = %d", v); }
806
807 // subcarrier detected
808 if(v > SUBCARRIER_DETECT_THRESHOLD) {
809 Demod.state = DEMOD_PHASE_REF_TRAINING;
810 Demod.sumI = ci;
811 Demod.sumQ = cq;
812 Demod.posCount = 1;
813 }
814 break;
815
816 case DEMOD_PHASE_REF_TRAINING:
817 if(Demod.posCount < 8) {
818
819 CHECK_FOR_SUBCARRIER();
820
821 if (v > SUBCARRIER_DETECT_THRESHOLD) {
822 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
823 // note: synchronization time > 80 1/fs
824 Demod.sumI += ci;
825 Demod.sumQ += cq;
826 ++Demod.posCount;
827 } else {
828 // subcarrier lost
829 Demod.state = DEMOD_UNSYNCD;
830 }
831 } else {
832 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
833 }
834 break;
835
836 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
837
838 MAKE_SOFT_DECISION();
839
840 if(v < 0) { // logic '0' detected
841 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
842 Demod.posCount = 0; // start of SOF sequence
843 } else {
844 // maximum length of TR1 = 200 1/fs
845 if(Demod.posCount > 26*2) Demod.state = DEMOD_UNSYNCD;
846 }
847 ++Demod.posCount;
848 break;
849
850 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
851 ++Demod.posCount;
852
853 MAKE_SOFT_DECISION();
854
855 if(v > 0) {
856 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
857 if(Demod.posCount < 8*2) {
858 Demod.state = DEMOD_UNSYNCD;
859 } else {
860 LED_C_ON(); // Got SOF
861 Demod.startTime = GetCountSspClk();
862 Demod.state = DEMOD_AWAITING_START_BIT;
863 Demod.posCount = 0;
864 Demod.len = 0;
865 }
866 } else {
867 // low phase of SOF too long (> 12 etu)
868 if (Demod.posCount > 14*2) {
869 Demod.state = DEMOD_UNSYNCD;
870 LED_C_OFF();
871 }
872 }
873 break;
874
875 case DEMOD_AWAITING_START_BIT:
876 ++Demod.posCount;
877
878 MAKE_SOFT_DECISION();
879
880 if (v > 0) {
881 if(Demod.posCount > 2*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
882 Demod.state = DEMOD_UNSYNCD;
883 LED_C_OFF();
884 }
885 } else { // start bit detected
886 Demod.bitCount = 0;
887 Demod.posCount = 1; // this was the first half
888 Demod.thisBit = v;
889 Demod.shiftReg = 0;
890 Demod.state = DEMOD_RECEIVING_DATA;
891 }
892 break;
893
894 case DEMOD_RECEIVING_DATA:
895
896 MAKE_SOFT_DECISION();
897
898 if (Demod.posCount == 0) {
899 // first half of bit
900 Demod.thisBit = v;
901 Demod.posCount = 1;
902 } else {
903 // second half of bit
904 Demod.thisBit += v;
905 Demod.shiftReg >>= 1;
906
907 // logic '1'
908 if (Demod.thisBit > 0) Demod.shiftReg |= 0x200;
909
910 ++Demod.bitCount;
911
912 // 1 start 8 data 1 stop = 10
913 if (Demod.bitCount == 10) {
914
915 uint16_t s = Demod.shiftReg;
916
917 // stop bit == '1', start bit == '0'
918 if ((s & 0x200) && (s & 0x001) == 0 ) {
919 // left shift to drop the startbit
920 Demod.output[Demod.len] = (s >> 1) & 0xFF;
921 ++Demod.len;
922 Demod.state = DEMOD_AWAITING_START_BIT;
923 } else {
924 // this one is a bit hard, either its a correc byte or its unsynced.
925 Demod.state = DEMOD_UNSYNCD;
926 Demod.endTime = GetCountSspClk();
927 LED_C_OFF();
928
929 // This is EOF (start, stop and all data bits == '0'
930 if (s == 0) return TRUE;
931 }
932 }
933 Demod.posCount = 0;
934 }
935 break;
936
937 default:
938 Demod.state = DEMOD_UNSYNCD;
939 LED_C_OFF();
940 break;
941 }
942 return FALSE;
943 }
944
945
946 /*
947 * Demodulate the samples we received from the tag, also log to tracebuffer
948 * quiet: set to 'TRUE' to disable debug output
949 */
950 static void GetTagSamplesFor14443bDemod() {
951 bool gotFrame = FALSE, finished = FALSE;
952 int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
953 int ci = 0, cq = 0;
954 uint32_t time_0 = 0, time_stop = 0;
955
956 BigBuf_free();
957
958 // Set up the demodulator for tag -> reader responses.
959 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
960
961 // The DMA buffer, used to stream samples from the FPGA
962 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
963 int8_t *upTo = dmaBuf;
964
965 // Setup and start DMA.
966 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE) ){
967 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
968 return;
969 }
970
971 // And put the FPGA in the appropriate mode
972 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
973
974 // get current clock
975 time_0 = GetCountSspClk();
976
977 // rx counter - dma counter? (how much?) & (mod) mask > 2. (since 2bytes at the time is read)
978 while ( !finished ) {
979
980 LED_A_INV();
981 WDT_HIT();
982
983 // LSB is a fpga signal bit.
984 ci = upTo[0] >> 1;
985 cq = upTo[1] >> 1;
986 upTo += 2;
987 lastRxCounter -= 2;
988
989 // restart DMA buffer to receive again.
990 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
991 upTo = dmaBuf;
992 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
993 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
994 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
995 }
996
997 // https://github.com/Proxmark/proxmark3/issues/103
998 gotFrame = Handle14443bTagSamplesDemod(ci, cq);
999 time_stop = GetCountSspClk() - time_0;
1000
1001 finished = (time_stop > iso14b_timeout || gotFrame);
1002 }
1003
1004 FpgaDisableSscDma();
1005
1006 if ( upTo ) upTo = NULL;
1007
1008 if (MF_DBGLEVEL >= 3) {
1009 Dbprintf("Demod.state = %d, Demod.len = %u, PDC_RCR = %u",
1010 Demod.state,
1011 Demod.len,
1012 AT91C_BASE_PDC_SSC->PDC_RCR
1013 );
1014 }
1015
1016 // print the last batch of IQ values from FPGA
1017 if (MF_DBGLEVEL == 4)
1018 Dbhexdump(ISO14443B_DMA_BUFFER_SIZE, (uint8_t *)dmaBuf, FALSE);
1019
1020 if ( Demod.len > 0 )
1021 LogTrace(Demod.output, Demod.len, Demod.startTime, Demod.endTime, NULL, FALSE);
1022 }
1023
1024
1025 //-----------------------------------------------------------------------------
1026 // Transmit the command (to the tag) that was placed in ToSend[].
1027 //-----------------------------------------------------------------------------
1028 static void TransmitFor14443b_AsReader(void) {
1029
1030 // we could been in following mode:
1031 // FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ
1032 // if its second call or more
1033
1034 // while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1035 // AT91C_BASE_SSC->SSC_THR = 0XFF;
1036 // }
1037
1038 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1039 SpinDelay(40);
1040
1041 int c;
1042 volatile uint32_t b;
1043
1044 // What does this loop do? Is it TR1?
1045 // 0xFF = 8 bits of 1. 1 bit == 1Etu,..
1046 // loop 10 * 8 = 80 ETU of delay, with a non modulated signal. why?
1047 // 80*9 = 720us.
1048 for(c = 0; c < 50;) {
1049 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1050 AT91C_BASE_SSC->SSC_THR = 0xFF;
1051 ++c;
1052 }
1053 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1054 b = AT91C_BASE_SSC->SSC_RHR;
1055 (void)b;
1056 }
1057 }
1058
1059 // Send frame loop
1060 for(c = 0; c < ToSendMax;) {
1061 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1062 AT91C_BASE_SSC->SSC_THR = ToSend[c++];
1063 }
1064 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1065 b = AT91C_BASE_SSC->SSC_RHR;
1066 (void)b;
1067 }
1068 }
1069 //WaitForFpgaDelayQueueIsEmpty(delay);
1070 // We should wait here for the FPGA to send all bits.
1071 WDT_HIT();
1072 }
1073
1074 //-----------------------------------------------------------------------------
1075 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1076 // so that it is ready to transmit to the tag using TransmitFor14443b().
1077 //-----------------------------------------------------------------------------
1078 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
1079 {
1080 /*
1081 * Reader data transmission:
1082 * - no modulation ONES
1083 * - SOF
1084 * - Command, data and CRC_B
1085 * - EOF
1086 * - no modulation ONES
1087 *
1088 * 1 ETU == 1 BIT!
1089 * TR0 - 8 ETUS minimum.
1090 *
1091 * QUESTION: how long is a 1 or 0 in pulses in the xcorr_848 mode?
1092 * 1 "stuffbit" = 1ETU (9us)
1093 */
1094 int i;
1095 uint8_t b;
1096
1097 ToSendReset();
1098
1099 // Send SOF
1100 // 10-11 ETUs of ZERO
1101 for(i = 0; i < 10; ++i) ToSendStuffBit(0);
1102
1103 // 2-3 ETUs of ONE
1104 ToSendStuffBit(1);
1105 ToSendStuffBit(1);
1106 ToSendStuffBit(1);
1107
1108 // Sending cmd, LSB
1109 // from here we add BITS
1110 for(i = 0; i < len; ++i) {
1111 // Start bit
1112 ToSendStuffBit(0);
1113 // Data bits
1114 b = cmd[i];
1115 if ( b & 1 ) ToSendStuffBit(1); else ToSendStuffBit(0);
1116 if ( (b>>1) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1117 if ( (b>>2) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1118 if ( (b>>3) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1119 if ( (b>>4) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1120 if ( (b>>5) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1121 if ( (b>>6) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1122 if ( (b>>7) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1123 // Stop bit
1124 ToSendStuffBit(1);
1125 // EGT extra guard time
1126 // For PCD it ranges 0-57us (1etu = 9us)
1127 ToSendStuffBit(1);
1128 ToSendStuffBit(1);
1129 ToSendStuffBit(1);
1130 }
1131
1132 // Send EOF
1133 // 10-11 ETUs of ZERO
1134 for(i = 0; i < 10; ++i) ToSendStuffBit(0);
1135
1136 // Transition time. TR0 - guard time
1137 // 8ETUS minum?
1138 // Per specification, Subcarrier must be stopped no later than 2 ETUs after EOF.
1139 // I'm guessing this is for the FPGA to be able to send all bits before we switch to listening mode
1140 for(i = 0; i < 32 ; ++i) ToSendStuffBit(1);
1141
1142 // TR1 - Synchronization time
1143 // Convert from last character reference to length
1144 ++ToSendMax;
1145 }
1146
1147
1148 /**
1149 Convenience function to encode, transmit and trace iso 14443b comms
1150 **/
1151 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len) {
1152
1153 CodeIso14443bAsReader(cmd, len);
1154
1155 uint32_t time_start = GetCountSspClk();
1156
1157 TransmitFor14443b_AsReader();
1158
1159 if(trigger) LED_A_ON();
1160
1161 LogTrace(cmd, len, time_start, GetCountSspClk()-time_start, NULL, TRUE);
1162 }
1163
1164 /* Sends an APDU to the tag
1165 * TODO: check CRC and preamble
1166 */
1167 uint8_t iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
1168 {
1169 uint8_t crc[2] = {0x00, 0x00};
1170 uint8_t message_frame[message_length + 4];
1171 // PCB
1172 message_frame[0] = 0x0A | pcb_blocknum;
1173 pcb_blocknum ^= 1;
1174 // CID
1175 message_frame[1] = 0;
1176 // INF
1177 memcpy(message_frame + 2, message, message_length);
1178 // EDC (CRC)
1179 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
1180 // send
1181 CodeAndTransmit14443bAsReader(message_frame, message_length + 4); //no
1182 // get response
1183 GetTagSamplesFor14443bDemod(); //no
1184 if(Demod.len < 3)
1185 return 0;
1186
1187 // VALIDATE CRC
1188 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1189 if ( crc[0] != Demod.output[Demod.len-2] || crc[1] != Demod.output[Demod.len-1] )
1190 return 0;
1191
1192 // copy response contents
1193 if(response != NULL)
1194 memcpy(response, Demod.output, Demod.len);
1195
1196 return Demod.len;
1197 }
1198
1199 /**
1200 * SRx Initialise.
1201 */
1202 uint8_t iso14443b_select_srx_card(iso14b_card_select_t *card )
1203 {
1204 // INITIATE command: wake up the tag using the INITIATE
1205 static const uint8_t init_srx[] = { ISO14443B_INITIATE, 0x00, 0x97, 0x5b };
1206 // SELECT command (with space for CRC)
1207 uint8_t select_srx[] = { ISO14443B_SELECT, 0x00, 0x00, 0x00};
1208 // temp to calc crc.
1209 uint8_t crc[2] = {0x00, 0x00};
1210
1211 CodeAndTransmit14443bAsReader(init_srx, sizeof(init_srx));
1212 GetTagSamplesFor14443bDemod(); //no
1213
1214 if (Demod.len == 0) return 2;
1215
1216 // Randomly generated Chip ID
1217 if (card) card->chipid = Demod.output[0];
1218
1219 select_srx[1] = Demod.output[0];
1220
1221 ComputeCrc14443(CRC_14443_B, select_srx, 2, &select_srx[2], &select_srx[3]);
1222 CodeAndTransmit14443bAsReader(select_srx, sizeof(select_srx));
1223 GetTagSamplesFor14443bDemod(); //no
1224
1225 if (Demod.len != 3) return 2;
1226
1227 // Check the CRC of the answer:
1228 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2 , &crc[0], &crc[1]);
1229 if(crc[0] != Demod.output[1] || crc[1] != Demod.output[2]) return 3;
1230
1231 // Check response from the tag: should be the same UID as the command we just sent:
1232 if (select_srx[1] != Demod.output[0]) return 1;
1233
1234 // First get the tag's UID:
1235 select_srx[0] = ISO14443B_GET_UID;
1236
1237 ComputeCrc14443(CRC_14443_B, select_srx, 1 , &select_srx[1], &select_srx[2]);
1238 CodeAndTransmit14443bAsReader(select_srx, 3); // Only first three bytes for this one
1239 GetTagSamplesFor14443bDemod(); //no
1240
1241 if (Demod.len != 10) return 2;
1242
1243 // The check the CRC of the answer
1244 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1245 if(crc[0] != Demod.output[8] || crc[1] != Demod.output[9]) return 3;
1246
1247 if (card) {
1248 card->uidlen = 8;
1249 memcpy(card->uid, Demod.output, 8);
1250 }
1251
1252 return 0;
1253 }
1254 /* Perform the ISO 14443 B Card Selection procedure
1255 * Currently does NOT do any collision handling.
1256 * It expects 0-1 cards in the device's range.
1257 * TODO: Support multiple cards (perform anticollision)
1258 * TODO: Verify CRC checksums
1259 */
1260 uint8_t iso14443b_select_card(iso14b_card_select_t *card )
1261 {
1262 // WUPB command (including CRC)
1263 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
1264 static const uint8_t wupb[] = { ISO14443B_REQB, 0x00, 0x08, 0x39, 0x73 };
1265 // ATTRIB command (with space for CRC)
1266 uint8_t attrib[] = { ISO14443B_ATTRIB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
1267
1268 // temp to calc crc.
1269 uint8_t crc[2] = {0x00, 0x00};
1270
1271 // first, wake up the tag
1272 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
1273 GetTagSamplesFor14443bDemod(); //select_card
1274
1275 // ATQB too short?
1276 if (Demod.len < 14) return 2;
1277
1278 // VALIDATE CRC
1279 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1280 if ( crc[0] != Demod.output[12] || crc[1] != Demod.output[13] )
1281 return 3;
1282
1283 if (card) {
1284 card->uidlen = 4;
1285 memcpy(card->uid, Demod.output+1, 4);
1286 memcpy(card->atqb, Demod.output+5, 7);
1287 }
1288
1289 // copy the PUPI to ATTRIB ( PUPI == UID )
1290 memcpy(attrib + 1, Demod.output + 1, 4);
1291
1292 // copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into ATTRIB (Param 3)
1293 attrib[7] = Demod.output[10] & 0x0F;
1294 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
1295
1296 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
1297 GetTagSamplesFor14443bDemod();//select_card
1298
1299 // Answer to ATTRIB too short?
1300 if(Demod.len < 3) return 2;
1301
1302 // VALIDATE CRC
1303 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1304 if ( crc[0] != Demod.output[1] || crc[1] != Demod.output[2] )
1305 return 3;
1306
1307 if (card) {
1308
1309 // CID
1310 card->cid = Demod.output[0];
1311
1312 // MAX FRAME
1313 uint16_t maxFrame = card->atqb[5] >> 4;
1314 if (maxFrame < 5) maxFrame = 8 * maxFrame + 16;
1315 else if (maxFrame == 5) maxFrame = 64;
1316 else if (maxFrame == 6) maxFrame = 96;
1317 else if (maxFrame == 7) maxFrame = 128;
1318 else if (maxFrame == 8) maxFrame = 256;
1319 else maxFrame = 257;
1320 iso14b_set_maxframesize(maxFrame);
1321
1322 // FWT
1323 uint8_t fwt = card->atqb[6] >> 4;
1324 if ( fwt < 16 ){
1325 uint32_t fwt_time = (302 << fwt);
1326 iso14b_set_timeout( fwt_time);
1327 }
1328 }
1329 // reset PCB block number
1330 pcb_blocknum = 0;
1331 return 0;
1332 }
1333
1334 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
1335 // field is setup for "Sending as Reader"
1336 void iso14443b_setup() {
1337 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup Enter");
1338 LEDsoff();
1339 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1340 //BigBuf_free();
1341 //BigBuf_Clear_ext(false);
1342
1343 // Initialize Demod and Uart structs
1344 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1345 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1346
1347 // connect Demodulated Signal to ADC:
1348 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1349
1350 // Set up the synchronous serial port
1351 FpgaSetupSsc();
1352
1353 // Signal field is on with the appropriate LED
1354 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1355 SpinDelay(100);
1356
1357 // Start the timer
1358 StartCountSspClk();
1359
1360 LED_D_ON();
1361 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup Exit");
1362 }
1363
1364 //-----------------------------------------------------------------------------
1365 // Read a SRI512 ISO 14443B tag.
1366 //
1367 // SRI512 tags are just simple memory tags, here we're looking at making a dump
1368 // of the contents of the memory. No anticollision algorithm is done, we assume
1369 // we have a single tag in the field.
1370 //
1371 // I tried to be systematic and check every answer of the tag, every CRC, etc...
1372 //-----------------------------------------------------------------------------
1373 void ReadSTMemoryIso14443b(uint8_t numofblocks)
1374 {
1375 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1376
1377 // Make sure that we start from off, since the tags are stateful;
1378 // confusing things will happen if we don't reset them between reads.
1379 switch_off(); // before ReadStMemory
1380
1381 set_tracing(TRUE);
1382
1383 uint8_t i = 0x00;
1384
1385 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1386 FpgaSetupSsc();
1387
1388 // Now give it time to spin up.
1389 // Signal field is on with the appropriate LED
1390 LED_D_ON();
1391 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
1392 SpinDelay(20);
1393
1394 // First command: wake up the tag using the INITIATE command
1395 uint8_t cmd1[] = {ISO14443B_INITIATE, 0x00, 0x97, 0x5b};
1396 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1)); //no
1397 GetTagSamplesFor14443bDemod(); // no
1398
1399 if (Demod.len == 0) {
1400 DbpString("No response from tag");
1401 set_tracing(FALSE);
1402 return;
1403 } else {
1404 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1405 Demod.output[0], Demod.output[1], Demod.output[2]);
1406 }
1407
1408 // There is a response, SELECT the uid
1409 DbpString("Now SELECT tag:");
1410 cmd1[0] = ISO14443B_SELECT; // 0x0E is SELECT
1411 cmd1[1] = Demod.output[0];
1412 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1413 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1)); //no
1414 GetTagSamplesFor14443bDemod(); //no
1415 if (Demod.len != 3) {
1416 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1417 set_tracing(FALSE);
1418 return;
1419 }
1420 // Check the CRC of the answer:
1421 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1422 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1423 DbpString("CRC Error reading select response.");
1424 set_tracing(FALSE);
1425 return;
1426 }
1427 // Check response from the tag: should be the same UID as the command we just sent:
1428 if (cmd1[1] != Demod.output[0]) {
1429 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1430 set_tracing(FALSE);
1431 return;
1432 }
1433
1434 // Tag is now selected,
1435 // First get the tag's UID:
1436 cmd1[0] = ISO14443B_GET_UID;
1437 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1438 CodeAndTransmit14443bAsReader(cmd1, 3); // no -- Only first three bytes for this one
1439 GetTagSamplesFor14443bDemod(); //no
1440 if (Demod.len != 10) {
1441 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1442 set_tracing(FALSE);
1443 return;
1444 }
1445 // The check the CRC of the answer (use cmd1 as temporary variable):
1446 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1447 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1448 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1449 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1450 // Do not return;, let's go on... (we should retry, maybe ?)
1451 }
1452 Dbprintf("Tag UID (64 bits): %08x %08x",
1453 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1454 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1455
1456 // Now loop to read all 16 blocks, address from 0 to last block
1457 Dbprintf("Tag memory dump, block 0 to %d", numofblocks);
1458 cmd1[0] = 0x08;
1459 i = 0x00;
1460 ++numofblocks;
1461
1462 for (;;) {
1463 if (i == numofblocks) {
1464 DbpString("System area block (0xff):");
1465 i = 0xff;
1466 }
1467 cmd1[1] = i;
1468 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1469 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1)); //no
1470 GetTagSamplesFor14443bDemod(); //no
1471
1472 if (Demod.len != 6) { // Check if we got an answer from the tag
1473 DbpString("Expected 6 bytes from tag, got less...");
1474 return;
1475 }
1476 // The check the CRC of the answer (use cmd1 as temporary variable):
1477 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1478 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1479 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1480 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1481 // Do not return;, let's go on... (we should retry, maybe ?)
1482 }
1483 // Now print out the memory location:
1484 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1485 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1486 (Demod.output[4]<<8)+Demod.output[5]);
1487
1488 if (i == 0xff) break;
1489 ++i;
1490 }
1491
1492 set_tracing(FALSE);
1493 }
1494
1495
1496 static void iso1444b_setup_snoop(void){
1497 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup_snoop Enter");
1498 LEDsoff();
1499 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1500 BigBuf_free();
1501 BigBuf_Clear_ext(false);
1502 clear_trace();//setup snoop
1503 set_tracing(TRUE);
1504
1505 // Initialize Demod and Uart structs
1506 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1507 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1508
1509 if (MF_DBGLEVEL > 1) {
1510 // Print debug information about the buffer sizes
1511 Dbprintf("Snooping buffers initialized:");
1512 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1513 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1514 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1515 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1516 }
1517
1518 // connect Demodulated Signal to ADC:
1519 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1520
1521 // Setup for the DMA.
1522 FpgaSetupSsc();
1523
1524 // Set FPGA in the appropriate mode
1525 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1526 SpinDelay(20);
1527
1528 // Start the SSP timer
1529 StartCountSspClk();
1530 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup_snoop Exit");
1531 }
1532
1533 //=============================================================================
1534 // Finally, the `sniffer' combines elements from both the reader and
1535 // simulated tag, to show both sides of the conversation.
1536 //=============================================================================
1537
1538 //-----------------------------------------------------------------------------
1539 // Record the sequence of commands sent by the reader to the tag, with
1540 // triggering so that we start recording at the point that the tag is moved
1541 // near the reader.
1542 //-----------------------------------------------------------------------------
1543 /*
1544 * Memory usage for this function, (within BigBuf)
1545 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1546 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1547 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1548 * Demodulated samples received - all the rest
1549 */
1550 void RAMFUNC SnoopIso14443b(void) {
1551
1552 uint32_t time_0 = 0, time_start = 0, time_stop = 0;
1553 int ci = 0, cq = 0;
1554 int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1555
1556 // We won't start recording the frames that we acquire until we trigger;
1557 // a good trigger condition to get started is probably when we see a
1558 // response from the tag.
1559 bool triggered = TRUE; // TODO: set and evaluate trigger condition
1560 bool TagIsActive = FALSE;
1561 bool ReaderIsActive = FALSE;
1562
1563 iso1444b_setup_snoop();
1564
1565 // The DMA buffer, used to stream samples from the FPGA
1566 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
1567 int8_t *upTo = dmaBuf;
1568
1569 // Setup and start DMA.
1570 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE) ){
1571 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1572 BigBuf_free();
1573 return;
1574 }
1575
1576 time_0 = GetCountSspClk();
1577
1578 // And now we loop, receiving samples.
1579 for(;;) {
1580
1581 WDT_HIT();
1582
1583 ci = upTo[0];
1584 cq = upTo[1];
1585 upTo += 2;
1586 lastRxCounter -= 2;
1587
1588 if (upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
1589 upTo = dmaBuf;
1590 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1591 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
1592 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
1593
1594 if (!tracing) {
1595 if (MF_DBGLEVEL >= 2) DbpString("Trace full");
1596 break;
1597 }
1598
1599 if (BUTTON_PRESS()) {
1600 if (MF_DBGLEVEL >= 2) DbpString("cancelled");
1601 break;
1602 }
1603 }
1604
1605 if (!TagIsActive) {
1606
1607 LED_A_ON();
1608
1609 // no need to try decoding reader data if the tag is sending
1610 if (Handle14443bReaderUartBit(ci & 0x01)) {
1611
1612 time_stop = GetCountSspClk() - time_0;
1613
1614 if (triggered)
1615 LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
1616
1617 /* And ready to receive another command. */
1618 UartReset();
1619 /* And also reset the demod code, which might have been */
1620 /* false-triggered by the commands from the reader. */
1621 DemodReset();
1622 } else {
1623 time_start = GetCountSspClk() - time_0;
1624 }
1625
1626 if (Handle14443bReaderUartBit(cq & 0x01)) {
1627
1628 time_stop = GetCountSspClk() - time_0;
1629
1630 if (triggered)
1631 LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
1632
1633 /* And ready to receive another command. */
1634 UartReset();
1635 /* And also reset the demod code, which might have been */
1636 /* false-triggered by the commands from the reader. */
1637 DemodReset();
1638 } else {
1639 time_start = GetCountSspClk() - time_0;
1640 }
1641 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1642 LED_A_OFF();
1643 }
1644
1645 if (!ReaderIsActive) {
1646 // no need to try decoding tag data if the reader is sending - and we cannot afford the time
1647 // is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
1648 // LSB is a fpga signal bit.
1649 if (Handle14443bTagSamplesDemod(ci >> 1, cq >> 1)) {
1650
1651 time_stop = GetCountSspClk() - time_0;
1652
1653 LogTrace(Demod.output, Demod.len, time_start, time_stop, NULL, FALSE);
1654
1655 triggered = TRUE;
1656
1657 // And ready to receive another response.
1658 DemodReset();
1659 } else {
1660 time_start = GetCountSspClk() - time_0;
1661 }
1662 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1663 }
1664 }
1665
1666 switch_off(); // Snoop
1667
1668 DbpString("Snoop statistics:");
1669 Dbprintf(" Uart State: %x ByteCount: %i ByteCountMax: %i", Uart.state, Uart.byteCnt, Uart.byteCntMax);
1670 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1671
1672 // free mem refs.
1673 if ( upTo ) upTo = NULL;
1674
1675 // Uart.byteCntMax should be set with ATQB value..
1676 }
1677
1678 void iso14b_set_trigger(bool enable) {
1679 trigger = enable;
1680 }
1681
1682 /*
1683 * Send raw command to tag ISO14443B
1684 * @Input
1685 * param flags enum ISO14B_COMMAND. (mifare.h)
1686 * len len of buffer data
1687 * data buffer with bytes to send
1688 *
1689 * @Output
1690 * none
1691 *
1692 */
1693 void SendRawCommand14443B_Ex(UsbCommand *c)
1694 {
1695 iso14b_command_t param = c->arg[0];
1696 size_t len = c->arg[1] & 0xffff;
1697 uint8_t *cmd = c->d.asBytes;
1698 uint8_t status = 0;
1699 uint32_t sendlen = sizeof(iso14b_card_select_t);
1700 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
1701
1702 if (MF_DBGLEVEL > 3) Dbprintf("14b raw: param, %04x", param );
1703
1704 // turn on trigger (LED_A)
1705 if ((param & ISO14B_REQUEST_TRIGGER) == ISO14B_REQUEST_TRIGGER)
1706 iso14b_set_trigger(TRUE);
1707
1708 if ((param & ISO14B_CONNECT) == ISO14B_CONNECT) {
1709 // Make sure that we start from off, since the tags are stateful;
1710 // confusing things will happen if we don't reset them between reads.
1711 //switch_off(); // before connect in raw
1712 iso14443b_setup();
1713 }
1714
1715 set_tracing(TRUE);
1716
1717 if ((param & ISO14B_SELECT_STD) == ISO14B_SELECT_STD) {
1718 iso14b_card_select_t *card = (iso14b_card_select_t*)buf;
1719 status = iso14443b_select_card(card);
1720 cmd_send(CMD_ACK, status, sendlen, 0, buf, sendlen);
1721 // 0: OK 2: attrib fail, 3:crc fail,
1722 if ( status > 0 ) return;
1723 }
1724
1725 if ((param & ISO14B_SELECT_SR) == ISO14B_SELECT_SR) {
1726 iso14b_card_select_t *card = (iso14b_card_select_t*)buf;
1727 status = iso14443b_select_srx_card(card);
1728 cmd_send(CMD_ACK, status, sendlen, 0, buf, sendlen);
1729 // 0: OK 2: attrib fail, 3:crc fail,
1730 if ( status > 0 ) return;
1731 }
1732
1733 if ((param & ISO14B_APDU) == ISO14B_APDU) {
1734 status = iso14443b_apdu(cmd, len, buf);
1735 cmd_send(CMD_ACK, status, status, 0, buf, status);
1736 }
1737
1738 if ((param & ISO14B_RAW) == ISO14B_RAW) {
1739 if((param & ISO14B_APPEND_CRC) == ISO14B_APPEND_CRC) {
1740 AppendCrc14443b(cmd, len);
1741 len += 2;
1742 }
1743
1744 CodeAndTransmit14443bAsReader(cmd, len); // raw
1745 GetTagSamplesFor14443bDemod(); // raw
1746
1747 sendlen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1748 status = (Demod.len > 0) ? 0 : 1;
1749 cmd_send(CMD_ACK, status, sendlen, 0, Demod.output, sendlen);
1750 }
1751
1752 // turn off trigger (LED_A)
1753 if ((param & ISO14B_REQUEST_TRIGGER) == ISO14B_REQUEST_TRIGGER)
1754 iso14b_set_trigger(FALSE);
1755
1756 // turn off antenna et al
1757 // we don't send a HALT command.
1758 if ((param & ISO14B_DISCONNECT) == ISO14B_DISCONNECT) {
1759 if (MF_DBGLEVEL > 3) Dbprintf("disconnect");
1760 switch_off(); // disconnect raw
1761 } else {
1762 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1763 }
1764
1765 }
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