1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, March 2006
3 // iZsh <izsh at fail0verflow.com>, June 2014
4 //-----------------------------------------------------------------------------
7 `include "lo_passthru.v"
8 `include "lo_edge_detect.v"
10 `include "clk_divider.v"
13 input spck, output miso, input mosi, input ncs,
14 input pck0, input ck_1356meg, input ck_1356megb,
15 output pwr_lo, output pwr_hi,
16 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
17 input [7:0] adc_d, output adc_clk, output adc_noe,
18 output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
19 input cross_hi, input cross_lo,
23 //-----------------------------------------------------------------------------
24 // The SPI receiver. This sets up the configuration word, which the rest of
25 // the logic looks at to determine how to connect the A/D and the coil
26 // drivers (i.e., which section gets it). Also assign some symbolic names
27 // to the configuration bits, for use below.
28 //-----------------------------------------------------------------------------
37 case(shift_reg[15:12])
40 conf_word <= shift_reg[7:0];
41 if (shift_reg[7:0] == 8'b00000001) begin // LF edge detect
42 user_byte1 <= 127; // default threshold
45 4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
46 4'b0011: user_byte1 <= shift_reg[7:0]; // FPGA_CMD_SET_USER_BYTE1
50 always @(posedge spck)
54 shift_reg[15:1] <= shift_reg[14:0];
59 wire [2:0] major_mode = conf_word[7:5];
61 // For the low-frequency configuration:
62 wire lf_field = conf_word[0];
63 wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
64 wire [7:0] lf_ed_threshold = user_byte1;
66 //-----------------------------------------------------------------------------
67 // And then we instantiate the modules corresponding to each of the FPGA's
68 // major modes, and use muxes to connect the outputs of the active mode to
70 //-----------------------------------------------------------------------------
73 clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
76 pck0, pck_cnt, pck_divclk,
77 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
79 lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
85 lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
94 le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
96 le_ssp_frame, ssp_dout, le_ssp_clk,
100 lf_ed_toggle_mode, lf_ed_threshold
104 // 000 -- LF reader (generic)
105 // 001 -- LF edge detect (generic)
106 // 010 -- LF passthrough
108 mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
109 mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
110 mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
111 mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
112 mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
113 mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
114 mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
115 mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
116 mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
117 mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
118 mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
120 // In all modes, let the ADC's outputs be enabled.
121 assign adc_noe = 1'b0;