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FIX: "lf sim" after changes to ticks timers on device side, there was a "starticks...
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 #ifndef SHORT_COIL
23 # define SHORT_COIL() LOW(GPIO_SSC_DOUT)
24 #endif
25 #ifndef OPEN_COIL
26 # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
27 #endif
28
29 /**
30 * Function to do a modulation and then get samples.
31 * @param delay_off
32 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
33 * @param useHighFreg
34 * @param command
35 */
36 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
37 {
38 /* Make sure the tag is reset */
39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
41 SpinDelay(200);
42
43 uint16_t period_0 = periods >> 16;
44 uint16_t period_1 = periods & 0xFFFF;
45
46 // 95 == 125 KHz 88 == 124.8 KHz
47 int divisor_used = (useHighFreq) ? 88 : 95;
48 sample_config sc = { 0,0,1, divisor_used, 0};
49 setSamplingConfig(&sc);
50
51 //clear read buffer
52 BigBuf_Clear_keep_EM();
53
54 LFSetupFPGAForADC(sc.divisor, 1);
55
56 // And a little more time for the tag to fully power up
57 SpinDelay(50);
58
59 // now modulate the reader field
60 while(*command != '\0' && *command != ' ') {
61 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
62 LED_D_OFF();
63 WaitUS(delay_off);
64 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
65
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
67 LED_D_ON();
68 if(*(command++) == '0')
69 WaitUS(period_0);
70 else
71 WaitUS(period_1);
72 }
73 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
74 LED_D_OFF();
75 WaitUS(delay_off);
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
78
79 // now do the read
80 DoAcquisition_config(false);
81 }
82
83 /* blank r/w tag data stream
84 ...0000000000000000 01111111
85 1010101010101010101010101010101010101010101010101010101010101010
86 0011010010100001
87 01111111
88 101010101010101[0]000...
89
90 [5555fe852c5555555555555555fe0000]
91 */
92 void ReadTItag(void)
93 {
94 // some hardcoded initial params
95 // when we read a TI tag we sample the zerocross line at 2Mhz
96 // TI tags modulate a 1 as 16 cycles of 123.2Khz
97 // TI tags modulate a 0 as 16 cycles of 134.2Khz
98 #define FSAMPLE 2000000
99 #define FREQLO 123200
100 #define FREQHI 134200
101
102 signed char *dest = (signed char *)BigBuf_get_addr();
103 uint16_t n = BigBuf_max_traceLen();
104 // 128 bit shift register [shift3:shift2:shift1:shift0]
105 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
106
107 int i, cycles=0, samples=0;
108 // how many sample points fit in 16 cycles of each frequency
109 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
110 // when to tell if we're close enough to one freq or another
111 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
112
113 // TI tags charge at 134.2Khz
114 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
115 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
116
117 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
118 // connects to SSP_DIN and the SSP_DOUT logic level controls
119 // whether we're modulating the antenna (high)
120 // or listening to the antenna (low)
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
122
123 // get TI tag data into the buffer
124 AcquireTiType();
125
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
127
128 for (i=0; i<n-1; i++) {
129 // count cycles by looking for lo to hi zero crossings
130 if ( (dest[i]<0) && (dest[i+1]>0) ) {
131 cycles++;
132 // after 16 cycles, measure the frequency
133 if (cycles>15) {
134 cycles=0;
135 samples=i-samples; // number of samples in these 16 cycles
136
137 // TI bits are coming to us lsb first so shift them
138 // right through our 128 bit right shift register
139 shift0 = (shift0>>1) | (shift1 << 31);
140 shift1 = (shift1>>1) | (shift2 << 31);
141 shift2 = (shift2>>1) | (shift3 << 31);
142 shift3 >>= 1;
143
144 // check if the cycles fall close to the number
145 // expected for either the low or high frequency
146 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
147 // low frequency represents a 1
148 shift3 |= (1<<31);
149 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
150 // high frequency represents a 0
151 } else {
152 // probably detected a gay waveform or noise
153 // use this as gaydar or discard shift register and start again
154 shift3 = shift2 = shift1 = shift0 = 0;
155 }
156 samples = i;
157
158 // for each bit we receive, test if we've detected a valid tag
159
160 // if we see 17 zeroes followed by 6 ones, we might have a tag
161 // remember the bits are backwards
162 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
163 // if start and end bytes match, we have a tag so break out of the loop
164 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
165 cycles = 0xF0B; //use this as a flag (ugly but whatever)
166 break;
167 }
168 }
169 }
170 }
171 }
172
173 // if flag is set we have a tag
174 if (cycles!=0xF0B) {
175 DbpString("Info: No valid tag detected.");
176 } else {
177 // put 64 bit data into shift1 and shift0
178 shift0 = (shift0>>24) | (shift1 << 8);
179 shift1 = (shift1>>24) | (shift2 << 8);
180
181 // align 16 bit crc into lower half of shift2
182 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
183
184 // if r/w tag, check ident match
185 if (shift3 & (1<<15) ) {
186 DbpString("Info: TI tag is rewriteable");
187 // only 15 bits compare, last bit of ident is not valid
188 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
189 DbpString("Error: Ident mismatch!");
190 } else {
191 DbpString("Info: TI tag ident is valid");
192 }
193 } else {
194 DbpString("Info: TI tag is readonly");
195 }
196
197 // WARNING the order of the bytes in which we calc crc below needs checking
198 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
199 // bytes in reverse or something
200 // calculate CRC
201 uint32_t crc=0;
202
203 crc = update_crc16(crc, (shift0)&0xff);
204 crc = update_crc16(crc, (shift0>>8)&0xff);
205 crc = update_crc16(crc, (shift0>>16)&0xff);
206 crc = update_crc16(crc, (shift0>>24)&0xff);
207 crc = update_crc16(crc, (shift1)&0xff);
208 crc = update_crc16(crc, (shift1>>8)&0xff);
209 crc = update_crc16(crc, (shift1>>16)&0xff);
210 crc = update_crc16(crc, (shift1>>24)&0xff);
211
212 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
213 if (crc != (shift2&0xffff)) {
214 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
215 } else {
216 DbpString("Info: CRC is good");
217 }
218 }
219 }
220
221 void WriteTIbyte(uint8_t b)
222 {
223 int i = 0;
224
225 // modulate 8 bits out to the antenna
226 for (i=0; i<8; i++)
227 {
228 if ( b & ( 1 << i ) ) {
229 // stop modulating antenna 1ms
230 LOW(GPIO_SSC_DOUT);
231 WaitUS(1000);
232 // modulate antenna 1ms
233 HIGH(GPIO_SSC_DOUT);
234 WaitUS(1000);
235 } else {
236 // stop modulating antenna 1ms
237 LOW(GPIO_SSC_DOUT);
238 WaitUS(300);
239 // modulate antenna 1m
240 HIGH(GPIO_SSC_DOUT);
241 WaitUS(1700);
242 }
243 }
244 }
245
246 void AcquireTiType(void)
247 {
248 int i, j, n;
249 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
250 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
251 #define TIBUFLEN 1250
252
253 // clear buffer
254 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
255
256 //clear buffer now so it does not interfere with timing later
257 BigBuf_Clear_ext(false);
258
259 // Set up the synchronous serial port
260 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
261 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
262
263 // steal this pin from the SSP and use it to control the modulation
264 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
265 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
266
267 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
268 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
269
270 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
271 // 48/2 = 24 MHz clock must be divided by 12
272 AT91C_BASE_SSC->SSC_CMR = 12;
273
274 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
275 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
276 AT91C_BASE_SSC->SSC_TCMR = 0;
277 AT91C_BASE_SSC->SSC_TFMR = 0;
278 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
279 LED_D_ON();
280
281 // modulate antenna
282 HIGH(GPIO_SSC_DOUT);
283
284 // Charge TI tag for 50ms.
285 SpinDelay(50);
286
287 // stop modulating antenna and listen
288 LOW(GPIO_SSC_DOUT);
289
290 LED_D_OFF();
291
292 i = 0;
293 for(;;) {
294 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
295 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
296 i++; if(i >= TIBUFLEN) break;
297 }
298 WDT_HIT();
299 }
300
301 // return stolen pin to SSP
302 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
303 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
304
305 char *dest = (char *)BigBuf_get_addr();
306 n = TIBUFLEN * 32;
307
308 // unpack buffer
309 for (i = TIBUFLEN-1; i >= 0; i--) {
310 for (j = 0; j < 32; j++) {
311 if(buf[i] & (1 << j)) {
312 dest[--n] = 1;
313 } else {
314 dest[--n] = -1;
315 }
316 }
317 }
318 }
319
320 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
321 // if crc provided, it will be written with the data verbatim (even if bogus)
322 // if not provided a valid crc will be computed from the data and written.
323 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
324 {
325 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
326 if(crc == 0) {
327 crc = update_crc16(crc, (idlo)&0xff);
328 crc = update_crc16(crc, (idlo>>8)&0xff);
329 crc = update_crc16(crc, (idlo>>16)&0xff);
330 crc = update_crc16(crc, (idlo>>24)&0xff);
331 crc = update_crc16(crc, (idhi)&0xff);
332 crc = update_crc16(crc, (idhi>>8)&0xff);
333 crc = update_crc16(crc, (idhi>>16)&0xff);
334 crc = update_crc16(crc, (idhi>>24)&0xff);
335 }
336 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
337
338 // TI tags charge at 134.2Khz
339 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
340 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
341 // connects to SSP_DIN and the SSP_DOUT logic level controls
342 // whether we're modulating the antenna (high)
343 // or listening to the antenna (low)
344 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
345 LED_A_ON();
346
347 // steal this pin from the SSP and use it to control the modulation
348 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
349 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
350
351 // writing algorithm:
352 // a high bit consists of a field off for 1ms and field on for 1ms
353 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
354 // initiate a charge time of 50ms (field on) then immediately start writing bits
355 // start by writing 0xBB (keyword) and 0xEB (password)
356 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
357 // finally end with 0x0300 (write frame)
358 // all data is sent lsb first
359 // finish with 15ms programming time
360
361 // modulate antenna
362 HIGH(GPIO_SSC_DOUT);
363 SpinDelay(50); // charge time
364
365 WriteTIbyte(0xbb); // keyword
366 WriteTIbyte(0xeb); // password
367 WriteTIbyte( (idlo )&0xff );
368 WriteTIbyte( (idlo>>8 )&0xff );
369 WriteTIbyte( (idlo>>16)&0xff );
370 WriteTIbyte( (idlo>>24)&0xff );
371 WriteTIbyte( (idhi )&0xff );
372 WriteTIbyte( (idhi>>8 )&0xff );
373 WriteTIbyte( (idhi>>16)&0xff );
374 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
375 WriteTIbyte( (crc )&0xff ); // crc lo
376 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
377 WriteTIbyte(0x00); // write frame lo
378 WriteTIbyte(0x03); // write frame hi
379 HIGH(GPIO_SSC_DOUT);
380 SpinDelay(50); // programming time
381
382 LED_A_OFF();
383
384 // get TI tag data into the buffer
385 AcquireTiType();
386
387 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
388 DbpString("Now use `lf ti read` to check");
389 }
390
391 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
392 {
393 int i = 0;
394 uint8_t *tab = BigBuf_get_addr();
395
396 StartTicks();
397
398 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
399
400 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
401 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
402 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
403
404 for(;;) {
405 WDT_HIT();
406
407 if (ledcontrol) LED_D_ON();
408
409 //wait until SSC_CLK goes HIGH
410 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
411 WDT_HIT();
412 if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
413 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
414 LED_D_OFF();
415 return;
416 }
417 }
418
419 if(tab[i])
420 OPEN_COIL();
421 else
422 SHORT_COIL();
423
424 if (ledcontrol) LED_D_OFF();
425
426 //wait until SSC_CLK goes LOW
427 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
428 WDT_HIT();
429 if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
430 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
431 LED_D_OFF();
432 return;
433 }
434 }
435
436 i++;
437 if(i == period) {
438 i = 0;
439 if (gap) {
440 WDT_HIT();
441 SHORT_COIL();
442 WaitUS(gap);
443 }
444 }
445 }
446 }
447
448 #define DEBUG_FRAME_CONTENTS 1
449 void SimulateTagLowFrequencyBidir(int divisor, int t0)
450 {
451 }
452
453 // compose fc/8 fc/10 waveform (FSK2)
454 static void fc(int c, int *n)
455 {
456 uint8_t *dest = BigBuf_get_addr();
457 int idx;
458
459 // for when we want an fc8 pattern every 4 logical bits
460 if(c==0) {
461 dest[((*n)++)]=1;
462 dest[((*n)++)]=1;
463 dest[((*n)++)]=1;
464 dest[((*n)++)]=1;
465 dest[((*n)++)]=0;
466 dest[((*n)++)]=0;
467 dest[((*n)++)]=0;
468 dest[((*n)++)]=0;
469 }
470
471 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
472 if(c==8) {
473 for (idx=0; idx<6; idx++) {
474 dest[((*n)++)]=1;
475 dest[((*n)++)]=1;
476 dest[((*n)++)]=1;
477 dest[((*n)++)]=1;
478 dest[((*n)++)]=0;
479 dest[((*n)++)]=0;
480 dest[((*n)++)]=0;
481 dest[((*n)++)]=0;
482 }
483 }
484
485 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
486 if(c==10) {
487 for (idx=0; idx<5; idx++) {
488 dest[((*n)++)]=1;
489 dest[((*n)++)]=1;
490 dest[((*n)++)]=1;
491 dest[((*n)++)]=1;
492 dest[((*n)++)]=1;
493 dest[((*n)++)]=0;
494 dest[((*n)++)]=0;
495 dest[((*n)++)]=0;
496 dest[((*n)++)]=0;
497 dest[((*n)++)]=0;
498 }
499 }
500 }
501 // compose fc/X fc/Y waveform (FSKx)
502 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
503 {
504 uint8_t *dest = BigBuf_get_addr();
505 uint8_t halfFC = fc/2;
506 uint8_t wavesPerClock = clock/fc;
507 uint8_t mod = clock % fc; //modifier
508 uint8_t modAdj = fc/mod; //how often to apply modifier
509 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
510 // loop through clock - step field clock
511 for (uint8_t idx=0; idx < wavesPerClock; idx++){
512 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
513 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
514 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
515 *n += fc;
516 }
517 if (mod>0) (*modCnt)++;
518 if ((mod>0) && modAdjOk){ //fsk2
519 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
520 memset(dest+(*n), 0, fc-halfFC);
521 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
522 *n += fc;
523 }
524 }
525 if (mod>0 && !modAdjOk){ //fsk1
526 memset(dest+(*n), 0, mod-(mod/2));
527 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
528 *n += mod;
529 }
530 }
531
532 // prepare a waveform pattern in the buffer based on the ID given then
533 // simulate a HID tag until the button is pressed
534 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
535 {
536 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
537 set_tracing(FALSE);
538
539 int n = 0, i = 0;
540 /*
541 HID tag bitstream format
542 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
543 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
544 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
545 A fc8 is inserted before every 4 bits
546 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
547 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
548 */
549
550 if (hi > 0xFFF) {
551 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
552 return;
553 }
554 fc(0,&n);
555 // special start of frame marker containing invalid bit sequences
556 fc(8, &n); fc(8, &n); // invalid
557 fc(8, &n); fc(10, &n); // logical 0
558 fc(10, &n); fc(10, &n); // invalid
559 fc(8, &n); fc(10, &n); // logical 0
560
561 WDT_HIT();
562 // manchester encode bits 43 to 32
563 for (i=11; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((hi>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 WDT_HIT();
573 // manchester encode bits 31 to 0
574 for (i=31; i>=0; i--) {
575 if ((i%4)==3) fc(0,&n);
576 if ((lo>>i)&1) {
577 fc(10, &n); fc(8, &n); // low-high transition
578 } else {
579 fc(8, &n); fc(10, &n); // high-low transition
580 }
581 }
582 WDT_HIT();
583
584 if (ledcontrol) LED_A_ON();
585 SimulateTagLowFrequency(n, 0, ledcontrol);
586 if (ledcontrol) LED_A_OFF();
587 }
588
589 // prepare a waveform pattern in the buffer based on the ID given then
590 // simulate a FSK tag until the button is pressed
591 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
592 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
593 {
594 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
595
596 // free eventually allocated BigBuf memory
597 BigBuf_free(); BigBuf_Clear_ext(false);
598 clear_trace();
599 set_tracing(FALSE);
600
601 int ledcontrol = 1, n = 0, i = 0;
602 uint8_t fcHigh = arg1 >> 8;
603 uint8_t fcLow = arg1 & 0xFF;
604 uint16_t modCnt = 0;
605 uint8_t clk = arg2 & 0xFF;
606 uint8_t invert = (arg2 >> 8) & 1;
607
608 for (i=0; i<size; i++){
609
610 if (BitStream[i] == invert)
611 fcAll(fcLow, &n, clk, &modCnt);
612 else
613 fcAll(fcHigh, &n, clk, &modCnt);
614 }
615 WDT_HIT();
616
617 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
618
619 if (ledcontrol) LED_A_ON();
620 SimulateTagLowFrequency(n, 0, ledcontrol);
621 if (ledcontrol) LED_A_OFF();
622 }
623
624 // compose ask waveform for one bit(ASK)
625 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
626 {
627 uint8_t *dest = BigBuf_get_addr();
628 uint8_t halfClk = clock/2;
629 // c = current bit 1 or 0
630 if (manchester==1){
631 memset(dest+(*n), c, halfClk);
632 memset(dest+(*n) + halfClk, c^1, halfClk);
633 } else {
634 memset(dest+(*n), c, clock);
635 }
636 *n += clock;
637 }
638
639 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
640 {
641 uint8_t *dest = BigBuf_get_addr();
642 uint8_t halfClk = clock/2;
643 if (c){
644 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
645 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
646 } else {
647 memset(dest+(*n), c ^ *phase, clock);
648 *phase ^= 1;
649 }
650 *n += clock;
651 }
652
653 static void stAskSimBit(int *n, uint8_t clock) {
654 uint8_t *dest = BigBuf_get_addr();
655 uint8_t halfClk = clock/2;
656 //ST = .5 high .5 low 1.5 high .5 low 1 high
657 memset(dest+(*n), 1, halfClk);
658 memset(dest+(*n) + halfClk, 0, halfClk);
659 memset(dest+(*n) + clock, 1, clock + halfClk);
660 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
661 memset(dest+(*n) + clock*3, 1, clock);
662 *n += clock*4;
663 }
664
665 // args clock, ask/man or askraw, invert, transmission separator
666 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
667 {
668 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
669 set_tracing(FALSE);
670
671 int ledcontrol = 1, n = 0, i = 0;
672 uint8_t clk = (arg1 >> 8) & 0xFF;
673 uint8_t encoding = arg1 & 0xFF;
674 uint8_t separator = arg2 & 1;
675 uint8_t invert = (arg2 >> 8) & 1;
676
677 if (encoding == 2){ //biphase
678 uint8_t phase = 0;
679 for (i=0; i<size; i++){
680 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
681 }
682 if (phase == 1) { //run a second set inverted to keep phase in check
683 for (i=0; i<size; i++){
684 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
685 }
686 }
687 } else { // ask/manchester || ask/raw
688 for (i=0; i<size; i++){
689 askSimBit(BitStream[i]^invert, &n, clk, encoding);
690 }
691 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
692 for (i=0; i<size; i++){
693 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
694 }
695 }
696 }
697 if (separator==1 && encoding == 1)
698 stAskSimBit(&n, clk);
699 else if (separator==1)
700 Dbprintf("sorry but separator option not yet available");
701
702 WDT_HIT();
703
704 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
705
706 if (ledcontrol) LED_A_ON();
707 SimulateTagLowFrequency(n, 0, ledcontrol);
708 if (ledcontrol) LED_A_OFF();
709 }
710
711 //carrier can be 2,4 or 8
712 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
713 {
714 uint8_t *dest = BigBuf_get_addr();
715 uint8_t halfWave = waveLen/2;
716 //uint8_t idx;
717 int i = 0;
718 if (phaseChg){
719 // write phase change
720 memset(dest+(*n), *curPhase^1, halfWave);
721 memset(dest+(*n) + halfWave, *curPhase, halfWave);
722 *n += waveLen;
723 *curPhase ^= 1;
724 i += waveLen;
725 }
726 //write each normal clock wave for the clock duration
727 for (; i < clk; i+=waveLen){
728 memset(dest+(*n), *curPhase, halfWave);
729 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
730 *n += waveLen;
731 }
732 }
733
734 // args clock, carrier, invert,
735 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
736 {
737 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
738 set_tracing(FALSE);
739
740 int ledcontrol = 1, n = 0, i = 0;
741 uint8_t clk = arg1 >> 8;
742 uint8_t carrier = arg1 & 0xFF;
743 uint8_t invert = arg2 & 0xFF;
744 uint8_t curPhase = 0;
745 for (i=0; i<size; i++){
746 if (BitStream[i] == curPhase){
747 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
748 } else {
749 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
750 }
751 }
752
753 WDT_HIT();
754
755 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
756
757 if (ledcontrol) LED_A_ON();
758 SimulateTagLowFrequency(n, 0, ledcontrol);
759 if (ledcontrol) LED_A_OFF();
760 }
761
762 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
763 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
764 {
765 uint8_t *dest = BigBuf_get_addr();
766 size_t size = 0;
767 uint32_t hi2=0, hi=0, lo=0;
768 int idx=0;
769 // Configure to go in 125Khz listen mode
770 LFSetupFPGAForADC(95, true);
771
772 //clear read buffer
773 BigBuf_Clear_keep_EM();
774
775 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
776
777 WDT_HIT();
778 if (ledcontrol) LED_A_ON();
779
780 DoAcquisition_default(-1,true);
781 // FSK demodulator
782 size = 50*128*2; //big enough to catch 2 sequences of largest format
783 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
784
785 if (idx>0 && lo>0 && (size==96 || size==192)){
786 // go over previously decoded manchester data and decode into usable tag ID
787 if (hi2 != 0){ //extra large HID tags 88/192 bits
788 Dbprintf("TAG ID: %x%08x%08x (%d)",
789 (unsigned int) hi2,
790 (unsigned int) hi,
791 (unsigned int) lo,
792 (unsigned int) (lo>>1) & 0xFFFF
793 );
794 } else { //standard HID tags 44/96 bits
795 uint8_t bitlen = 0;
796 uint32_t fc = 0;
797 uint32_t cardnum = 0;
798
799 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
800 uint32_t lo2=0;
801 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
802 uint8_t idx3 = 1;
803 while(lo2 > 1){ //find last bit set to 1 (format len bit)
804 lo2=lo2 >> 1;
805 idx3++;
806 }
807 bitlen = idx3+19;
808 fc =0;
809 cardnum=0;
810 if(bitlen == 26){
811 cardnum = (lo>>1)&0xFFFF;
812 fc = (lo>>17)&0xFF;
813 }
814 if(bitlen == 37){
815 cardnum = (lo>>1)&0x7FFFF;
816 fc = ((hi&0xF)<<12)|(lo>>20);
817 }
818 if(bitlen == 34){
819 cardnum = (lo>>1)&0xFFFF;
820 fc= ((hi&1)<<15)|(lo>>17);
821 }
822 if(bitlen == 35){
823 cardnum = (lo>>1)&0xFFFFF;
824 fc = ((hi&1)<<11)|(lo>>21);
825 }
826 }
827 else { //if bit 38 is not set then 37 bit format is used
828 bitlen= 37;
829 fc =0;
830 cardnum=0;
831 if(bitlen==37){
832 cardnum = (lo>>1)&0x7FFFF;
833 fc = ((hi&0xF)<<12)|(lo>>20);
834 }
835 }
836 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
837 (unsigned int) hi,
838 (unsigned int) lo,
839 (unsigned int) (lo>>1) & 0xFFFF,
840 (unsigned int) bitlen,
841 (unsigned int) fc,
842 (unsigned int) cardnum);
843 }
844 if (findone){
845 if (ledcontrol) LED_A_OFF();
846 *high = hi;
847 *low = lo;
848 return;
849 }
850 // reset
851 }
852 hi2 = hi = lo = idx = 0;
853 WDT_HIT();
854 }
855 DbpString("Stopped");
856 if (ledcontrol) LED_A_OFF();
857 }
858
859 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
860 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
861 {
862 uint8_t *dest = BigBuf_get_addr();
863 size_t size;
864 int idx=0;
865 //clear read buffer
866 BigBuf_Clear_keep_EM();
867 // Configure to go in 125Khz listen mode
868 LFSetupFPGAForADC(95, true);
869
870 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
871
872 WDT_HIT();
873 if (ledcontrol) LED_A_ON();
874
875 DoAcquisition_default(-1,true);
876 // FSK demodulator
877 size = 50*128*2; //big enough to catch 2 sequences of largest format
878 idx = AWIDdemodFSK(dest, &size);
879
880 if (idx<=0 || size!=96) continue;
881 // Index map
882 // 0 10 20 30 40 50 60
883 // | | | | | | |
884 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
885 // -----------------------------------------------------------------------------
886 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
887 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
888 // |---26 bit---| |-----117----||-------------142-------------|
889 // b = format bit len, o = odd parity of last 3 bits
890 // f = facility code, c = card number
891 // w = wiegand parity
892 // (26 bit format shown)
893
894 //get raw ID before removing parities
895 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
896 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
897 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
898
899 size = removeParity(dest, idx+8, 4, 1, 88);
900 if (size != 66) continue;
901
902 // Index map
903 // 0 10 20 30 40 50 60
904 // | | | | | | |
905 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
906 // -----------------------------------------------------------------------------
907 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
908 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
909 // |26 bit| |-117--| |-----142------|
910 //
911 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
912 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
913 // |50 bit| |----4000------||-----------2248975-------------|
914 //
915 // b = format bit len, o = odd parity of last 3 bits
916 // f = facility code, c = card number
917 // w = wiegand parity
918
919 uint32_t fc = 0;
920 uint32_t cardnum = 0;
921 uint32_t code1 = 0;
922 uint32_t code2 = 0;
923 uint8_t fmtLen = bytebits_to_byte(dest,8);
924 switch(fmtLen) {
925 case 26:
926 fc = bytebits_to_byte(dest + 9, 8);
927 cardnum = bytebits_to_byte(dest + 17, 16);
928 code1 = bytebits_to_byte(dest + 8,fmtLen);
929 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
930 break;
931 case 50:
932 fc = bytebits_to_byte(dest + 9, 16);
933 cardnum = bytebits_to_byte(dest + 25, 32);
934 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
935 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
936 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
937 break;
938 default:
939 if (fmtLen > 32 ) {
940 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
941 code1 = bytebits_to_byte(dest+8,fmtLen-32);
942 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
943 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
944 } else {
945 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
946 code1 = bytebits_to_byte(dest+8,fmtLen);
947 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
948 }
949 break;
950 }
951 if (findone){
952 if (ledcontrol) LED_A_OFF();
953 return;
954 }
955 idx = 0;
956 WDT_HIT();
957 }
958 DbpString("Stopped");
959 if (ledcontrol) LED_A_OFF();
960 }
961
962 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
963 {
964 uint8_t *dest = BigBuf_get_addr();
965
966 size_t size=0, idx=0;
967 int clk=0, invert=0, errCnt=0, maxErr=20;
968 uint32_t hi=0;
969 uint64_t lo=0;
970 //clear read buffer
971 BigBuf_Clear_keep_EM();
972 // Configure to go in 125Khz listen mode
973 LFSetupFPGAForADC(95, true);
974
975 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
976
977 WDT_HIT();
978 if (ledcontrol) LED_A_ON();
979
980 DoAcquisition_default(-1,true);
981 size = BigBuf_max_traceLen();
982 //askdemod and manchester decode
983 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
984 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
985 WDT_HIT();
986
987 if (errCnt<0) continue;
988
989 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
990 if (errCnt){
991 if (size>64){
992 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
993 hi,
994 (uint32_t)(lo>>32),
995 (uint32_t)lo,
996 (uint32_t)(lo&0xFFFF),
997 (uint32_t)((lo>>16LL) & 0xFF),
998 (uint32_t)(lo & 0xFFFFFF));
999 } else {
1000 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1001 (uint32_t)(lo>>32),
1002 (uint32_t)lo,
1003 (uint32_t)(lo&0xFFFF),
1004 (uint32_t)((lo>>16LL) & 0xFF),
1005 (uint32_t)(lo & 0xFFFFFF));
1006 }
1007
1008 if (findone){
1009 if (ledcontrol) LED_A_OFF();
1010 *high=lo>>32;
1011 *low=lo & 0xFFFFFFFF;
1012 return;
1013 }
1014 }
1015 WDT_HIT();
1016 hi = lo = size = idx = 0;
1017 clk = invert = errCnt = 0;
1018 }
1019 DbpString("Stopped");
1020 if (ledcontrol) LED_A_OFF();
1021 }
1022
1023 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1024 {
1025 uint8_t *dest = BigBuf_get_addr();
1026 int idx=0;
1027 uint32_t code=0, code2=0;
1028 uint8_t version=0;
1029 uint8_t facilitycode=0;
1030 uint16_t number=0;
1031 uint8_t crc = 0;
1032 uint16_t calccrc = 0;
1033
1034 //clear read buffer
1035 BigBuf_Clear_keep_EM();
1036
1037 // Configure to go in 125Khz listen mode
1038 LFSetupFPGAForADC(95, true);
1039
1040 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1041 WDT_HIT();
1042 if (ledcontrol) LED_A_ON();
1043 DoAcquisition_default(-1,true);
1044 //fskdemod and get start index
1045 WDT_HIT();
1046 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1047 if (idx<0) continue;
1048 //valid tag found
1049
1050 //Index map
1051 //0 10 20 30 40 50 60
1052 //| | | | | | |
1053 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1054 //-----------------------------------------------------------------------------
1055 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1056 //
1057 //Checksum:
1058 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1059 //preamble F0 E0 01 03 B6 75
1060 // How to calc checksum,
1061 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1062 // F0 + E0 + 01 + 03 + B6 = 28A
1063 // 28A & FF = 8A
1064 // FF - 8A = 75
1065 // Checksum: 0x75
1066 //XSF(version)facility:codeone+codetwo
1067 //Handle the data
1068 if(findone){ //only print binary if we are doing one
1069 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1070 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1071 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1072 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1073 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1074 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1075 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1076 }
1077 code = bytebits_to_byte(dest+idx,32);
1078 code2 = bytebits_to_byte(dest+idx+32,32);
1079 version = bytebits_to_byte(dest+idx+27,8); //14,4
1080 facilitycode = bytebits_to_byte(dest+idx+18,8);
1081 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1082
1083 crc = bytebits_to_byte(dest+idx+54,8);
1084 for (uint8_t i=1; i<6; ++i)
1085 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1086 calccrc &= 0xff;
1087 calccrc = 0xff - calccrc;
1088
1089 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1090
1091 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1092 // if we're only looking for one tag
1093 if (findone){
1094 if (ledcontrol) LED_A_OFF();
1095 *high=code;
1096 *low=code2;
1097 return;
1098 }
1099 code=code2=0;
1100 version=facilitycode=0;
1101 number=0;
1102 idx=0;
1103
1104 WDT_HIT();
1105 }
1106 DbpString("Stopped");
1107 if (ledcontrol) LED_A_OFF();
1108 }
1109
1110 /*------------------------------
1111 * T5555/T5557/T5567/T5577 routines
1112 *------------------------------
1113 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1114 *
1115 * Relevant communication times in microsecond
1116 * To compensate antenna falling times shorten the write times
1117 * and enlarge the gap ones.
1118 * Q5 tags seems to have issues when these values changes.
1119 */
1120
1121 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
1122 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
1123 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
1124 #define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
1125 #define READ_GAP 15*8
1126
1127 // VALUES TAKEN FROM EM4x function: SendForward
1128 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1129 // WRITE_GAP = 128; (16*8)
1130 // WRITE_1 = 256 32*8; (32*8)
1131
1132 // These timings work for 4469/4269/4305 (with the 55*8 above)
1133 // WRITE_0 = 23*8 , 9*8
1134
1135 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1136 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1137 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1138 // T0 = TIMER_CLOCK1 / 125000 = 192
1139 // 1 Cycle = 8 microseconds(us) == 1 field clock
1140
1141 // new timer:
1142 // = 1us = 1.5ticks
1143 // 1fc = 8us = 12ticks
1144 void TurnReadLFOn(uint32_t delay) {
1145 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1146
1147 // measure antenna strength.
1148 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1149
1150 // Give it a bit of time for the resonant antenna to settle.
1151 WaitUS(delay);
1152 }
1153
1154 // Write one bit to card
1155 void T55xxWriteBit(int bit) {
1156 if (!bit)
1157 TurnReadLFOn(WRITE_0);
1158 else
1159 TurnReadLFOn(WRITE_1);
1160 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1161 WaitUS(WRITE_GAP);
1162 }
1163
1164 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1165 void T55xxResetRead(void) {
1166 LED_A_ON();
1167 //clear buffer now so it does not interfere with timing later
1168 BigBuf_Clear_keep_EM();
1169
1170 // Set up FPGA, 125kHz
1171 LFSetupFPGAForADC(95, true);
1172
1173 // Trigger T55x7 in mode.
1174 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1175 WaitUS(START_GAP);
1176
1177 // reset tag - op code 00
1178 T55xxWriteBit(0);
1179 T55xxWriteBit(0);
1180
1181 // Turn field on to read the response
1182 TurnReadLFOn(READ_GAP);
1183
1184 // Acquisition
1185 doT55x7Acquisition(BigBuf_max_traceLen());
1186
1187 // Turn the field off
1188 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1189 cmd_send(CMD_ACK,0,0,0,0,0);
1190 LED_A_OFF();
1191 }
1192
1193 // Write one card block in page 0, no lock
1194 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1195 LED_A_ON();
1196 bool PwdMode = arg & 0x1;
1197 uint8_t Page = (arg & 0x2)>>1;
1198 uint32_t i = 0;
1199
1200 // Set up FPGA, 125kHz
1201 LFSetupFPGAForADC(95, true);
1202
1203 // Trigger T55x7 in mode.
1204 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1205 WaitUS(START_GAP);
1206
1207 // Opcode 10
1208 T55xxWriteBit(1);
1209 T55xxWriteBit(Page); //Page 0
1210 if (PwdMode){
1211 // Send Pwd
1212 for (i = 0x80000000; i != 0; i >>= 1)
1213 T55xxWriteBit(Pwd & i);
1214 }
1215 // Send Lock bit
1216 T55xxWriteBit(0);
1217
1218 // Send Data
1219 for (i = 0x80000000; i != 0; i >>= 1)
1220 T55xxWriteBit(Data & i);
1221
1222 // Send Block number
1223 for (i = 0x04; i != 0; i >>= 1)
1224 T55xxWriteBit(Block & i);
1225
1226 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1227 // so wait a little more)
1228 TurnReadLFOn(20 * 1000);
1229
1230 //could attempt to do a read to confirm write took
1231 // as the tag should repeat back the new block
1232 // until it is reset, but to confirm it we would
1233 // need to know the current block 0 config mode
1234
1235 // turn field off
1236 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1237 LED_A_OFF();
1238 }
1239
1240 // Write one card block in page 0, no lock
1241 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1242 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1243 cmd_send(CMD_ACK,0,0,0,0,0);
1244 }
1245
1246 // Read one card block in page [page]
1247 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1248 LED_A_ON();
1249 bool PwdMode = arg0 & 0x1;
1250 uint8_t Page = (arg0 & 0x2) >> 1;
1251 uint32_t i = 0;
1252 bool RegReadMode = (Block == 0xFF);
1253
1254 //clear buffer now so it does not interfere with timing later
1255 BigBuf_Clear_keep_EM();
1256
1257 //make sure block is at max 7
1258 Block &= 0x7;
1259
1260 // Set up FPGA, 125kHz to power up the tag
1261 LFSetupFPGAForADC(95, true);
1262 SpinDelay(3);
1263
1264 // Trigger T55x7 Direct Access Mode with start gap
1265 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1266 WaitUS(START_GAP);
1267
1268 // Opcode 1[page]
1269 T55xxWriteBit(1);
1270 T55xxWriteBit(Page); //Page 0
1271
1272 if (PwdMode){
1273 // Send Pwd
1274 for (i = 0x80000000; i != 0; i >>= 1)
1275 T55xxWriteBit(Pwd & i);
1276 }
1277 // Send a zero bit separation
1278 T55xxWriteBit(0);
1279
1280 // Send Block number (if direct access mode)
1281 if (!RegReadMode)
1282 for (i = 0x04; i != 0; i >>= 1)
1283 T55xxWriteBit(Block & i);
1284
1285 // Turn field on to read the response
1286 TurnReadLFOn(READ_GAP);
1287
1288 // Acquisition
1289 doT55x7Acquisition(12000);
1290
1291 // Turn the field off
1292 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1293 cmd_send(CMD_ACK,0,0,0,0,0);
1294 LED_A_OFF();
1295 }
1296
1297 void T55xxWakeUp(uint32_t Pwd){
1298 LED_B_ON();
1299 uint32_t i = 0;
1300
1301 // Set up FPGA, 125kHz
1302 LFSetupFPGAForADC(95, true);
1303
1304 // Trigger T55x7 Direct Access Mode
1305 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1306 WaitUS(START_GAP);
1307
1308 // Opcode 10
1309 T55xxWriteBit(1);
1310 T55xxWriteBit(0); //Page 0
1311
1312 // Send Pwd
1313 for (i = 0x80000000; i != 0; i >>= 1)
1314 T55xxWriteBit(Pwd & i);
1315
1316 // Turn and leave field on to let the begin repeating transmission
1317 TurnReadLFOn(20*1000);
1318 }
1319
1320 /*-------------- Cloning routines -----------*/
1321 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1322 // write last block first and config block last (if included)
1323 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1324 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1325 }
1326
1327 // Copy HID id to card and setup block 0 config
1328 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1329 uint32_t data[] = {0,0,0,0,0,0,0};
1330 uint8_t last_block = 0;
1331
1332 if (longFMT){
1333 // Ensure no more than 84 bits supplied
1334 if (hi2 > 0xFFFFF) {
1335 DbpString("Tags can only have 84 bits.");
1336 return;
1337 }
1338 // Build the 6 data blocks for supplied 84bit ID
1339 last_block = 6;
1340 // load preamble (1D) & long format identifier (9E manchester encoded)
1341 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1342 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1343 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1344 data[3] = manchesterEncode2Bytes(hi >> 16);
1345 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1346 data[5] = manchesterEncode2Bytes(lo >> 16);
1347 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1348 } else {
1349 // Ensure no more than 44 bits supplied
1350 if (hi > 0xFFF) {
1351 DbpString("Tags can only have 44 bits.");
1352 return;
1353 }
1354 // Build the 3 data blocks for supplied 44bit ID
1355 last_block = 3;
1356 // load preamble
1357 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1358 data[2] = manchesterEncode2Bytes(lo >> 16);
1359 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1360 }
1361 // load chip config block
1362 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1363
1364 //TODO add selection of chip for Q5 or T55x7
1365 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1366
1367 LED_D_ON();
1368 // Program the data blocks for supplied ID
1369 // and the block 0 for HID format
1370 WriteT55xx(data, 0, last_block+1);
1371
1372 LED_D_OFF();
1373
1374 DbpString("DONE!");
1375 }
1376
1377 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1378 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1379 //TODO add selection of chip for Q5 or T55x7
1380 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1381 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1382
1383 LED_D_ON();
1384 // Program the data blocks for supplied ID
1385 // and the block 0 config
1386 WriteT55xx(data, 0, 3);
1387 LED_D_OFF();
1388 DbpString("DONE!");
1389 }
1390
1391 // Clone Indala 64-bit tag by UID to T55x7
1392 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1393 //Program the 2 data blocks for supplied 64bit UID
1394 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1395 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1396 //TODO add selection of chip for Q5 or T55x7
1397 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1398
1399 WriteT55xx(data, 0, 3);
1400 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1401 // T5567WriteBlock(0x603E1042,0);
1402 DbpString("DONE!");
1403 }
1404 // Clone Indala 224-bit tag by UID to T55x7
1405 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1406 //Program the 7 data blocks for supplied 224bit UID
1407 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1408 // and the block 0 for Indala224 format
1409 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1410 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1411 //TODO add selection of chip for Q5 or T55x7
1412 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1413 WriteT55xx(data, 0, 8);
1414 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1415 // T5567WriteBlock(0x603E10E2,0);
1416 DbpString("DONE!");
1417 }
1418 // clone viking tag to T55xx
1419 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1420 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1421 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1422 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1423 // Program the data blocks for supplied ID and the block 0 config
1424 WriteT55xx(data, 0, 3);
1425 LED_D_OFF();
1426 cmd_send(CMD_ACK,0,0,0,0,0);
1427 }
1428
1429 // Define 9bit header for EM410x tags
1430 #define EM410X_HEADER 0x1FF
1431 #define EM410X_ID_LENGTH 40
1432
1433 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1434 int i, id_bit;
1435 uint64_t id = EM410X_HEADER;
1436 uint64_t rev_id = 0; // reversed ID
1437 int c_parity[4]; // column parity
1438 int r_parity = 0; // row parity
1439 uint32_t clock = 0;
1440
1441 // Reverse ID bits given as parameter (for simpler operations)
1442 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1443 if (i < 32) {
1444 rev_id = (rev_id << 1) | (id_lo & 1);
1445 id_lo >>= 1;
1446 } else {
1447 rev_id = (rev_id << 1) | (id_hi & 1);
1448 id_hi >>= 1;
1449 }
1450 }
1451
1452 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1453 id_bit = rev_id & 1;
1454
1455 if (i % 4 == 0) {
1456 // Don't write row parity bit at start of parsing
1457 if (i)
1458 id = (id << 1) | r_parity;
1459 // Start counting parity for new row
1460 r_parity = id_bit;
1461 } else {
1462 // Count row parity
1463 r_parity ^= id_bit;
1464 }
1465
1466 // First elements in column?
1467 if (i < 4)
1468 // Fill out first elements
1469 c_parity[i] = id_bit;
1470 else
1471 // Count column parity
1472 c_parity[i % 4] ^= id_bit;
1473
1474 // Insert ID bit
1475 id = (id << 1) | id_bit;
1476 rev_id >>= 1;
1477 }
1478
1479 // Insert parity bit of last row
1480 id = (id << 1) | r_parity;
1481
1482 // Fill out column parity at the end of tag
1483 for (i = 0; i < 4; ++i)
1484 id = (id << 1) | c_parity[i];
1485
1486 // Add stop bit
1487 id <<= 1;
1488
1489 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1490 LED_D_ON();
1491
1492 // Write EM410x ID
1493 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1494
1495 clock = (card & 0xFF00) >> 8;
1496 clock = (clock == 0) ? 64 : clock;
1497 Dbprintf("Clock rate: %d", clock);
1498 if (card & 0xFF) { //t55x7
1499 clock = GetT55xxClockBit(clock);
1500 if (clock == 0) {
1501 Dbprintf("Invalid clock rate: %d", clock);
1502 return;
1503 }
1504 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1505 } else { //t5555 (Q5)
1506 clock = (clock-2)>>1; //n = (RF-2)/2
1507 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1508 }
1509
1510 WriteT55xx(data, 0, 3);
1511
1512 LED_D_OFF();
1513 Dbprintf("Tag %s written with 0x%08x%08x\n",
1514 card ? "T55x7":"T5555",
1515 (uint32_t)(id >> 32),
1516 (uint32_t)id);
1517 }
1518
1519 //-----------------------------------
1520 // EM4469 / EM4305 routines
1521 //-----------------------------------
1522 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1523 #define FWD_CMD_WRITE 0xA
1524 #define FWD_CMD_READ 0x9
1525 #define FWD_CMD_DISABLE 0x5
1526
1527 uint8_t forwardLink_data[64]; //array of forwarded bits
1528 uint8_t * forward_ptr; //ptr for forward message preparation
1529 uint8_t fwd_bit_sz; //forwardlink bit counter
1530 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1531
1532 //====================================================================
1533 // prepares command bits
1534 // see EM4469 spec
1535 //====================================================================
1536 //--------------------------------------------------------------------
1537 // VALUES TAKEN FROM EM4x function: SendForward
1538 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1539 // WRITE_GAP = 128; (16*8)
1540 // WRITE_1 = 256 32*8; (32*8)
1541
1542 // These timings work for 4469/4269/4305 (with the 55*8 above)
1543 // WRITE_0 = 23*8 , 9*8
1544
1545 uint8_t Prepare_Cmd( uint8_t cmd ) {
1546
1547 *forward_ptr++ = 0; //start bit
1548 *forward_ptr++ = 0; //second pause for 4050 code
1549
1550 *forward_ptr++ = cmd;
1551 cmd >>= 1;
1552 *forward_ptr++ = cmd;
1553 cmd >>= 1;
1554 *forward_ptr++ = cmd;
1555 cmd >>= 1;
1556 *forward_ptr++ = cmd;
1557
1558 return 6; //return number of emited bits
1559 }
1560
1561 //====================================================================
1562 // prepares address bits
1563 // see EM4469 spec
1564 //====================================================================
1565 uint8_t Prepare_Addr( uint8_t addr ) {
1566
1567 register uint8_t line_parity;
1568
1569 uint8_t i;
1570 line_parity = 0;
1571 for(i=0;i<6;i++) {
1572 *forward_ptr++ = addr;
1573 line_parity ^= addr;
1574 addr >>= 1;
1575 }
1576
1577 *forward_ptr++ = (line_parity & 1);
1578
1579 return 7; //return number of emited bits
1580 }
1581
1582 //====================================================================
1583 // prepares data bits intreleaved with parity bits
1584 // see EM4469 spec
1585 //====================================================================
1586 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1587
1588 register uint8_t line_parity;
1589 register uint8_t column_parity;
1590 register uint8_t i, j;
1591 register uint16_t data;
1592
1593 data = data_low;
1594 column_parity = 0;
1595
1596 for(i=0; i<4; i++) {
1597 line_parity = 0;
1598 for(j=0; j<8; j++) {
1599 line_parity ^= data;
1600 column_parity ^= (data & 1) << j;
1601 *forward_ptr++ = data;
1602 data >>= 1;
1603 }
1604 *forward_ptr++ = line_parity;
1605 if(i == 1)
1606 data = data_hi;
1607 }
1608
1609 for(j=0; j<8; j++) {
1610 *forward_ptr++ = column_parity;
1611 column_parity >>= 1;
1612 }
1613 *forward_ptr = 0;
1614
1615 return 45; //return number of emited bits
1616 }
1617
1618 //====================================================================
1619 // Forward Link send function
1620 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1621 // fwd_bit_count set with number of bits to be sent
1622 //====================================================================
1623 void SendForward(uint8_t fwd_bit_count) {
1624
1625 fwd_write_ptr = forwardLink_data;
1626 fwd_bit_sz = fwd_bit_count;
1627
1628 LED_D_ON();
1629
1630 // Set up FPGA, 125kHz
1631 LFSetupFPGAForADC(95, true);
1632
1633 // force 1st mod pulse (start gap must be longer for 4305)
1634 fwd_bit_sz--; //prepare next bit modulation
1635 fwd_write_ptr++;
1636 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1637 WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
1638 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1639 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1640
1641 // now start writting
1642 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1643 if(((*fwd_write_ptr++) & 1) == 1)
1644 WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1645 else {
1646 //These timings work for 4469/4269/4305 (with the 55*8 above)
1647 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1648 WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1649 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1650 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1651 }
1652 }
1653 }
1654
1655 void EM4xLogin(uint32_t Password) {
1656
1657 uint8_t fwd_bit_count;
1658 forward_ptr = forwardLink_data;
1659 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1660 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1661 SendForward(fwd_bit_count);
1662
1663 //Wait for command to complete
1664 WaitMS(20);
1665 }
1666
1667 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1668
1669 uint8_t fwd_bit_count;
1670 uint8_t *dest = BigBuf_get_addr();
1671 uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
1672 uint32_t i = 0;
1673
1674 // Clear destination buffer before sending the command
1675 BigBuf_Clear_ext(false);
1676
1677 //If password mode do login
1678 if (PwdMode == 1) EM4xLogin(Pwd);
1679
1680 forward_ptr = forwardLink_data;
1681 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1682 fwd_bit_count += Prepare_Addr( Address );
1683
1684 SendForward(fwd_bit_count);
1685
1686 // Now do the acquisition
1687 // ICEMAN, change to the one in lfsampling.c
1688 i = 0;
1689 for(;;) {
1690 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1691 AT91C_BASE_SSC->SSC_THR = 0x43;
1692 }
1693 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1694 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1695 ++i;
1696 if (i >= bufsize) break;
1697 }
1698 }
1699
1700 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1701 cmd_send(CMD_ACK,0,0,0,0,0);
1702 LED_D_OFF();
1703 }
1704
1705 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1706
1707 uint8_t fwd_bit_count;
1708
1709 //If password mode do login
1710 if (PwdMode == 1) EM4xLogin(Pwd);
1711
1712 forward_ptr = forwardLink_data;
1713 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1714 fwd_bit_count += Prepare_Addr( Address );
1715 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1716
1717 SendForward(fwd_bit_count);
1718
1719 //Wait for write to complete
1720 WaitMS(20);
1721 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1722 LED_D_OFF();
1723 }
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