]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ADD: lf indalademod output, The binary string is now printed with linebreaks every...
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" //test
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76 /* blank r/w tag data stream
77 ...0000000000000000 01111111
78 1010101010101010101010101010101010101010101010101010101010101010
79 0011010010100001
80 01111111
81 101010101010101[0]000...
82
83 [5555fe852c5555555555555555fe0000]
84 */
85 void ReadTItag(void)
86 {
87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
94
95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
178 if (shift3 & (1<<15) ) {
179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x",
206 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
207 if (crc != (shift2&0xffff)) {
208 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
209 } else {
210 DbpString("Info: CRC is good");
211 }
212 }
213 }
214
215 void WriteTIbyte(uint8_t b)
216 {
217 int i = 0;
218
219 // modulate 8 bits out to the antenna
220 for (i=0; i<8; i++)
221 {
222 if (b&(1<<i)) {
223 // stop modulating antenna
224 LOW(GPIO_SSC_DOUT);
225 SpinDelayUs(1000);
226 // modulate antenna
227 HIGH(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 } else {
230 // stop modulating antenna
231 LOW(GPIO_SSC_DOUT);
232 SpinDelayUs(300);
233 // modulate antenna
234 HIGH(GPIO_SSC_DOUT);
235 SpinDelayUs(1700);
236 }
237 }
238 }
239
240 void AcquireTiType(void)
241 {
242 int i, j, n;
243 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
244 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
245 #define TIBUFLEN 1250
246
247 // clear buffer
248 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
249
250 //clear buffer now so it does not interfere with timing later
251 BigBuf_Clear_ext(false);
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN * 32;
301
302 // unpack buffer
303 for (i = TIBUFLEN-1; i >= 0; i--) {
304 for (j = 0; j < 32; j++) {
305 if(buf[i] & (1 << j)) {
306 dest[--n] = 1;
307 } else {
308 dest[--n] = -1;
309 }
310 }
311 }
312 }
313
314 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
315 // if crc provided, it will be written with the data verbatim (even if bogus)
316 // if not provided a valid crc will be computed from the data and written.
317 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
318 {
319 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
320 if(crc == 0) {
321 crc = update_crc16(crc, (idlo)&0xff);
322 crc = update_crc16(crc, (idlo>>8)&0xff);
323 crc = update_crc16(crc, (idlo>>16)&0xff);
324 crc = update_crc16(crc, (idlo>>24)&0xff);
325 crc = update_crc16(crc, (idhi)&0xff);
326 crc = update_crc16(crc, (idhi>>8)&0xff);
327 crc = update_crc16(crc, (idhi>>16)&0xff);
328 crc = update_crc16(crc, (idhi>>24)&0xff);
329 }
330 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use 'lf ti read' to check");
383 }
384
385 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386 {
387 int i;
388 uint8_t *tab = BigBuf_get_addr();
389
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
392
393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
394 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
395 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
396
397 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
398 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
399
400 i = 0;
401 for(;;) {
402 //wait until SSC_CLK goes HIGH
403 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
404 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
405 DbpString("Stopped");
406 return;
407 }
408 WDT_HIT();
409 }
410 if (ledcontrol) LED_D_ON();
411
412 if(tab[i])
413 OPEN_COIL();
414 else
415 SHORT_COIL();
416
417 if (ledcontrol) LED_D_OFF();
418
419 //wait until SSC_CLK goes LOW
420 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
421 if(BUTTON_PRESS()) {
422 DbpString("Stopped");
423 return;
424 }
425 WDT_HIT();
426 }
427
428 i++;
429 if(i == period) {
430
431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
438 }
439
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor, int t0)
442 {
443 }
444
445 // compose fc/8 fc/10 waveform (FSK2)
446 static void fc(int c, int *n)
447 {
448 uint8_t *dest = BigBuf_get_addr();
449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
462
463 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
477 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 }
491 }
492 }
493 // compose fc/X fc/Y waveform (FSKx)
494 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
495 {
496 uint8_t *dest = BigBuf_get_addr();
497 uint8_t halfFC = fc/2;
498 uint8_t wavesPerClock = clock/fc;
499 uint8_t mod = clock % fc; //modifier
500 uint8_t modAdj = fc/mod; //how often to apply modifier
501 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
502 // loop through clock - step field clock
503 for (uint8_t idx=0; idx < wavesPerClock; idx++){
504 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
506 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
507 *n += fc;
508 }
509 if (mod>0) (*modCnt)++;
510 if ((mod>0) && modAdjOk){ //fsk2
511 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
512 memset(dest+(*n), 0, fc-halfFC);
513 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
514 *n += fc;
515 }
516 }
517 if (mod>0 && !modAdjOk){ //fsk1
518 memset(dest+(*n), 0, mod-(mod/2));
519 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
520 *n += mod;
521 }
522 }
523
524 // prepare a waveform pattern in the buffer based on the ID given then
525 // simulate a HID tag until the button is pressed
526 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
527 {
528 int n=0, i=0;
529 /*
530 HID tag bitstream format
531 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
532 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
533 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
534 A fc8 is inserted before every 4 bits
535 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
536 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
537 */
538
539 if (hi>0xFFF) {
540 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
541 return;
542 }
543 fc(0,&n);
544 // special start of frame marker containing invalid bit sequences
545 fc(8, &n); fc(8, &n); // invalid
546 fc(8, &n); fc(10, &n); // logical 0
547 fc(10, &n); fc(10, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549
550 WDT_HIT();
551 // manchester encode bits 43 to 32
552 for (i=11; i>=0; i--) {
553 if ((i%4)==3) fc(0,&n);
554 if ((hi>>i)&1) {
555 fc(10, &n); fc(8, &n); // low-high transition
556 } else {
557 fc(8, &n); fc(10, &n); // high-low transition
558 }
559 }
560
561 WDT_HIT();
562 // manchester encode bits 31 to 0
563 for (i=31; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((lo>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 if (ledcontrol) LED_A_ON();
573 SimulateTagLowFrequency(n, 0, ledcontrol);
574 if (ledcontrol) LED_A_OFF();
575 }
576
577 // prepare a waveform pattern in the buffer based on the ID given then
578 // simulate a FSK tag until the button is pressed
579 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
580 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
581 {
582 int ledcontrol=1;
583 int n=0, i=0;
584 uint8_t fcHigh = arg1 >> 8;
585 uint8_t fcLow = arg1 & 0xFF;
586 uint16_t modCnt = 0;
587 uint8_t clk = arg2 & 0xFF;
588 uint8_t invert = (arg2 >> 8) & 1;
589
590 for (i=0; i<size; i++){
591 if (BitStream[i] == invert){
592 fcAll(fcLow, &n, clk, &modCnt);
593 } else {
594 fcAll(fcHigh, &n, clk, &modCnt);
595 }
596 }
597 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
598 /*Dbprintf("DEBUG: First 32:");
599 uint8_t *dest = BigBuf_get_addr();
600 i=0;
601 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
602 i+=16;
603 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
604 */
605 if (ledcontrol)
606 LED_A_ON();
607
608 SimulateTagLowFrequency(n, 0, ledcontrol);
609
610 if (ledcontrol)
611 LED_A_OFF();
612 }
613
614 // compose ask waveform for one bit(ASK)
615 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
616 {
617 uint8_t *dest = BigBuf_get_addr();
618 uint8_t halfClk = clock/2;
619 // c = current bit 1 or 0
620 if (manchester==1){
621 memset(dest+(*n), c, halfClk);
622 memset(dest+(*n) + halfClk, c^1, halfClk);
623 } else {
624 memset(dest+(*n), c, clock);
625 }
626 *n += clock;
627 }
628
629 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
630 {
631 uint8_t *dest = BigBuf_get_addr();
632 uint8_t halfClk = clock/2;
633 if (c){
634 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
635 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
636 } else {
637 memset(dest+(*n), c ^ *phase, clock);
638 *phase ^= 1;
639 }
640
641 }
642
643 // args clock, ask/man or askraw, invert, transmission separator
644 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
645 {
646 int ledcontrol = 1;
647 int n=0, i=0;
648 uint8_t clk = (arg1 >> 8) & 0xFF;
649 uint8_t encoding = arg1 & 0xFF;
650 uint8_t separator = arg2 & 1;
651 uint8_t invert = (arg2 >> 8) & 1;
652
653 if (encoding==2){ //biphase
654 uint8_t phase=0;
655 for (i=0; i<size; i++){
656 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
657 }
658 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
659 for (i=0; i<size; i++){
660 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
661 }
662 }
663 } else { // ask/manchester || ask/raw
664 for (i=0; i<size; i++){
665 askSimBit(BitStream[i]^invert, &n, clk, encoding);
666 }
667 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
668 for (i=0; i<size; i++){
669 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
670 }
671 }
672 }
673
674 if (separator==1) Dbprintf("sorry but separator option not yet available");
675
676 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
677
678 if (ledcontrol) LED_A_ON();
679 SimulateTagLowFrequency(n, 0, ledcontrol);
680 if (ledcontrol) LED_A_OFF();
681 }
682
683 //carrier can be 2,4 or 8
684 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
685 {
686 uint8_t *dest = BigBuf_get_addr();
687 uint8_t halfWave = waveLen/2;
688 //uint8_t idx;
689 int i = 0;
690 if (phaseChg){
691 // write phase change
692 memset(dest+(*n), *curPhase^1, halfWave);
693 memset(dest+(*n) + halfWave, *curPhase, halfWave);
694 *n += waveLen;
695 *curPhase ^= 1;
696 i += waveLen;
697 }
698 //write each normal clock wave for the clock duration
699 for (; i < clk; i+=waveLen){
700 memset(dest+(*n), *curPhase, halfWave);
701 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
702 *n += waveLen;
703 }
704 }
705
706 // args clock, carrier, invert,
707 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
708 {
709 int ledcontrol = 1;
710 int n=0, i=0;
711 uint8_t clk = arg1 >> 8;
712 uint8_t carrier = arg1 & 0xFF;
713 uint8_t invert = arg2 & 0xFF;
714 uint8_t curPhase = 0;
715 for (i=0; i<size; i++){
716 if (BitStream[i] == curPhase){
717 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
718 } else {
719 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
720 }
721 }
722 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
723
724 if (ledcontrol) LED_A_ON();
725 SimulateTagLowFrequency(n, 0, ledcontrol);
726 if (ledcontrol) LED_A_OFF();
727 }
728
729 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
730 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
731 {
732 uint8_t *dest = BigBuf_get_addr();
733 size_t size = 0;
734 uint32_t hi2=0, hi=0, lo=0;
735 int idx=0;
736 // Configure to go in 125Khz listen mode
737 LFSetupFPGAForADC(95, true);
738
739 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
740
741 WDT_HIT();
742 if (ledcontrol) LED_A_ON();
743
744 DoAcquisition_default(-1,true);
745 // FSK demodulator
746 size = 50*128*2; //big enough to catch 2 sequences of largest format
747 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
748
749 if (idx>0 && lo>0 && (size==96 || size==192)){
750 // go over previously decoded manchester data and decode into usable tag ID
751 if (hi2 != 0){ //extra large HID tags 88/192 bits
752 Dbprintf("TAG ID: %x%08x%08x (%d)",
753 (unsigned int) hi2,
754 (unsigned int) hi,
755 (unsigned int) lo,
756 (unsigned int) (lo>>1) & 0xFFFF
757 );
758 }else { //standard HID tags 44/96 bits
759 uint8_t bitlen = 0;
760 uint32_t fc = 0;
761 uint32_t cardnum = 0;
762
763 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
764 uint32_t lo2=0;
765 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
766 uint8_t idx3 = 1;
767 while(lo2 > 1){ //find last bit set to 1 (format len bit)
768 lo2=lo2 >> 1;
769 idx3++;
770 }
771 bitlen = idx3+19;
772 fc =0;
773 cardnum=0;
774 if(bitlen == 26){
775 cardnum = (lo>>1)&0xFFFF;
776 fc = (lo>>17)&0xFF;
777 }
778 if(bitlen == 37){
779 cardnum = (lo>>1)&0x7FFFF;
780 fc = ((hi&0xF)<<12)|(lo>>20);
781 }
782 if(bitlen == 34){
783 cardnum = (lo>>1)&0xFFFF;
784 fc= ((hi&1)<<15)|(lo>>17);
785 }
786 if(bitlen == 35){
787 cardnum = (lo>>1)&0xFFFFF;
788 fc = ((hi&1)<<11)|(lo>>21);
789 }
790 }
791 else { //if bit 38 is not set then 37 bit format is used
792 bitlen= 37;
793 fc =0;
794 cardnum=0;
795 if(bitlen==37){
796 cardnum = (lo>>1)&0x7FFFF;
797 fc = ((hi&0xF)<<12)|(lo>>20);
798 }
799 }
800 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
801 (unsigned int) hi,
802 (unsigned int) lo,
803 (unsigned int) (lo>>1) & 0xFFFF,
804 (unsigned int) bitlen,
805 (unsigned int) fc,
806 (unsigned int) cardnum);
807 }
808 if (findone){
809 if (ledcontrol) LED_A_OFF();
810 *high = hi;
811 *low = lo;
812 return;
813 }
814 // reset
815 }
816 hi2 = hi = lo = idx = 0;
817 WDT_HIT();
818 }
819 DbpString("Stopped");
820 if (ledcontrol) LED_A_OFF();
821 }
822
823 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
824 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
825 {
826 uint8_t *dest = BigBuf_get_addr();
827 size_t size;
828 int idx=0;
829 // Configure to go in 125Khz listen mode
830 LFSetupFPGAForADC(95, true);
831
832 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
833
834 WDT_HIT();
835 if (ledcontrol) LED_A_ON();
836
837 DoAcquisition_default(-1,true);
838 // FSK demodulator
839 size = 50*128*2; //big enough to catch 2 sequences of largest format
840 idx = AWIDdemodFSK(dest, &size);
841
842 if (idx>0 && size==96){
843 // Index map
844 // 0 10 20 30 40 50 60
845 // | | | | | | |
846 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
847 // -----------------------------------------------------------------------------
848 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
849 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
850 // |---26 bit---| |-----117----||-------------142-------------|
851 // b = format bit len, o = odd parity of last 3 bits
852 // f = facility code, c = card number
853 // w = wiegand parity
854 // (26 bit format shown)
855
856 //get raw ID before removing parities
857 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
858 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
859 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
860
861 size = removeParity(dest, idx+8, 4, 1, 88);
862 // ok valid card found!
863
864 // Index map
865 // 0 10 20 30 40 50 60
866 // | | | | | | |
867 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
868 // -----------------------------------------------------------------------------
869 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
870 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
871 // |26 bit| |-117--| |-----142------|
872 // b = format bit len, o = odd parity of last 3 bits
873 // f = facility code, c = card number
874 // w = wiegand parity
875 // (26 bit format shown)
876
877 uint32_t fc = 0;
878 uint32_t cardnum = 0;
879 uint32_t code1 = 0;
880 uint32_t code2 = 0;
881 uint8_t fmtLen = bytebits_to_byte(dest,8);
882 if (fmtLen==26){
883 fc = bytebits_to_byte(dest+9, 8);
884 cardnum = bytebits_to_byte(dest+17, 16);
885 code1 = bytebits_to_byte(dest+8,fmtLen);
886 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
887 } else {
888 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
889 if (fmtLen>32){
890 code1 = bytebits_to_byte(dest+8,fmtLen-32);
891 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
892 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
893 } else{
894 code1 = bytebits_to_byte(dest+8,fmtLen);
895 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
896 }
897 }
898 if (findone){
899 if (ledcontrol) LED_A_OFF();
900 return;
901 }
902 // reset
903 }
904 idx = 0;
905 WDT_HIT();
906 }
907 DbpString("Stopped");
908 if (ledcontrol) LED_A_OFF();
909 }
910
911 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
912 {
913 uint8_t *dest = BigBuf_get_addr();
914
915 size_t size=0, idx=0;
916 int clk=0, invert=0, errCnt=0, maxErr=20;
917 uint32_t hi=0;
918 uint64_t lo=0;
919 // Configure to go in 125Khz listen mode
920 LFSetupFPGAForADC(95, true);
921
922 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
923
924 WDT_HIT();
925 if (ledcontrol) LED_A_ON();
926
927 DoAcquisition_default(-1,true);
928 size = BigBuf_max_traceLen();
929 //askdemod and manchester decode
930 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
931 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
932 WDT_HIT();
933
934 if (errCnt<0) continue;
935
936 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
937 if (errCnt){
938 if (size>64){
939 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
940 hi,
941 (uint32_t)(lo>>32),
942 (uint32_t)lo,
943 (uint32_t)(lo&0xFFFF),
944 (uint32_t)((lo>>16LL) & 0xFF),
945 (uint32_t)(lo & 0xFFFFFF));
946 } else {
947 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
948 (uint32_t)(lo>>32),
949 (uint32_t)lo,
950 (uint32_t)(lo&0xFFFF),
951 (uint32_t)((lo>>16LL) & 0xFF),
952 (uint32_t)(lo & 0xFFFFFF));
953 }
954
955 if (findone){
956 if (ledcontrol) LED_A_OFF();
957 *high=lo>>32;
958 *low=lo & 0xFFFFFFFF;
959 return;
960 }
961 }
962 WDT_HIT();
963 hi = lo = size = idx = 0;
964 clk = invert = errCnt = 0;
965 }
966 DbpString("Stopped");
967 if (ledcontrol) LED_A_OFF();
968 }
969
970 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
971 {
972 uint8_t *dest = BigBuf_get_addr();
973 int idx=0;
974 uint32_t code=0, code2=0;
975 uint8_t version=0;
976 uint8_t facilitycode=0;
977 uint16_t number=0;
978 uint8_t crc = 0;
979 uint16_t calccrc = 0;
980 // Configure to go in 125Khz listen mode
981 LFSetupFPGAForADC(95, true);
982
983 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
984 WDT_HIT();
985 if (ledcontrol) LED_A_ON();
986 DoAcquisition_default(-1,true);
987 //fskdemod and get start index
988 WDT_HIT();
989 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
990 if (idx<0) continue;
991 //valid tag found
992
993 //Index map
994 //0 10 20 30 40 50 60
995 //| | | | | | |
996 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
997 //-----------------------------------------------------------------------------
998 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
999 //
1000 //Checksum:
1001 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1002 //preamble F0 E0 01 03 B6 75
1003 // How to calc checksum,
1004 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1005 // F0 + E0 + 01 + 03 + B6 = 28A
1006 // 28A & FF = 8A
1007 // FF - 8A = 75
1008 // Checksum: 0x75
1009 //XSF(version)facility:codeone+codetwo
1010 //Handle the data
1011 if(findone){ //only print binary if we are doing one
1012 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1013 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1014 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1015 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1016 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1017 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1018 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1019 }
1020 code = bytebits_to_byte(dest+idx,32);
1021 code2 = bytebits_to_byte(dest+idx+32,32);
1022 version = bytebits_to_byte(dest+idx+27,8); //14,4
1023 facilitycode = bytebits_to_byte(dest+idx+18,8);
1024 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1025
1026 crc = bytebits_to_byte(dest+idx+54,8);
1027 for (uint8_t i=1; i<6; ++i)
1028 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1029 calccrc &= 0xff;
1030 calccrc = 0xff - calccrc;
1031
1032 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1033
1034 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1035 // if we're only looking for one tag
1036 if (findone){
1037 if (ledcontrol) LED_A_OFF();
1038 *high=code;
1039 *low=code2;
1040 return;
1041 }
1042 code=code2=0;
1043 version=facilitycode=0;
1044 number=0;
1045 idx=0;
1046
1047 WDT_HIT();
1048 }
1049 DbpString("Stopped");
1050 if (ledcontrol) LED_A_OFF();
1051 }
1052
1053 /*------------------------------
1054 * T5555/T5557/T5567/T5577 routines
1055 *------------------------------
1056 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1057 *
1058 * Relevant communication times in microsecond
1059 * To compensate antenna falling times shorten the write times
1060 * and enlarge the gap ones.
1061 * Q5 tags seems to have issues when these values changes.
1062 */
1063
1064 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1065 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1066 #define WRITE_0 16*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1067 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1068 #define READ_GAP 15*8
1069
1070 // VALUES TAKEN FROM EM4x function: SendForward
1071 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1072 // WRITE_GAP = 128; (16*8)
1073 // WRITE_1 = 256 32*8; (32*8)
1074
1075 // These timings work for 4469/4269/4305 (with the 55*8 above)
1076 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1077
1078 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1079 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1080 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1081 // T0 = TIMER_CLOCK1 / 125000 = 192
1082 // 1 Cycle = 8 microseconds(us) == 1 field clock
1083
1084 void TurnReadLFOn(int delay) {
1085 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1086 // Give it a bit of time for the resonant antenna to settle.
1087
1088 // measure antenna strength.
1089 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1090 // where to save it
1091
1092 SpinDelayUs(delay);
1093 }
1094
1095 // Write one bit to card
1096 void T55xxWriteBit(int bit) {
1097 if (!bit)
1098 TurnReadLFOn(WRITE_0);
1099 else
1100 TurnReadLFOn(WRITE_1);
1101 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1102 SpinDelayUs(WRITE_GAP);
1103 }
1104
1105 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1106 void T55xxResetRead(void) {
1107 LED_A_ON();
1108 //clear buffer now so it does not interfere with timing later
1109 BigBuf_Clear_ext(false);
1110
1111 // Set up FPGA, 125kHz
1112 LFSetupFPGAForADC(95, true);
1113
1114 // Trigger T55x7 in mode.
1115 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1116 SpinDelayUs(START_GAP);
1117
1118 // reset tag - op code 00
1119 T55xxWriteBit(0);
1120 T55xxWriteBit(0);
1121
1122 // Turn field on to read the response
1123 TurnReadLFOn(READ_GAP);
1124
1125 // Acquisition
1126 doT55x7Acquisition(BigBuf_max_traceLen());
1127
1128 // Turn the field off
1129 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1130 cmd_send(CMD_ACK,0,0,0,0,0);
1131 LED_A_OFF();
1132 }
1133
1134 // Write one card block in page 0, no lock
1135 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1136 LED_A_ON();
1137 bool PwdMode = arg & 0x1;
1138 uint8_t Page = (arg & 0x2)>>1;
1139 uint32_t i = 0;
1140
1141 // Set up FPGA, 125kHz
1142 LFSetupFPGAForADC(95, true);
1143
1144 // Trigger T55x7 in mode.
1145 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1146 SpinDelayUs(START_GAP);
1147
1148 // Opcode 10
1149 T55xxWriteBit(1);
1150 T55xxWriteBit(Page); //Page 0
1151 if (PwdMode){
1152 // Send Pwd
1153 for (i = 0x80000000; i != 0; i >>= 1)
1154 T55xxWriteBit(Pwd & i);
1155 }
1156 // Send Lock bit
1157 T55xxWriteBit(0);
1158
1159 // Send Data
1160 for (i = 0x80000000; i != 0; i >>= 1)
1161 T55xxWriteBit(Data & i);
1162
1163 // Send Block number
1164 for (i = 0x04; i != 0; i >>= 1)
1165 T55xxWriteBit(Block & i);
1166
1167 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1168 // so wait a little more)
1169 TurnReadLFOn(20 * 1000);
1170 //could attempt to do a read to confirm write took
1171 // as the tag should repeat back the new block
1172 // until it is reset, but to confirm it we would
1173 // need to know the current block 0 config mode
1174
1175 // turn field off
1176 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1177 LED_A_OFF();
1178 }
1179
1180 // Write one card block in page 0, no lock
1181 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1182 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1183 cmd_send(CMD_ACK,0,0,0,0,0);
1184 }
1185
1186 // Read one card block in page [page]
1187 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1188 LED_A_ON();
1189 bool PwdMode = arg0 & 0x1;
1190 uint8_t Page = (arg0 & 0x2) >> 1;
1191 uint32_t i = 0;
1192 bool RegReadMode = (Block == 0xFF);
1193
1194 //clear buffer now so it does not interfere with timing later
1195 BigBuf_Clear_ext(false);
1196
1197 //make sure block is at max 7
1198 Block &= 0x7;
1199
1200 // Set up FPGA, 125kHz to power up the tag
1201 LFSetupFPGAForADC(95, true);
1202
1203 // Trigger T55x7 Direct Access Mode with start gap
1204 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1205 SpinDelayUs(START_GAP);
1206
1207 // Opcode 1[page]
1208 T55xxWriteBit(1);
1209 T55xxWriteBit(Page); //Page 0
1210
1211 if (PwdMode){
1212 // Send Pwd
1213 for (i = 0x80000000; i != 0; i >>= 1)
1214 T55xxWriteBit(Pwd & i);
1215 }
1216 // Send a zero bit separation
1217 T55xxWriteBit(0);
1218
1219 // Send Block number (if direct access mode)
1220 if (!RegReadMode)
1221 for (i = 0x04; i != 0; i >>= 1)
1222 T55xxWriteBit(Block & i);
1223
1224 // Turn field on to read the response
1225 TurnReadLFOn(READ_GAP);
1226
1227 // Acquisition
1228 doT55x7Acquisition(12000);
1229
1230 // Turn the field off
1231 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1232 cmd_send(CMD_ACK,0,0,0,0,0);
1233 LED_A_OFF();
1234 }
1235
1236 void T55xxWakeUp(uint32_t Pwd){
1237 LED_B_ON();
1238 uint32_t i = 0;
1239
1240 // Set up FPGA, 125kHz
1241 LFSetupFPGAForADC(95, true);
1242
1243 // Trigger T55x7 Direct Access Mode
1244 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1245 SpinDelayUs(START_GAP);
1246
1247 // Opcode 10
1248 T55xxWriteBit(1);
1249 T55xxWriteBit(0); //Page 0
1250
1251 // Send Pwd
1252 for (i = 0x80000000; i != 0; i >>= 1)
1253 T55xxWriteBit(Pwd & i);
1254
1255 // Turn and leave field on to let the begin repeating transmission
1256 TurnReadLFOn(20*1000);
1257 }
1258
1259 /*-------------- Cloning routines -----------*/
1260
1261 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1262 // write last block first and config block last (if included)
1263 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1264 T55xxWriteBlockExt(blockdata[i-1],i-1,0,0);
1265 }
1266
1267 // Copy HID id to card and setup block 0 config
1268 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1269 uint32_t data[] = {0,0,0,0,0,0,0};
1270 //int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1271 uint8_t last_block = 0;
1272
1273 if (longFMT){
1274 // Ensure no more than 84 bits supplied
1275 if (hi2>0xFFFFF) {
1276 DbpString("Tags can only have 84 bits.");
1277 return;
1278 }
1279 // Build the 6 data blocks for supplied 84bit ID
1280 last_block = 6;
1281 // load preamble (1D) & long format identifier (9E manchester encoded)
1282 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1283 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1284 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1285 data[3] = manchesterEncode2Bytes(hi >> 16);
1286 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1287 data[5] = manchesterEncode2Bytes(lo >> 16);
1288 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1289 } else {
1290 // Ensure no more than 44 bits supplied
1291 if (hi>0xFFF) {
1292 DbpString("Tags can only have 44 bits.");
1293 return;
1294 }
1295 // Build the 3 data blocks for supplied 44bit ID
1296 last_block = 3;
1297 // load preamble
1298 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1299 data[2] = manchesterEncode2Bytes(lo >> 16);
1300 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1301 }
1302 // load chip config block
1303 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1304
1305 //TODO add selection of chip for Q5 or T55x7
1306 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1307
1308 LED_D_ON();
1309 // Program the data blocks for supplied ID
1310 // and the block 0 for HID format
1311 WriteT55xx(data, 0, last_block+1);
1312
1313 LED_D_OFF();
1314
1315 DbpString("DONE!");
1316 }
1317
1318 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1319 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1320 //TODO add selection of chip for Q5 or T55x7
1321 // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1322
1323 LED_D_ON();
1324 // Program the data blocks for supplied ID
1325 // and the block 0 config
1326 WriteT55xx(data, 0, 3);
1327
1328 LED_D_OFF();
1329
1330 DbpString("DONE!");
1331 }
1332
1333 // Clone Indala 64-bit tag by UID to T55x7
1334 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1335 //Program the 2 data blocks for supplied 64bit UID
1336 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1337 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1338 //TODO add selection of chip for Q5 or T55x7
1339 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1340
1341 WriteT55xx(data, 0, 3);
1342 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1343 // T5567WriteBlock(0x603E1042,0);
1344 DbpString("DONE!");
1345 }
1346 // Clone Indala 224-bit tag by UID to T55x7
1347 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1348 //Program the 7 data blocks for supplied 224bit UID
1349 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1350 // and the block 0 for Indala224 format
1351 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1352 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1353 //TODO add selection of chip for Q5 or T55x7
1354 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1355 WriteT55xx(data, 0, 8);
1356 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1357 // T5567WriteBlock(0x603E10E2,0);
1358 DbpString("DONE!");
1359 }
1360
1361 // Define 9bit header for EM410x tags
1362 #define EM410X_HEADER 0x1FF
1363 #define EM410X_ID_LENGTH 40
1364
1365 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1366 int i, id_bit;
1367 uint64_t id = EM410X_HEADER;
1368 uint64_t rev_id = 0; // reversed ID
1369 int c_parity[4]; // column parity
1370 int r_parity = 0; // row parity
1371 uint32_t clock = 0;
1372
1373 // Reverse ID bits given as parameter (for simpler operations)
1374 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1375 if (i < 32) {
1376 rev_id = (rev_id << 1) | (id_lo & 1);
1377 id_lo >>= 1;
1378 } else {
1379 rev_id = (rev_id << 1) | (id_hi & 1);
1380 id_hi >>= 1;
1381 }
1382 }
1383
1384 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1385 id_bit = rev_id & 1;
1386
1387 if (i % 4 == 0) {
1388 // Don't write row parity bit at start of parsing
1389 if (i)
1390 id = (id << 1) | r_parity;
1391 // Start counting parity for new row
1392 r_parity = id_bit;
1393 } else {
1394 // Count row parity
1395 r_parity ^= id_bit;
1396 }
1397
1398 // First elements in column?
1399 if (i < 4)
1400 // Fill out first elements
1401 c_parity[i] = id_bit;
1402 else
1403 // Count column parity
1404 c_parity[i % 4] ^= id_bit;
1405
1406 // Insert ID bit
1407 id = (id << 1) | id_bit;
1408 rev_id >>= 1;
1409 }
1410
1411 // Insert parity bit of last row
1412 id = (id << 1) | r_parity;
1413
1414 // Fill out column parity at the end of tag
1415 for (i = 0; i < 4; ++i)
1416 id = (id << 1) | c_parity[i];
1417
1418 // Add stop bit
1419 id <<= 1;
1420
1421 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1422 LED_D_ON();
1423
1424 // Write EM410x ID
1425 uint32_t data[] = {0, id>>32, id & 0xFFFFFFFF};
1426
1427 clock = (card & 0xFF00) >> 8;
1428 clock = (clock == 0) ? 64 : clock;
1429 Dbprintf("Clock rate: %d", clock);
1430 if (card & 0xFF) { //t55x7
1431 clock = GetT55xxClockBit(clock);
1432 if (clock == 0) {
1433 Dbprintf("Invalid clock rate: %d", clock);
1434 return;
1435 }
1436 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1437 } else { //t5555 (Q5)
1438 clock = (clock-2)>>1; //n = (RF-2)/2
1439 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1440 }
1441
1442 WriteT55xx(data, 0, 3);
1443
1444 LED_D_OFF();
1445 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1446 (uint32_t)(id >> 32), (uint32_t)id);
1447 }
1448
1449 //-----------------------------------
1450 // EM4469 / EM4305 routines
1451 //-----------------------------------
1452 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1453 #define FWD_CMD_WRITE 0xA
1454 #define FWD_CMD_READ 0x9
1455 #define FWD_CMD_DISABLE 0x5
1456
1457 uint8_t forwardLink_data[64]; //array of forwarded bits
1458 uint8_t * forward_ptr; //ptr for forward message preparation
1459 uint8_t fwd_bit_sz; //forwardlink bit counter
1460 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1461
1462 //====================================================================
1463 // prepares command bits
1464 // see EM4469 spec
1465 //====================================================================
1466 //--------------------------------------------------------------------
1467 // VALUES TAKEN FROM EM4x function: SendForward
1468 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1469 // WRITE_GAP = 128; (16*8)
1470 // WRITE_1 = 256 32*8; (32*8)
1471
1472 // These timings work for 4469/4269/4305 (with the 55*8 above)
1473 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1474
1475 uint8_t Prepare_Cmd( uint8_t cmd ) {
1476
1477 *forward_ptr++ = 0; //start bit
1478 *forward_ptr++ = 0; //second pause for 4050 code
1479
1480 *forward_ptr++ = cmd;
1481 cmd >>= 1;
1482 *forward_ptr++ = cmd;
1483 cmd >>= 1;
1484 *forward_ptr++ = cmd;
1485 cmd >>= 1;
1486 *forward_ptr++ = cmd;
1487
1488 return 6; //return number of emited bits
1489 }
1490
1491 //====================================================================
1492 // prepares address bits
1493 // see EM4469 spec
1494 //====================================================================
1495 uint8_t Prepare_Addr( uint8_t addr ) {
1496
1497 register uint8_t line_parity;
1498
1499 uint8_t i;
1500 line_parity = 0;
1501 for(i=0;i<6;i++) {
1502 *forward_ptr++ = addr;
1503 line_parity ^= addr;
1504 addr >>= 1;
1505 }
1506
1507 *forward_ptr++ = (line_parity & 1);
1508
1509 return 7; //return number of emited bits
1510 }
1511
1512 //====================================================================
1513 // prepares data bits intreleaved with parity bits
1514 // see EM4469 spec
1515 //====================================================================
1516 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1517
1518 register uint8_t line_parity;
1519 register uint8_t column_parity;
1520 register uint8_t i, j;
1521 register uint16_t data;
1522
1523 data = data_low;
1524 column_parity = 0;
1525
1526 for(i=0; i<4; i++) {
1527 line_parity = 0;
1528 for(j=0; j<8; j++) {
1529 line_parity ^= data;
1530 column_parity ^= (data & 1) << j;
1531 *forward_ptr++ = data;
1532 data >>= 1;
1533 }
1534 *forward_ptr++ = line_parity;
1535 if(i == 1)
1536 data = data_hi;
1537 }
1538
1539 for(j=0; j<8; j++) {
1540 *forward_ptr++ = column_parity;
1541 column_parity >>= 1;
1542 }
1543 *forward_ptr = 0;
1544
1545 return 45; //return number of emited bits
1546 }
1547
1548 //====================================================================
1549 // Forward Link send function
1550 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1551 // fwd_bit_count set with number of bits to be sent
1552 //====================================================================
1553 void SendForward(uint8_t fwd_bit_count) {
1554
1555 fwd_write_ptr = forwardLink_data;
1556 fwd_bit_sz = fwd_bit_count;
1557
1558 LED_D_ON();
1559
1560 // Set up FPGA, 125kHz
1561 LFSetupFPGAForADC(95, true);
1562
1563 // force 1st mod pulse (start gap must be longer for 4305)
1564 fwd_bit_sz--; //prepare next bit modulation
1565 fwd_write_ptr++;
1566 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1567 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1568 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1569 SpinDelayUs(16*8); //16 cycles on (8us each)
1570
1571 // now start writting
1572 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1573 if(((*fwd_write_ptr++) & 1) == 1)
1574 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1575 else {
1576 //These timings work for 4469/4269/4305 (with the 55*8 above)
1577 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1578 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1579 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1580 SpinDelayUs(9*8); //16 cycles on (8us each)
1581 }
1582 }
1583 }
1584
1585 void EM4xLogin(uint32_t Password) {
1586
1587 uint8_t fwd_bit_count;
1588
1589 forward_ptr = forwardLink_data;
1590 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1591 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1592
1593 SendForward(fwd_bit_count);
1594
1595 //Wait for command to complete
1596 SpinDelay(20);
1597 }
1598
1599 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1600
1601 uint8_t fwd_bit_count;
1602 uint8_t *dest = BigBuf_get_addr();
1603 uint16_t bufsize = BigBuf_max_traceLen();
1604 uint32_t i = 0;
1605
1606 //clear buffer now so it does not interfere with timing later
1607 BigBuf_Clear_ext(false);
1608
1609 //If password mode do login
1610 if (PwdMode == 1) EM4xLogin(Pwd);
1611
1612 forward_ptr = forwardLink_data;
1613 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1614 fwd_bit_count += Prepare_Addr( Address );
1615
1616 // Connect the A/D to the peak-detected low-frequency path.
1617 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1618 // Now set up the SSC to get the ADC samples that are now streaming at us.
1619 FpgaSetupSsc();
1620
1621 SendForward(fwd_bit_count);
1622
1623 // Now do the acquisition
1624 i = 0;
1625 for(;;) {
1626 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1627 AT91C_BASE_SSC->SSC_THR = 0x43;
1628 }
1629 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1630 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1631 ++i;
1632 if (i >= bufsize) break;
1633 }
1634 }
1635
1636 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1637 cmd_send(CMD_ACK,0,0,0,0,0);
1638 LED_D_OFF();
1639 }
1640
1641 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1642
1643 uint8_t fwd_bit_count;
1644
1645 //If password mode do login
1646 if (PwdMode == 1) EM4xLogin(Pwd);
1647
1648 forward_ptr = forwardLink_data;
1649 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1650 fwd_bit_count += Prepare_Addr( Address );
1651 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1652
1653 SendForward(fwd_bit_count);
1654
1655 //Wait for write to complete
1656 SpinDelay(20);
1657 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1658 LED_D_OFF();
1659 }
1660
1661 void CopyViKingtoT55x7(uint32_t block1, uint32_t block2) {
1662
1663 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1664 // Program the data blocks for supplied ID and the block 0 config
1665 WriteT55xx(data, 0, 3);
1666 LED_D_OFF();
1667 }
1668
Proxmark3 GIT tracking
Impressum, Datenschutz