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CHG: "hf legic write" - now writes on the limits better.
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 // 2016 Iceman
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // LEGIC RF simulation code
10 //-----------------------------------------------------------------------------
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 uint8_t bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 // testing calculating in (us) microseconds.
73 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
74 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
75 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
76 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
77 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
78
79 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
80
81 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
82 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
83
84 #define OFFSET_LOG 1024
85
86 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
87
88 #ifndef SHORT_COIL
89 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
90 #endif
91 #ifndef OPEN_COIL
92 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
93 #endif
94 #ifndef LINE_IN
95 # define LINE_IN AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
96 #endif
97 // Pause pulse, off in 20us / 30ticks,
98 // ONE / ZERO bit pulse,
99 // one == 80us / 120ticks
100 // zero == 40us / 60ticks
101 #ifndef COIL_PULSE
102 # define COIL_PULSE(x) \
103 do { \
104 SHORT_COIL; \
105 WaitTicks( (RWD_TIME_PAUSE) ); \
106 OPEN_COIL; \
107 WaitTicks((x)); \
108 } while (0);
109 #endif
110
111 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
112 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
113 #define LEGIC_CARD_MEMSIZE 1024
114 static uint8_t* cardmem;
115
116 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
117 // Overflow, won't happen
118 if (f->bits >= 31) return;
119
120 f->data |= (bit << f->bits);
121 f->bits++;
122 }
123
124 static void frame_clean(struct legic_frame * const f) {
125 f->data = 0;
126 f->bits = 0;
127 }
128
129 // Prng works when waiting in 99.1us cycles.
130 // and while sending/receiving in bit frames (100, 60)
131 /*static void CalibratePrng( uint32_t time){
132 // Calculate Cycles based on timer 100us
133 uint32_t i = (time - sendFrameStop) / 100 ;
134
135 // substract cycles of finished frames
136 int k = i - legic_prng_count()+1;
137
138 // substract current frame length, rewind to beginning
139 if ( k > 0 )
140 legic_prng_forward(k);
141 }
142 */
143
144 /* Generate Keystream */
145 uint32_t get_key_stream(int skip, int count) {
146
147 int i;
148
149 // Use int to enlarge timer tc to 32bit
150 legic_prng_bc += prng_timer->TC_CV;
151
152 // reset the prng timer.
153
154 /* If skip == -1, forward prng time based */
155 if(skip == -1) {
156 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
157 i -= legic_prng_count(); /* substract cycles of finished frames */
158 i -= count; /* substract current frame length, rewind to beginning */
159 legic_prng_forward(i);
160 } else {
161 legic_prng_forward(skip);
162 }
163
164 i = (count == 6) ? -1 : legic_read_count;
165
166 /* Generate KeyStream */
167 return legic_prng_get_bits(count);
168 }
169
170 /* Send a frame in tag mode, the FPGA must have been set up by
171 * LegicRfSimulate
172 */
173 void frame_send_tag(uint16_t response, uint8_t bits) {
174
175 uint16_t mask = 1;
176
177 /* Bitbang the response */
178 SHORT_COIL;
179 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
180 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
181
182 /* TAG_FRAME_WAIT -> shift by 2 */
183 legic_prng_forward(2);
184 response ^= legic_prng_get_bits(bits);
185
186 /* Wait for the frame start */
187 WaitTicks( TAG_FRAME_WAIT );
188
189 for (; mask < BITMASK(bits); mask <<= 1) {
190 if (response & mask)
191 OPEN_COIL
192 else
193 SHORT_COIL
194 WaitTicks(TAG_BIT_PERIOD);
195 }
196 SHORT_COIL;
197 }
198
199 /* Send a frame in reader mode, the FPGA must have been set up by
200 * LegicRfReader
201 */
202 void frame_sendAsReader(uint32_t data, uint8_t bits){
203
204 uint32_t starttime = GET_TICKS, send = 0, mask = 1;
205
206 // xor lsfr onto data.
207 send = data ^ legic_prng_get_bits(bits);
208
209 for (; mask < BITMASK(bits); mask <<= 1) {
210 if (send & mask)
211 COIL_PULSE(RWD_TIME_1)
212 else
213 COIL_PULSE(RWD_TIME_0)
214 }
215
216 // Final pause to mark the end of the frame
217 COIL_PULSE(0);
218
219 // log
220 uint8_t cmdbytes[] = {bits, BYTEx(data,0), BYTEx(data,1), BYTEx(data,2), BYTEx(send,0), BYTEx(send,1), BYTEx(send,2)};
221 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
222 }
223
224 /* Receive a frame from the card in reader emulation mode, the FPGA and
225 * timer must have been set up by LegicRfReader and frame_sendAsReader.
226 *
227 * The LEGIC RF protocol from card to reader does not include explicit
228 * frame start/stop information or length information. The reader must
229 * know beforehand how many bits it wants to receive. (Notably: a card
230 * sending a stream of 0-bits is indistinguishable from no card present.)
231 *
232 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
233 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
234 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
235 * for edges. Count the edges in each bit interval. If they are approximately
236 * 0 this was a 0-bit, if they are approximately equal to the number of edges
237 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
238 * timer that's still running from frame_sendAsReader in order to get a synchronization
239 * with the frame that we just sent.
240 *
241 * FIXME: Because we're relying on the hysteresis to just do the right thing
242 * the range is severely reduced (and you'll probably also need a good antenna).
243 * So this should be fixed some time in the future for a proper receiver.
244 */
245 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
246
247 if ( bits > 32 ) return;
248
249 uint8_t i = bits, edges = 0;
250 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
251 uint32_t old_level = 0;
252 volatile uint32_t level = 0;
253
254 frame_clean(f);
255
256 // calibrate the prng.
257 legic_prng_forward(2);
258 data = legic_prng_get_bits(bits);
259
260 //FIXED time between sending frame and now listening frame. 330us
261 uint32_t starttime = GET_TICKS;
262 // its about 9+9 ticks delay from end-send to here.
263 WaitTicks( 477 );
264
265 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
266
267 while ( i-- ){
268 edges = 0;
269 while ( GET_TICKS < next_bit_at) {
270
271 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
272
273 if (level != old_level)
274 ++edges;
275
276 old_level = level;
277 }
278
279 next_bit_at += TAG_BIT_PERIOD;
280
281 // We expect 42 edges (ONE)
282 if ( edges > 20 )
283 data ^= the_bit;
284
285 the_bit <<= 1;
286 }
287
288 // output
289 f->data = data;
290 f->bits = bits;
291
292 // log
293 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
294 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
295 }
296
297 // Setup pm3 as a Legic Reader
298 static uint32_t setup_phase_reader(uint8_t iv) {
299
300 // Switch on carrier and let the tag charge for 1ms
301 HIGH(GPIO_SSC_DOUT);
302 WaitUS(5000);
303
304 ResetTicks();
305
306 // no keystream yet
307 legic_prng_init(0);
308
309 // send IV handshake
310 frame_sendAsReader(iv, 7);
311
312 // Now both tag and reader has same IV. Prng can start.
313 legic_prng_init(iv);
314
315 frame_receiveAsReader(&current_frame, 6);
316
317 // 292us (438t) - fixed delay before sending ack.
318 // minus log and stuff 100tick?
319 WaitTicks(338);
320 legic_prng_forward(3);
321
322 // Send obsfuscated acknowledgment frame.
323 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
324 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
325 switch ( current_frame.data ) {
326 case 0x0D: frame_sendAsReader(0x19, 6); break;
327 case 0x1D:
328 case 0x3D: frame_sendAsReader(0x39, 6); break;
329 default: break;
330 }
331
332 legic_prng_forward(2);
333 return current_frame.data;
334 }
335
336 static void LegicCommonInit(void) {
337
338 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
339 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
340 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
341
342 /* Bitbang the transmitter */
343 SHORT_COIL;
344 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
345 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
346 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
347
348 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
349 cardmem = BigBuf_get_EM_addr();
350 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
351
352 clear_trace();
353 set_tracing(TRUE);
354 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
355
356 StartTicks();
357 }
358
359 // Switch off carrier, make sure tag is reset
360 static void switch_off_tag_rwd(void) {
361 SHORT_COIL;
362 WaitUS(20);
363 WDT_HIT();
364 }
365
366 // calculate crc4 for a legic READ command
367 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
368 crc_clear(&legic_crc);
369 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
370 crc_update(&legic_crc, temp, cmd_sz + 8 );
371 return crc_finish(&legic_crc);
372 }
373
374 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
375
376 uint8_t byte, crc, calcCrc = 0;
377 uint32_t cmd = (index << 1) | LEGIC_READ;
378
379 // 90ticks = 60us (should be 100us but crc calc takes time.)
380 //WaitTicks(330); // 330ticks prng(4) - works
381 WaitTicks(240); // 240ticks prng(3) - works
382
383 frame_sendAsReader(cmd, cmd_sz);
384 frame_receiveAsReader(&current_frame, 12);
385
386 // CRC check.
387 byte = BYTEx(current_frame.data, 0);
388 crc = BYTEx(current_frame.data, 1);
389 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
390
391 if( calcCrc != crc ) {
392 Dbprintf("!!! crc mismatch: %x != %x !!!", calcCrc, crc);
393 return -1;
394 }
395
396 legic_prng_forward(3);
397 return byte;
398 }
399
400 /*
401 * - assemble a write_cmd_frame with crc and send it
402 * - wait until the tag sends back an ACK ('1' bit unencrypted)
403 * - forward the prng based on the timing
404 */
405 bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
406
407 bool isOK = false;
408 int8_t i = 40;
409 uint8_t edges = 0;
410 uint8_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd;
411 uint32_t steps = 0, next_bit_at, start, crc, old_level = 0;
412
413 crc = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
414
415 // send write command
416 uint32_t cmd = LEGIC_WRITE;
417 cmd |= index << 1; // index
418 cmd |= byte << (addr_sz+1); // Data
419 cmd |= (crc & 0xF ) << (addr_sz+1+8); // CRC
420
421 WaitTicks(240);
422
423 frame_sendAsReader(cmd, cmd_sz);
424
425 LINE_IN;
426
427 start = GET_TICKS;
428
429 // ACK, - one single "1" bit after 3.6ms
430 // 3.6ms = 3600us * 1.5 = 5400ticks.
431 WaitTicks(5400);
432
433 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
434
435 while ( i-- ) {
436 WDT_HIT();
437 edges = 0;
438 while ( GET_TICKS < next_bit_at) {
439
440 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
441
442 if (level != old_level)
443 ++edges;
444
445 old_level = level;
446 }
447
448 next_bit_at += TAG_BIT_PERIOD;
449
450 // We expect 42 edges (ONE)
451 if(edges > 20 ) {
452 steps = ( (GET_TICKS - start) / TAG_BIT_PERIOD);
453 legic_prng_forward(steps);
454 isOK = true;
455 goto OUT;
456 }
457 }
458
459 OUT: ;
460 legic_prng_forward(1);
461
462 uint8_t cmdbytes[] = {1, isOK, BYTEx(steps, 0), BYTEx(steps, 1) };
463 LogTrace(cmdbytes, sizeof(cmdbytes), start, GET_TICKS, NULL, FALSE);
464 return isOK;
465 }
466
467 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
468
469 uint16_t i = 0;
470 uint8_t isOK = 1;
471 legic_card_select_t card;
472
473 LegicCommonInit();
474
475 if ( legic_select_card_iv(&card, iv) ) {
476 isOK = 0;
477 goto OUT;
478 }
479
480 if (len + offset > card.cardsize)
481 len = card.cardsize - offset;
482
483 LED_B_ON();
484 while (i < len) {
485 int r = legic_read_byte(offset + i, card.cmdsize);
486
487 if (r == -1 || BUTTON_PRESS()) {
488 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
489 isOK = 0;
490 goto OUT;
491 }
492 cardmem[i++] = r;
493 WDT_HIT();
494 }
495
496 OUT:
497 WDT_HIT();
498 switch_off_tag_rwd();
499 LEDsoff();
500 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
501 return 0;
502 }
503
504 void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
505
506 #define LOWERLIMIT 4
507 uint8_t isOK = 1, msg = 0;
508 legic_card_select_t card;
509
510 // uid NOT is writeable.
511 if ( offset <= LOWERLIMIT ) {
512 isOK = 0;
513 goto OUT;
514 }
515
516 LegicCommonInit();
517
518 if ( legic_select_card_iv(&card, iv) ) {
519 isOK = 0;
520 msg = 1;
521 goto OUT;
522 }
523
524 if ( len + offset > card.cardsize)
525 len = card.cardsize - offset;
526
527 LED_B_ON();
528 while( len > 0 ) {
529 --len;
530 if ( !legic_write_byte( len + offset, data[len], card.addrsize) ) {
531 Dbprintf("operation failed | %02X | %02X | %02X", len + offset, len, data[len] );
532 isOK = 0;
533 goto OUT;
534 }
535 WDT_HIT();
536 }
537 OUT:
538 cmd_send(CMD_ACK, isOK, msg,0,0,0);
539 switch_off_tag_rwd();
540 LEDsoff();
541 }
542
543 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
544
545 if ( p_card == NULL ) return 1;
546
547 p_card->tagtype = setup_phase_reader(iv);
548
549 switch(p_card->tagtype) {
550 case 0x0d:
551 p_card->cmdsize = 6;
552 p_card->addrsize = 5;
553 p_card->cardsize = 22;
554 break;
555 case 0x1d:
556 p_card->cmdsize = 9;
557 p_card->addrsize = 8;
558 p_card->cardsize = 256;
559 break;
560 case 0x3d:
561 p_card->cmdsize = 11;
562 p_card->addrsize = 10;
563 p_card->cardsize = 1024;
564 break;
565 default:
566 p_card->cmdsize = 0;
567 p_card->addrsize = 0;
568 p_card->cardsize = 0;
569 return 2;
570 }
571 return 0;
572 }
573 int legic_select_card(legic_card_select_t *p_card){
574 return legic_select_card_iv(p_card, 0x01);
575 }
576
577 //-----------------------------------------------------------------------------
578 // Work with emulator memory
579 //
580 // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
581 // involved in dealing with emulator memory. But if it is called later, it might
582 // destroy the Emulator Memory.
583 //-----------------------------------------------------------------------------
584 // arg0 = offset
585 // arg1 = num of bytes
586 void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
587 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
588 legic_emlset_mem(data, arg0, arg1);
589 }
590 // arg0 = offset
591 // arg1 = num of bytes
592 void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
593 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
594 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
595 legic_emlget_mem(buf, arg0, arg1);
596 LED_B_ON();
597 cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
598 LED_B_OFF();
599 }
600 void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
601 cardmem = BigBuf_get_EM_addr();
602 memcpy(cardmem + offset, data, numofbytes);
603 }
604 void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
605 cardmem = BigBuf_get_EM_addr();
606 memcpy(data, cardmem + offset, numofbytes);
607 }
608
609 void LegicRfInfo(void){
610
611 int r;
612
613 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
614 legic_card_select_t *card = (legic_card_select_t*) buf;
615
616 LegicCommonInit();
617
618 if ( legic_select_card(card) ) {
619 cmd_send(CMD_ACK,0,0,0,0,0);
620 goto OUT;
621 }
622
623 // read UID bytes
624 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
625 r = legic_read_byte(i, card->cmdsize);
626 if ( r == -1 ) {
627 cmd_send(CMD_ACK,0,0,0,0,0);
628 goto OUT;
629 }
630 card->uid[i] = r & 0xFF;
631 }
632
633 // MCC byte.
634 r = legic_read_byte(4, card->cmdsize);
635 uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
636 if ( r != calc_mcc) {
637 cmd_send(CMD_ACK,0,0,0,0,0);
638 goto OUT;
639 }
640
641 // OK
642 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
643
644 OUT:
645 switch_off_tag_rwd();
646 LEDsoff();
647 }
648
649 /* Handle (whether to respond) a frame in tag mode
650 * Only called when simulating a tag.
651 */
652 static void frame_handle_tag(struct legic_frame const * const f)
653 {
654 // log
655 //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
656 //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
657
658 cardmem = BigBuf_get_EM_addr();
659
660 /* First Part of Handshake (IV) */
661 if(f->bits == 7) {
662
663 LED_C_ON();
664
665 // Reset prng timer
666 ResetTimer(prng_timer);
667
668 // IV from reader.
669 legic_prng_init(f->data);
670
671 // We should have three tagtypes with three different answers.
672 frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */
673
674 legic_state = STATE_IV;
675 legic_read_count = 0;
676 legic_prng_bc = 0;
677 legic_prng_iv = f->data;
678
679
680 ResetTimer(timer);
681 WaitUS(280);
682 return;
683 }
684
685 /* 0x19==??? */
686 if(legic_state == STATE_IV) {
687 uint32_t local_key = get_key_stream(3, 6);
688 int xored = 0x39 ^ local_key;
689 if((f->bits == 6) && (f->data == xored)) {
690 legic_state = STATE_CON;
691
692 ResetTimer(timer);
693 WaitUS(200);
694 return;
695
696 } else {
697 legic_state = STATE_DISCON;
698 LED_C_OFF();
699 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
700 return;
701 }
702 }
703
704 /* Read */
705 if(f->bits == 11) {
706 if(legic_state == STATE_CON) {
707 uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11);
708 uint16_t addr = f->data ^ key;
709 addr >>= 1;
710 uint8_t data = cardmem[addr];
711 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
712
713 legic_read_count++;
714 legic_prng_forward(legic_reqresp_drift);
715
716 frame_send_tag(hash | data, 12);
717 ResetTimer(timer);
718 legic_prng_forward(2);
719 WaitTicks(330);
720 return;
721 }
722 }
723
724 /* Write */
725 if (f->bits == 23 || f->bits == 21 ) {
726 uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23);
727 uint16_t addr = f->data ^ key;
728 addr >>= 1;
729 addr &= 0x3ff;
730 uint32_t data = f->data ^ key;
731 data >>= 11;
732 data &= 0xff;
733
734 cardmem[addr] = data;
735 /* write command */
736 legic_state = STATE_DISCON;
737 LED_C_OFF();
738 Dbprintf("write - addr: %x, data: %x", addr, data);
739 // should send a ACK after 3.6ms
740 return;
741 }
742
743 if(legic_state != STATE_DISCON) {
744 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
745 Dbprintf("IV: %03.3x", legic_prng_iv);
746 }
747
748 legic_state = STATE_DISCON;
749 legic_read_count = 0;
750 SpinDelay(10);
751 LED_C_OFF();
752 return;
753 }
754
755 /* Read bit by bit untill full frame is received
756 * Call to process frame end answer
757 */
758 static void emit(int bit) {
759
760 switch (bit) {
761 case 1:
762 frame_append_bit(&current_frame, 1);
763 break;
764 case 0:
765 frame_append_bit(&current_frame, 0);
766 break;
767 default:
768 if(current_frame.bits <= 4) {
769 frame_clean(&current_frame);
770 } else {
771 frame_handle_tag(&current_frame);
772 frame_clean(&current_frame);
773 }
774 WDT_HIT();
775 break;
776 }
777 }
778
779 void LegicRfSimulate(int phase, int frame, int reqresp)
780 {
781 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
782 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
783 * envelope waveform on DIN and should send our response on DOUT.
784 *
785 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
786 * measure the time between two rising edges on DIN, and no encoding on the
787 * subcarrier from card to reader, so we'll just shift out our verbatim data
788 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
789 * seems to be 330us.
790 */
791
792 int old_level = 0, active = 0;
793 legic_state = STATE_DISCON;
794
795 legic_phase_drift = phase;
796 legic_frame_drift = frame;
797 legic_reqresp_drift = reqresp;
798
799 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
800 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
801 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
802
803 /* Bitbang the receiver */
804 LINE_IN;
805
806 // need a way to determine which tagtype we are simulating
807
808 // hook up emulator memory
809 cardmem = BigBuf_get_EM_addr();
810
811 clear_trace();
812 set_tracing(TRUE);
813
814 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
815
816 StartTicks();
817
818 LED_B_ON();
819 DbpString("Starting Legic emulator, press button to end");
820
821 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
822 volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
823
824 uint32_t time = GET_TICKS;
825
826 if (level != old_level) {
827
828 if (level) {
829
830 ResetTicks();
831
832 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
833 /* 1 bit */
834 emit(1);
835 active = 1;
836 LED_A_ON();
837 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
838 /* 0 bit */
839 emit(0);
840 active = 1;
841 LED_A_ON();
842 } else if (active) {
843 /* invalid */
844 emit(-1);
845 active = 0;
846 LED_A_OFF();
847 }
848 }
849 }
850
851 /* Frame end */
852 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
853 emit(-1);
854 active = 0;
855 LED_A_OFF();
856 }
857
858 /*
859 * Disable the counter, Then wait for the clock to acknowledge the
860 * shutdown in its status register. Reading the SR has the
861 * side-effect of clearing any pending state in there.
862 */
863 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
864 StopTicks();
865
866 old_level = level;
867 WDT_HIT();
868 }
869
870 WDT_HIT();
871 switch_off_tag_rwd();
872 LEDsoff();
873 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
874 }
875
876 //-----------------------------------------------------------------------------
877 // Code up a string of octets at layer 2 (including CRC, we don't generate
878 // that here) so that they can be transmitted to the reader. Doesn't transmit
879 // them yet, just leaves them ready to send in ToSend[].
880 //-----------------------------------------------------------------------------
881 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
882 // {
883 // int i;
884
885 // ToSendReset();
886
887 // // Transmit a burst of ones, as the initial thing that lets the
888 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
889 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
890 // // so I will too.
891 // for(i = 0; i < 20; i++) {
892 // ToSendStuffBit(1);
893 // ToSendStuffBit(1);
894 // ToSendStuffBit(1);
895 // ToSendStuffBit(1);
896 // }
897
898 // // Send SOF.
899 // for(i = 0; i < 10; i++) {
900 // ToSendStuffBit(0);
901 // ToSendStuffBit(0);
902 // ToSendStuffBit(0);
903 // ToSendStuffBit(0);
904 // }
905 // for(i = 0; i < 2; i++) {
906 // ToSendStuffBit(1);
907 // ToSendStuffBit(1);
908 // ToSendStuffBit(1);
909 // ToSendStuffBit(1);
910 // }
911
912 // for(i = 0; i < len; i++) {
913 // int j;
914 // uint8_t b = cmd[i];
915
916 // // Start bit
917 // ToSendStuffBit(0);
918 // ToSendStuffBit(0);
919 // ToSendStuffBit(0);
920 // ToSendStuffBit(0);
921
922 // // Data bits
923 // for(j = 0; j < 8; j++) {
924 // if(b & 1) {
925 // ToSendStuffBit(1);
926 // ToSendStuffBit(1);
927 // ToSendStuffBit(1);
928 // ToSendStuffBit(1);
929 // } else {
930 // ToSendStuffBit(0);
931 // ToSendStuffBit(0);
932 // ToSendStuffBit(0);
933 // ToSendStuffBit(0);
934 // }
935 // b >>= 1;
936 // }
937
938 // // Stop bit
939 // ToSendStuffBit(1);
940 // ToSendStuffBit(1);
941 // ToSendStuffBit(1);
942 // ToSendStuffBit(1);
943 // }
944
945 // // Send EOF.
946 // for(i = 0; i < 10; i++) {
947 // ToSendStuffBit(0);
948 // ToSendStuffBit(0);
949 // ToSendStuffBit(0);
950 // ToSendStuffBit(0);
951 // }
952 // for(i = 0; i < 2; i++) {
953 // ToSendStuffBit(1);
954 // ToSendStuffBit(1);
955 // ToSendStuffBit(1);
956 // ToSendStuffBit(1);
957 // }
958
959 // // Convert from last byte pos to length
960 // ToSendMax++;
961 // }
962
963 //-----------------------------------------------------------------------------
964 // The software UART that receives commands from the reader, and its state
965 // variables.
966 //-----------------------------------------------------------------------------
967 /*
968 static struct {
969 enum {
970 STATE_UNSYNCD,
971 STATE_GOT_FALLING_EDGE_OF_SOF,
972 STATE_AWAITING_START_BIT,
973 STATE_RECEIVING_DATA
974 } state;
975 uint16_t shiftReg;
976 int bitCnt;
977 int byteCnt;
978 int byteCntMax;
979 int posCnt;
980 uint8_t *output;
981 } Uart;
982 */
983 /* Receive & handle a bit coming from the reader.
984 *
985 * This function is called 4 times per bit (every 2 subcarrier cycles).
986 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
987 *
988 * LED handling:
989 * LED A -> ON once we have received the SOF and are expecting the rest.
990 * LED A -> OFF once we have received EOF or are in error state or unsynced
991 *
992 * Returns: true if we received a EOF
993 * false if we are still waiting for some more
994 */
995 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
996 // {
997 // switch(Uart.state) {
998 // case STATE_UNSYNCD:
999 // if(!bit) {
1000 // // we went low, so this could be the beginning of an SOF
1001 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1002 // Uart.posCnt = 0;
1003 // Uart.bitCnt = 0;
1004 // }
1005 // break;
1006
1007 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1008 // Uart.posCnt++;
1009 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1010 // if(bit) {
1011 // if(Uart.bitCnt > 9) {
1012 // // we've seen enough consecutive
1013 // // zeros that it's a valid SOF
1014 // Uart.posCnt = 0;
1015 // Uart.byteCnt = 0;
1016 // Uart.state = STATE_AWAITING_START_BIT;
1017 // LED_A_ON(); // Indicate we got a valid SOF
1018 // } else {
1019 // // didn't stay down long enough
1020 // // before going high, error
1021 // Uart.state = STATE_UNSYNCD;
1022 // }
1023 // } else {
1024 // // do nothing, keep waiting
1025 // }
1026 // Uart.bitCnt++;
1027 // }
1028 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1029 // if(Uart.bitCnt > 12) {
1030 // // Give up if we see too many zeros without
1031 // // a one, too.
1032 // LED_A_OFF();
1033 // Uart.state = STATE_UNSYNCD;
1034 // }
1035 // break;
1036
1037 // case STATE_AWAITING_START_BIT:
1038 // Uart.posCnt++;
1039 // if(bit) {
1040 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1041 // // stayed high for too long between
1042 // // characters, error
1043 // Uart.state = STATE_UNSYNCD;
1044 // }
1045 // } else {
1046 // // falling edge, this starts the data byte
1047 // Uart.posCnt = 0;
1048 // Uart.bitCnt = 0;
1049 // Uart.shiftReg = 0;
1050 // Uart.state = STATE_RECEIVING_DATA;
1051 // }
1052 // break;
1053
1054 // case STATE_RECEIVING_DATA:
1055 // Uart.posCnt++;
1056 // if(Uart.posCnt == 2) {
1057 // // time to sample a bit
1058 // Uart.shiftReg >>= 1;
1059 // if(bit) {
1060 // Uart.shiftReg |= 0x200;
1061 // }
1062 // Uart.bitCnt++;
1063 // }
1064 // if(Uart.posCnt >= 4) {
1065 // Uart.posCnt = 0;
1066 // }
1067 // if(Uart.bitCnt == 10) {
1068 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1069 // {
1070 // // this is a data byte, with correct
1071 // // start and stop bits
1072 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1073 // Uart.byteCnt++;
1074
1075 // if(Uart.byteCnt >= Uart.byteCntMax) {
1076 // // Buffer overflowed, give up
1077 // LED_A_OFF();
1078 // Uart.state = STATE_UNSYNCD;
1079 // } else {
1080 // // so get the next byte now
1081 // Uart.posCnt = 0;
1082 // Uart.state = STATE_AWAITING_START_BIT;
1083 // }
1084 // } else if (Uart.shiftReg == 0x000) {
1085 // // this is an EOF byte
1086 // LED_A_OFF(); // Finished receiving
1087 // Uart.state = STATE_UNSYNCD;
1088 // if (Uart.byteCnt != 0) {
1089 // return TRUE;
1090 // }
1091 // } else {
1092 // // this is an error
1093 // LED_A_OFF();
1094 // Uart.state = STATE_UNSYNCD;
1095 // }
1096 // }
1097 // break;
1098
1099 // default:
1100 // LED_A_OFF();
1101 // Uart.state = STATE_UNSYNCD;
1102 // break;
1103 // }
1104
1105 // return FALSE;
1106 // }
1107 /*
1108
1109 static void UartReset() {
1110 Uart.byteCntMax = 3;
1111 Uart.state = STATE_UNSYNCD;
1112 Uart.byteCnt = 0;
1113 Uart.bitCnt = 0;
1114 Uart.posCnt = 0;
1115 memset(Uart.output, 0x00, 3);
1116 }
1117 */
1118 // static void UartInit(uint8_t *data) {
1119 // Uart.output = data;
1120 // UartReset();
1121 // }
1122
1123 //=============================================================================
1124 // An LEGIC reader. We take layer two commands, code them
1125 // appropriately, and then send them to the tag. We then listen for the
1126 // tag's response, which we leave in the buffer to be demodulated on the
1127 // PC side.
1128 //=============================================================================
1129 /*
1130 static struct {
1131 enum {
1132 DEMOD_UNSYNCD,
1133 DEMOD_PHASE_REF_TRAINING,
1134 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1135 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1136 DEMOD_AWAITING_START_BIT,
1137 DEMOD_RECEIVING_DATA
1138 } state;
1139 int bitCount;
1140 int posCount;
1141 int thisBit;
1142 uint16_t shiftReg;
1143 uint8_t *output;
1144 int len;
1145 int sumI;
1146 int sumQ;
1147 } Demod;
1148 */
1149 /*
1150 * Handles reception of a bit from the tag
1151 *
1152 * This function is called 2 times per bit (every 4 subcarrier cycles).
1153 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1154 *
1155 * LED handling:
1156 * LED C -> ON once we have received the SOF and are expecting the rest.
1157 * LED C -> OFF once we have received EOF or are unsynced
1158 *
1159 * Returns: true if we received a EOF
1160 * false if we are still waiting for some more
1161 *
1162 */
1163
1164 /*
1165 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1166 {
1167 int v = 0;
1168 int ai = ABS(ci);
1169 int aq = ABS(cq);
1170 int halfci = (ai >> 1);
1171 int halfcq = (aq >> 1);
1172
1173 switch(Demod.state) {
1174 case DEMOD_UNSYNCD:
1175
1176 CHECK_FOR_SUBCARRIER()
1177
1178 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1179 Demod.state = DEMOD_PHASE_REF_TRAINING;
1180 Demod.sumI = ci;
1181 Demod.sumQ = cq;
1182 Demod.posCount = 1;
1183 }
1184 break;
1185
1186 case DEMOD_PHASE_REF_TRAINING:
1187 if(Demod.posCount < 8) {
1188
1189 CHECK_FOR_SUBCARRIER()
1190
1191 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1192 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1193 // note: synchronization time > 80 1/fs
1194 Demod.sumI += ci;
1195 Demod.sumQ += cq;
1196 ++Demod.posCount;
1197 } else {
1198 // subcarrier lost
1199 Demod.state = DEMOD_UNSYNCD;
1200 }
1201 } else {
1202 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1203 }
1204 break;
1205
1206 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1207
1208 MAKE_SOFT_DECISION()
1209
1210 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1211 // logic '0' detected
1212 if (v <= 0) {
1213
1214 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1215
1216 // start of SOF sequence
1217 Demod.posCount = 0;
1218 } else {
1219 // maximum length of TR1 = 200 1/fs
1220 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1221 }
1222 ++Demod.posCount;
1223 break;
1224
1225 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1226 ++Demod.posCount;
1227
1228 MAKE_SOFT_DECISION()
1229
1230 if(v > 0) {
1231 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1232 if(Demod.posCount < 10*2) {
1233 Demod.state = DEMOD_UNSYNCD;
1234 } else {
1235 LED_C_ON(); // Got SOF
1236 Demod.state = DEMOD_AWAITING_START_BIT;
1237 Demod.posCount = 0;
1238 Demod.len = 0;
1239 }
1240 } else {
1241 // low phase of SOF too long (> 12 etu)
1242 if(Demod.posCount > 13*2) {
1243 Demod.state = DEMOD_UNSYNCD;
1244 LED_C_OFF();
1245 }
1246 }
1247 break;
1248
1249 case DEMOD_AWAITING_START_BIT:
1250 ++Demod.posCount;
1251
1252 MAKE_SOFT_DECISION()
1253
1254 if(v > 0) {
1255 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1256 if(Demod.posCount > 3*2) {
1257 Demod.state = DEMOD_UNSYNCD;
1258 LED_C_OFF();
1259 }
1260 } else {
1261 // start bit detected
1262 Demod.bitCount = 0;
1263 Demod.posCount = 1; // this was the first half
1264 Demod.thisBit = v;
1265 Demod.shiftReg = 0;
1266 Demod.state = DEMOD_RECEIVING_DATA;
1267 }
1268 break;
1269
1270 case DEMOD_RECEIVING_DATA:
1271
1272 MAKE_SOFT_DECISION()
1273
1274 if(Demod.posCount == 0) {
1275 // first half of bit
1276 Demod.thisBit = v;
1277 Demod.posCount = 1;
1278 } else {
1279 // second half of bit
1280 Demod.thisBit += v;
1281 Demod.shiftReg >>= 1;
1282 // logic '1'
1283 if(Demod.thisBit > 0)
1284 Demod.shiftReg |= 0x200;
1285
1286 ++Demod.bitCount;
1287
1288 if(Demod.bitCount == 10) {
1289
1290 uint16_t s = Demod.shiftReg;
1291
1292 if((s & 0x200) && !(s & 0x001)) {
1293 // stop bit == '1', start bit == '0'
1294 uint8_t b = (s >> 1);
1295 Demod.output[Demod.len] = b;
1296 ++Demod.len;
1297 Demod.state = DEMOD_AWAITING_START_BIT;
1298 } else {
1299 Demod.state = DEMOD_UNSYNCD;
1300 LED_C_OFF();
1301
1302 if(s == 0x000) {
1303 // This is EOF (start, stop and all data bits == '0'
1304 return TRUE;
1305 }
1306 }
1307 }
1308 Demod.posCount = 0;
1309 }
1310 break;
1311
1312 default:
1313 Demod.state = DEMOD_UNSYNCD;
1314 LED_C_OFF();
1315 break;
1316 }
1317 return FALSE;
1318 }
1319 */
1320 /*
1321 // Clear out the state of the "UART" that receives from the tag.
1322 static void DemodReset() {
1323 Demod.len = 0;
1324 Demod.state = DEMOD_UNSYNCD;
1325 Demod.posCount = 0;
1326 Demod.sumI = 0;
1327 Demod.sumQ = 0;
1328 Demod.bitCount = 0;
1329 Demod.thisBit = 0;
1330 Demod.shiftReg = 0;
1331 memset(Demod.output, 0x00, 3);
1332 }
1333
1334 static void DemodInit(uint8_t *data) {
1335 Demod.output = data;
1336 DemodReset();
1337 }
1338 */
1339
1340 /*
1341 * Demodulate the samples we received from the tag, also log to tracebuffer
1342 * quiet: set to 'TRUE' to disable debug output
1343 */
1344
1345 /*
1346 #define LEGIC_DMA_BUFFER_SIZE 256
1347
1348 static void GetSamplesForLegicDemod(int n, bool quiet)
1349 {
1350 int max = 0;
1351 bool gotFrame = FALSE;
1352 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1353 int ci, cq, samples = 0;
1354
1355 BigBuf_free();
1356
1357 // And put the FPGA in the appropriate mode
1358 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1359
1360 // The response (tag -> reader) that we're receiving.
1361 // Set up the demodulator for tag -> reader responses.
1362 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1363
1364 // The DMA buffer, used to stream samples from the FPGA
1365 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1366 int8_t *upTo = dmaBuf;
1367
1368 // Setup and start DMA.
1369 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1370 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1371 return;
1372 }
1373
1374 // Signal field is ON with the appropriate LED:
1375 LED_D_ON();
1376 for(;;) {
1377 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1378 if(behindBy > max) max = behindBy;
1379
1380 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1381 ci = upTo[0];
1382 cq = upTo[1];
1383 upTo += 2;
1384 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1385 upTo = dmaBuf;
1386 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1387 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1388 }
1389 lastRxCounter -= 2;
1390 if(lastRxCounter <= 0)
1391 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1392
1393 samples += 2;
1394
1395 gotFrame = HandleLegicSamplesDemod(ci , cq );
1396 if ( gotFrame )
1397 break;
1398 }
1399
1400 if(samples > n || gotFrame)
1401 break;
1402 }
1403
1404 FpgaDisableSscDma();
1405
1406 if (!quiet && Demod.len == 0) {
1407 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1408 max,
1409 samples,
1410 gotFrame,
1411 Demod.len,
1412 Demod.sumI,
1413 Demod.sumQ
1414 );
1415 }
1416
1417 //Tracing
1418 if (Demod.len > 0) {
1419 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1420 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1421 }
1422 }
1423
1424 */
1425
1426 //-----------------------------------------------------------------------------
1427 // Transmit the command (to the tag) that was placed in ToSend[].
1428 //-----------------------------------------------------------------------------
1429 /*
1430 static void TransmitForLegic(void)
1431 {
1432 int c;
1433
1434 FpgaSetupSsc();
1435
1436 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1437 AT91C_BASE_SSC->SSC_THR = 0xff;
1438
1439 // Signal field is ON with the appropriate Red LED
1440 LED_D_ON();
1441
1442 // Signal we are transmitting with the Green LED
1443 LED_B_ON();
1444 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1445
1446 for(c = 0; c < 10;) {
1447 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1448 AT91C_BASE_SSC->SSC_THR = 0xff;
1449 c++;
1450 }
1451 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1452 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1453 (void)r;
1454 }
1455 WDT_HIT();
1456 }
1457
1458 c = 0;
1459 for(;;) {
1460 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1461 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1462 legic_prng_forward(1); // forward the lfsr
1463 c++;
1464 if(c >= ToSendMax) {
1465 break;
1466 }
1467 }
1468 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1469 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1470 (void)r;
1471 }
1472 WDT_HIT();
1473 }
1474 LED_B_OFF();
1475 }
1476 */
1477
1478 //-----------------------------------------------------------------------------
1479 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1480 // so that it is ready to transmit to the tag using TransmitForLegic().
1481 //-----------------------------------------------------------------------------
1482 /*
1483 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1484 {
1485 int i, j;
1486 uint8_t b;
1487
1488 ToSendReset();
1489
1490 // Send SOF
1491 for(i = 0; i < 7; i++)
1492 ToSendStuffBit(1);
1493
1494
1495 for(i = 0; i < cmdlen; i++) {
1496 // Start bit
1497 ToSendStuffBit(0);
1498
1499 // Data bits
1500 b = cmd[i];
1501 for(j = 0; j < bits; j++) {
1502 if(b & 1) {
1503 ToSendStuffBit(1);
1504 } else {
1505 ToSendStuffBit(0);
1506 }
1507 b >>= 1;
1508 }
1509 }
1510
1511 // Convert from last character reference to length
1512 ++ToSendMax;
1513 }
1514 */
1515 /**
1516 Convenience function to encode, transmit and trace Legic comms
1517 **/
1518 /*
1519 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1520 {
1521 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1522 TransmitForLegic();
1523 if (tracing) {
1524 uint8_t parity[1] = {0x00};
1525 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1526 }
1527 }
1528
1529 */
1530 // Set up LEGIC communication
1531 /*
1532 void ice_legic_setup() {
1533
1534 // standard things.
1535 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1536 BigBuf_free(); BigBuf_Clear_ext(false);
1537 clear_trace();
1538 set_tracing(TRUE);
1539 DemodReset();
1540 UartReset();
1541
1542 // Set up the synchronous serial port
1543 FpgaSetupSsc();
1544
1545 // connect Demodulated Signal to ADC:
1546 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1547
1548 // Signal field is on with the appropriate LED
1549 LED_D_ON();
1550 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1551 SpinDelay(20);
1552 // Start the timer
1553 //StartCountSspClk();
1554
1555 // initalize CRC
1556 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1557
1558 // initalize prng
1559 legic_prng_init(0);
1560 }
1561 */
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