1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
5 //-----------------------------------------------------------------------------
6 // Main code for the bootloader
7 //-----------------------------------------------------------------------------
12 //#include "usb_hid.h"
14 void DbpString(char *str
) {
16 while (str
[len
] != 0x00) {
19 cmd_send(CMD_DEBUG_PRINT_STRING
,len
,0,0,(byte_t
*)str
,len
);
22 struct common_area common_area
__attribute__((section(".commonarea")));
23 unsigned int start_addr
, end_addr
, bootrom_unlocked
;
24 extern char _bootrom_start
, _bootrom_end
, _flash_start
, _flash_end
;
26 static void ConfigClocks(void)
28 // we are using a 16 MHz crystal as the basis for everything
29 // slow clock runs at 32Khz typical regardless of crystal
31 // enable system clock and USB clock
32 AT91C_BASE_PMC
->PMC_SCER
= AT91C_PMC_PCK
| AT91C_PMC_UDP
;
34 // enable the clock to the following peripherals
35 AT91C_BASE_PMC
->PMC_PCER
=
43 // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
44 // if SLCK slow clock runs at its worst case (max) frequency of 42khz
45 // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
47 // enable main oscillator and set startup delay
48 AT91C_BASE_PMC
->PMC_MOR
=
50 PMC_MAIN_OSC_STARTUP_DELAY(8);
52 // wait for main oscillator to stabilize
53 while ( !(AT91C_BASE_PMC
->PMC_SR
& AT91C_PMC_MOSCS
) )
56 // PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
57 // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
58 // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
59 AT91C_BASE_PMC
->PMC_PLLR
=
61 PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
62 PMC_PLL_FREQUENCY_RANGE(0) |
63 PMC_PLL_MULTIPLIER(12) |
64 PMC_PLL_USB_DIVISOR(1);
66 // wait for PLL to lock
67 while ( !(AT91C_BASE_PMC
->PMC_SR
& AT91C_PMC_LOCK
) )
70 // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
71 // datasheet recommends that this register is programmed in two operations
72 // when changing to PLL, program the prescaler first then the source
73 AT91C_BASE_PMC
->PMC_MCKR
= AT91C_PMC_PRES_CLK_2
;
75 // wait for main clock ready signal
76 while ( !(AT91C_BASE_PMC
->PMC_SR
& AT91C_PMC_MCKRDY
) )
79 // set the source to PLL
80 AT91C_BASE_PMC
->PMC_MCKR
= AT91C_PMC_PRES_CLK_2
| AT91C_PMC_CSS_PLL_CLK
;
82 // wait for main clock ready signal
83 while ( !(AT91C_BASE_PMC
->PMC_SR
& AT91C_PMC_MCKRDY
) )
87 static void Fatal(void)
92 void UsbPacketReceived(uint8_t *packet
, int len
) {
94 UsbCommand
* c
= (UsbCommand
*)packet
;
97 if(len
!= sizeof(UsbCommand
)) {
101 uint32_t arg0
= (uint32_t)c
->arg
[0];
104 case CMD_DEVICE_INFO
: {
106 arg0
= DEVICE_INFO_FLAG_BOOTROM_PRESENT
| DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM
|
107 DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH
;
108 if(common_area
.flags
.osimage_present
) {
109 arg0
|= DEVICE_INFO_FLAG_OSIMAGE_PRESENT
;
111 cmd_send(CMD_DEVICE_INFO
,arg0
,1,2,0,0);
114 case CMD_SETUP_WRITE
: {
115 /* The temporary write buffer of the embedded flash controller is mapped to the
116 * whole memory region, only the last 8 bits are decoded.
118 p
= (volatile uint32_t *)&_flash_start
;
119 for(i
= 0; i
< 12; i
++) {
120 p
[i
+arg0
] = c
->d
.asDwords
[i
];
124 case CMD_FINISH_WRITE
: {
125 uint32_t* flash_mem
= (uint32_t*)(&_flash_start
);
126 for (size_t j
=0; j
<2; j
++) {
127 for(i
= 0+(64*j
); i
< 64+(64*j
); i
++) {
128 flash_mem
[i
] = c
->d
.asDwords
[i
];
131 uint32_t flash_address
= arg0
+ (0x100*j
);
133 /* Check that the address that we are supposed to write to is within our allowed region */
134 if( ((flash_address
+AT91C_IFLASH_PAGE_SIZE
-1) >= end_addr
) || (flash_address
< start_addr
) ) {
137 cmd_send(CMD_NACK
,0,0,0,0,0);
139 uint32_t page_n
= (flash_address
- ((uint32_t)flash_mem
)) / AT91C_IFLASH_PAGE_SIZE
;
140 /* Translate address to flash page and do flash, update here for the 512k part */
141 AT91C_BASE_EFC0
->EFC_FCR
= MC_FLASH_COMMAND_KEY
|
142 MC_FLASH_COMMAND_PAGEN(page_n
) |
143 AT91C_MC_FCMD_START_PROG
;
146 // Wait until flashing of page finishes
148 while(!((sr
= AT91C_BASE_EFC0
->EFC_FSR
) & AT91C_MC_FRDY
));
149 if(sr
& (AT91C_MC_LOCKE
| AT91C_MC_PROGE
)) {
151 cmd_send(CMD_NACK
,0,0,0,0,0);
156 case CMD_HARDWARE_RESET
: {
158 AT91C_BASE_RSTC
->RSTC_RCR
= RST_CONTROL_KEY
| AT91C_RSTC_PROCRST
;
161 case CMD_START_FLASH
: {
162 if(c
->arg
[2] == START_FLASH_MAGIC
) bootrom_unlocked
= 1;
163 else bootrom_unlocked
= 0;
165 int prot_start
= (int)&_bootrom_start
;
166 int prot_end
= (int)&_bootrom_end
;
167 int allow_start
= (int)&_flash_start
;
168 int allow_end
= (int)&_flash_end
;
169 int cmd_start
= c
->arg
[0];
170 int cmd_end
= c
->arg
[1];
172 /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
173 * bootrom area. In any case they must be within the flash area.
175 if( (bootrom_unlocked
|| ((cmd_start
>= prot_end
) || (cmd_end
< prot_start
)))
176 && (cmd_start
>= allow_start
) && (cmd_end
<= allow_end
) ) {
177 start_addr
= cmd_start
;
180 start_addr
= end_addr
= 0;
182 cmd_send(CMD_NACK
,0,0,0,0,0);
193 cmd_send(CMD_ACK
,arg0
,0,0,0,0);
197 static void flash_mode(int externally_entered
)
201 bootrom_unlocked
= 0;
202 byte_t rx
[sizeof(UsbCommand
)];
206 for (volatile size_t i
=0; i
<0x100000; i
++) {};
212 rx_len
= usb_read(rx
,sizeof(UsbCommand
));
214 UsbPacketReceived(rx
,rx_len
);
218 if(!externally_entered
&& !BUTTON_PRESS()) {
219 /* Perform a reset to leave flash mode */
222 AT91C_BASE_RSTC
->RSTC_RCR
= RST_CONTROL_KEY
| AT91C_RSTC_PROCRST
;
225 if(externally_entered
&& BUTTON_PRESS()) {
226 /* Let the user's button press override the automatic leave */
227 externally_entered
= 0;
232 extern uint32_t _osimage_entry
;
236 // First set up all the I/O pins; GPIOs configured directly, other ones
237 // just need to be assigned to the appropriate peripheral.
239 // Kill all the pullups, especially the one on USB D+; leave them for
240 // the unused pins, though.
241 AT91C_BASE_PIOA
->PIO_PPUDR
=
259 // (and add GPIO_FPGA_ON)
260 // These pins are outputs
261 AT91C_BASE_PIOA
->PIO_OER
=
268 // PIO controls the following pins
269 AT91C_BASE_PIOA
->PIO_PER
=
276 // USB_D_PLUS_PULLUP_OFF();
283 AT91C_BASE_EFC0
->EFC_FMR
=
285 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
287 // Initialize all system clocks
292 int common_area_present
= 0;
293 switch(AT91C_BASE_RSTC
->RSTC_RSR
& AT91C_RSTC_RSTTYP
) {
294 case AT91C_RSTC_RSTTYP_WATCHDOG
:
295 case AT91C_RSTC_RSTTYP_SOFTWARE
:
296 case AT91C_RSTC_RSTTYP_USER
:
297 /* In these cases the common_area in RAM should be ok, retain it if it's there */
298 if(common_area
.magic
== COMMON_AREA_MAGIC
&& common_area
.version
== 1) {
299 common_area_present
= 1;
302 default: /* Otherwise, initialize it from scratch */
306 if(!common_area_present
){
307 /* Common area not ok, initialize it */
308 int i
; for(i
=0; i
<sizeof(common_area
); i
++) { /* Makeshift memset, no need to drag util.c into this */
309 ((char*)&common_area
)[i
] = 0;
311 common_area
.magic
= COMMON_AREA_MAGIC
;
312 common_area
.version
= 1;
313 common_area
.flags
.bootrom_present
= 1;
316 common_area
.flags
.bootrom_present
= 1;
317 if(common_area
.command
== COMMON_AREA_COMMAND_ENTER_FLASH_MODE
) {
318 common_area
.command
= COMMON_AREA_COMMAND_NONE
;
320 } else if(BUTTON_PRESS()) {
322 } else if(_osimage_entry
== 0xffffffffU
) {
325 // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
326 __asm("bx %0\n" : : "r" ( ((int)&_osimage_entry
) | 0x1 ) );