git.zerfleddert.de Git - proxmark3-svn/blob - bootrom/bootrom.c

   1 //-----------------------------------------------------------------------------
   2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
   3 // at your option, any later version. See the LICENSE.txt file for the text of
   4 // the license.
   5 //-----------------------------------------------------------------------------
   6 // Main code for the bootloader
   7 //-----------------------------------------------------------------------------
   8
   9 #include <proxmark3.h>
  10 #include "usb_cdc.h"
  11 #include "cmd.h"
  12 //#include "usb_hid.h"
  13
  14 void DbpString(char *str) {
  15   byte_t len = 0;
  16   while (str[len] != 0x00) {
  17     len++;
  18   }
  19   cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len);
  20 }
  21
  22 struct common_area common_area __attribute__((section(".commonarea")));
  23 unsigned int start_addr, end_addr, bootrom_unlocked;
  24 extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
  25
  26 static void ConfigClocks(void)
  27 {
  28     // we are using a 16 MHz crystal as the basis for everything
  29     // slow clock runs at 32Khz typical regardless of crystal
  30
  31     // enable system clock and USB clock
  32     AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;
  33
  34         // enable the clock to the following peripherals
  35     AT91C_BASE_PMC->PMC_PCER =
  36                 (1<<AT91C_ID_PIOA)      |
  37                 (1<<AT91C_ID_ADC)       |
  38                 (1<<AT91C_ID_SPI)       |
  39                 (1<<AT91C_ID_SSC)       |
  40                 (1<<AT91C_ID_PWMC)      |
  41                 (1<<AT91C_ID_UDP);
  42
  43         // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
  44         // if SLCK slow clock runs at its worst case (max) frequency of 42khz
  45         // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
  46
  47         // enable main oscillator and set startup delay
  48     AT91C_BASE_PMC->PMC_MOR =
  49         AT91C_CKGR_MOSCEN |
  50         PMC_MAIN_OSC_STARTUP_DELAY(8);
  51
  52         // wait for main oscillator to stabilize
  53         while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
  54                 ;
  55
  56     // PLL output clock frequency in range  80 - 160 MHz needs CKGR_PLL = 00
  57     // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
  58     // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
  59     AT91C_BASE_PMC->PMC_PLLR =
  60         PMC_PLL_DIVISOR(2) |
  61                 PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
  62                 PMC_PLL_FREQUENCY_RANGE(0) |
  63                 PMC_PLL_MULTIPLIER(12) |
  64                 PMC_PLL_USB_DIVISOR(1);
  65
  66         // wait for PLL to lock
  67         while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
  68                 ;
  69
  70         // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
  71         // datasheet recommends that this register is programmed in two operations
  72         // when changing to PLL, program the prescaler first then the source
  73     AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
  74
  75         // wait for main clock ready signal
  76         while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
  77                 ;
  78
  79         // set the source to PLL
  80     AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
  81
  82         // wait for main clock ready signal
  83         while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
  84                 ;
  85 }
  86
  87 static void Fatal(void)
  88 {
  89   for(;;);
  90 }
  91
  92 void UsbPacketReceived(uint8_t *packet, int len) {
  93   int i, dont_ack=0;
  94   UsbCommand* c = (UsbCommand *)packet;
  95   volatile uint32_t *p;
  96
  97   if(len != sizeof(UsbCommand)) {
  98     Fatal();
  99   }
 100
 101   uint32_t arg0 = (uint32_t)c->arg[0];
 102
 103   switch(c->cmd) {
 104     case CMD_DEVICE_INFO: {
 105       dont_ack = 1;
 106       arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
 107       DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
 108       if(common_area.flags.osimage_present) {
 109         arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
 110       }
 111       cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
 112     } break;
 113
 114     case CMD_SETUP_WRITE: {
 115       /* The temporary write buffer of the embedded flash controller is mapped to the
 116        * whole memory region, only the last 8 bits are decoded.
 117        */
 118       p = (volatile uint32_t *)&_flash_start;
 119       for(i = 0; i < 12; i++) {
 120         p[i+arg0] = c->d.asDwords[i];
 121       }
 122     } break;
 123
 124     case CMD_FINISH_WRITE: {
 125       uint32_t* flash_mem = (uint32_t*)(&_flash_start);
 126       for (size_t j=0; j<2; j++) {
 127         for(i = 0+(64*j); i < 64+(64*j); i++) {
 128           flash_mem[i] = c->d.asDwords[i];
 129         }
 130
 131         uint32_t flash_address = arg0 + (0x100*j);
 132
 133         /* Check that the address that we are supposed to write to is within our allowed region */
 134         if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (flash_address < start_addr) ) {
 135           /* Disallow write */
 136           dont_ack = 1;
 137           cmd_send(CMD_NACK,0,0,0,0,0);
 138         } else {
 139           uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
 140           /* Translate address to flash page and do flash, update here for the 512k part */
 141           AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
 142           MC_FLASH_COMMAND_PAGEN(page_n) |
 143           AT91C_MC_FCMD_START_PROG;
 144         }
 145
 146         // Wait until flashing of page finishes
 147         uint32_t sr;
 148         while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
 149         if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
 150           dont_ack = 1;
 151           cmd_send(CMD_NACK,0,0,0,0,0);
 152         }
 153       }
 154     } break;
 155
 156     case CMD_HARDWARE_RESET: {
 157       usb_disable();
 158       AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
 159     } break;
 160
 161     case CMD_START_FLASH: {
 162       if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
 163       else bootrom_unlocked = 0;
 164       {
 165         int prot_start = (int)&_bootrom_start;
 166         int prot_end = (int)&_bootrom_end;
 167         int allow_start = (int)&_flash_start;
 168         int allow_end = (int)&_flash_end;
 169         int cmd_start = c->arg[0];
 170         int cmd_end = c->arg[1];
 171
 172         /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
 173          * bootrom area. In any case they must be within the flash area.
 174          */
 175         if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
 176            && (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
 177           start_addr = cmd_start;
 178           end_addr = cmd_end;
 179         } else {
 180           start_addr = end_addr = 0;
 181           dont_ack = 1;
 182           cmd_send(CMD_NACK,0,0,0,0,0);
 183         }
 184       }
 185     } break;
 186
 187     default: {
 188       Fatal();
 189     } break;
 190   }
 191
 192   if(!dont_ack) {
 193     cmd_send(CMD_ACK,arg0,0,0,0,0);
 194   }
 195 }
 196
 197 static void flash_mode(int externally_entered)
 198 {
 199         start_addr = 0;
 200         end_addr = 0;
 201         bootrom_unlocked = 0;
 202   byte_t rx[sizeof(UsbCommand)];
 203         size_t rx_len;
 204
 205   usb_enable();
 206   for (volatile size_t i=0; i<0x100000; i++);
 207
 208         for(;;) {
 209                 WDT_HIT();
 210
 211     if (usb_poll()) {
 212       rx_len = usb_read(rx,sizeof(UsbCommand));
 213       if (rx_len) {
 214         UsbPacketReceived(rx,rx_len);
 215       }
 216     }
 217
 218                 if(!externally_entered && !BUTTON_PRESS()) {
 219                         /* Perform a reset to leave flash mode */
 220                 usb_disable();
 221                         LED_B_ON();
 222                         AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
 223                         for(;;);
 224                 }
 225                 if(externally_entered && BUTTON_PRESS()) {
 226                         /* Let the user's button press override the automatic leave */
 227                         externally_entered = 0;
 228                 }
 229         }
 230 }
 231
 232 extern uint32_t _osimage_entry;
 233 void BootROM(void)
 234 {
 235     //------------
 236     // First set up all the I/O pins; GPIOs configured directly, other ones
 237     // just need to be assigned to the appropriate peripheral.
 238
 239     // Kill all the pullups, especially the one on USB D+; leave them for
 240     // the unused pins, though.
 241     AT91C_BASE_PIOA->PIO_PPUDR =
 242         GPIO_USB_PU                     |
 243                 GPIO_LED_A                      |
 244                 GPIO_LED_B                      |
 245                 GPIO_LED_C                      |
 246                 GPIO_LED_D                      |
 247                 GPIO_FPGA_DIN           |
 248                 GPIO_FPGA_DOUT          |
 249                 GPIO_FPGA_CCLK          |
 250                 GPIO_FPGA_NINIT         |
 251                 GPIO_FPGA_NPROGRAM      |
 252                 GPIO_FPGA_DONE          |
 253                 GPIO_MUXSEL_HIPKD       |
 254                 GPIO_MUXSEL_HIRAW       |
 255                 GPIO_MUXSEL_LOPKD       |
 256                 GPIO_MUXSEL_LORAW       |
 257                 GPIO_RELAY                      |
 258                 GPIO_NVDD_ON;
 259                 // (and add GPIO_FPGA_ON)
 260         // These pins are outputs
 261     AT91C_BASE_PIOA->PIO_OER =
 262         GPIO_LED_A                      |
 263                 GPIO_LED_B                      |
 264                 GPIO_LED_C                      |
 265                 GPIO_LED_D                      |
 266                 GPIO_RELAY                      |
 267                 GPIO_NVDD_ON;
 268         // PIO controls the following pins
 269     AT91C_BASE_PIOA->PIO_PER =
 270         GPIO_USB_PU                     |
 271                 GPIO_LED_A                      |
 272                 GPIO_LED_B                      |
 273                 GPIO_LED_C                      |
 274                 GPIO_LED_D;
 275
 276 //    USB_D_PLUS_PULLUP_OFF();
 277   usb_disable();
 278     LED_D_OFF();
 279     LED_C_ON();
 280     LED_B_OFF();
 281     LED_A_OFF();
 282
 283         AT91C_BASE_EFC0->EFC_FMR =
 284                 AT91C_MC_FWS_1FWS |
 285                 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
 286
 287     // Initialize all system clocks
 288     ConfigClocks();
 289
 290     LED_A_ON();
 291
 292     int common_area_present = 0;
 293     switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
 294     case AT91C_RSTC_RSTTYP_WATCHDOG:
 295     case AT91C_RSTC_RSTTYP_SOFTWARE:
 296     case AT91C_RSTC_RSTTYP_USER:
 297             /* In these cases the common_area in RAM should be ok, retain it if it's there */
 298             if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
 299                     common_area_present = 1;
 300             }
 301             break;
 302     default: /* Otherwise, initialize it from scratch */
 303             break;
 304     }
 305
 306     if(!common_area_present){
 307             /* Common area not ok, initialize it */
 308             int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
 309                     ((char*)&common_area)[i] = 0;
 310             }
 311             common_area.magic = COMMON_AREA_MAGIC;
 312             common_area.version = 1;
 313             common_area.flags.bootrom_present = 1;
 314     }
 315
 316     common_area.flags.bootrom_present = 1;
 317     if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
 318             common_area.command = COMMON_AREA_COMMAND_NONE;
 319             flash_mode(1);
 320     } else if(BUTTON_PRESS()) {
 321             flash_mode(0);
 322     } else if(_osimage_entry == 0xffffffffU) {
 323             flash_mode(1);
 324     } else {
 325             // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
 326             __asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
 327     }
 328 }