1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
13 #include "proxmark3.h"
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
22 #include "mifareutil.h"
24 static uint32_t iso14a_timeout
;
27 // the block number for the ISO14443-4 PCB
28 static uint8_t iso14_pcb_blocknum
= 0;
33 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
34 #define REQUEST_GUARD_TIME (7000/16 + 1)
35 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
36 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
37 // bool LastCommandWasRequest = FALSE;
40 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
42 // When the PM acts as reader and is receiving tag data, it takes
43 // 3 ticks delay in the AD converter
44 // 16 ticks until the modulation detector completes and sets curbit
45 // 8 ticks until bit_to_arm is assigned from curbit
46 // 8*16 ticks for the transfer from FPGA to ARM
47 // 4*16 ticks until we measure the time
48 // - 8*16 ticks because we measure the time of the previous transfer
49 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
51 // When the PM acts as a reader and is sending, it takes
52 // 4*16 ticks until we can write data to the sending hold register
53 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
54 // 8 ticks until the first transfer starts
55 // 8 ticks later the FPGA samples the data
56 // 1 tick to assign mod_sig_coil
57 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
59 // When the PM acts as tag and is receiving it takes
60 // 2 ticks delay in the RF part (for the first falling edge),
61 // 3 ticks for the A/D conversion,
62 // 8 ticks on average until the start of the SSC transfer,
63 // 8 ticks until the SSC samples the first data
64 // 7*16 ticks to complete the transfer from FPGA to ARM
65 // 8 ticks until the next ssp_clk rising edge
66 // 4*16 ticks until we measure the time
67 // - 8*16 ticks because we measure the time of the previous transfer
68 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
70 // The FPGA will report its internal sending delay in
71 uint16_t FpgaSendQueueDelay
;
72 // the 5 first bits are the number of bits buffered in mod_sig_buf
73 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
74 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
76 // When the PM acts as tag and is sending, it takes
77 // 4*16 ticks until we can write data to the sending hold register
78 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
79 // 8 ticks until the first transfer starts
80 // 8 ticks later the FPGA samples the data
81 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
82 // + 1 tick to assign mod_sig_coil
83 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
85 // When the PM acts as sniffer and is receiving tag data, it takes
86 // 3 ticks A/D conversion
87 // 14 ticks to complete the modulation detection
88 // 8 ticks (on average) until the result is stored in to_arm
89 // + the delays in transferring data - which is the same for
90 // sniffing reader and tag data and therefore not relevant
91 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
93 // When the PM acts as sniffer and is receiving reader data, it takes
94 // 2 ticks delay in analogue RF receiver (for the falling edge of the
95 // start bit, which marks the start of the communication)
96 // 3 ticks A/D conversion
97 // 8 ticks on average until the data is stored in to_arm.
98 // + the delays in transferring data - which is the same for
99 // sniffing reader and tag data and therefore not relevant
100 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
102 //variables used for timing purposes:
103 //these are in ssp_clk cycles:
104 static uint32_t NextTransferTime
;
105 static uint32_t LastTimeProxToAirStart
;
106 static uint32_t LastProxToAirDuration
;
110 // CARD TO READER - manchester
111 // Sequence D: 11110000 modulation with subcarrier during first half
112 // Sequence E: 00001111 modulation with subcarrier during second half
113 // Sequence F: 00000000 no modulation with subcarrier
114 // READER TO CARD - miller
115 // Sequence X: 00001100 drop after half a period
116 // Sequence Y: 00000000 no drop
117 // Sequence Z: 11000000 drop at start
125 const uint8_t OddByteParity
[256] = {
126 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
145 void iso14a_set_trigger(bool enable
) {
150 void iso14a_set_timeout(uint32_t timeout
) {
151 iso14a_timeout
= timeout
;
152 if(MF_DBGLEVEL
>= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout
, iso14a_timeout
/ 106);
156 void iso14a_set_ATS_timeout(uint8_t *ats
) {
162 if (ats
[0] > 1) { // there is a format byte T0
163 if ((ats
[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
164 if ((ats
[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
169 fwi
= (tb1
& 0xf0) >> 4; // frame waiting indicator (FWI)
170 fwt
= 256 * 16 * (1 << fwi
); // frame waiting time (FWT) in 1/fc
172 iso14a_set_timeout(fwt
/(8*16));
178 //-----------------------------------------------------------------------------
179 // Generate the parity value for a byte sequence
181 //-----------------------------------------------------------------------------
182 byte_t
oddparity (const byte_t bt
)
184 return OddByteParity
[bt
];
187 void GetParity(const uint8_t *pbtCmd
, uint16_t iLen
, uint8_t *par
)
189 uint16_t paritybit_cnt
= 0;
190 uint16_t paritybyte_cnt
= 0;
191 uint8_t parityBits
= 0;
193 for (uint16_t i
= 0; i
< iLen
; i
++) {
194 // Generate the parity bits
195 parityBits
|= ((OddByteParity
[pbtCmd
[i
]]) << (7-paritybit_cnt
));
196 if (paritybit_cnt
== 7) {
197 par
[paritybyte_cnt
] = parityBits
; // save 8 Bits parity
198 parityBits
= 0; // and advance to next Parity Byte
206 // save remaining parity bits
207 par
[paritybyte_cnt
] = parityBits
;
211 void AppendCrc14443a(uint8_t* data
, int len
)
213 ComputeCrc14443(CRC_14443_A
,data
,len
,data
+len
,data
+len
+1);
216 void AppendCrc14443b(uint8_t* data
, int len
)
218 ComputeCrc14443(CRC_14443_B
,data
,len
,data
+len
,data
+len
+1);
222 //=============================================================================
223 // ISO 14443 Type A - Miller decoder
224 //=============================================================================
226 // This decoder is used when the PM3 acts as a tag.
227 // The reader will generate "pauses" by temporarily switching of the field.
228 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
229 // The FPGA does a comparison with a threshold and would deliver e.g.:
230 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
231 // The Miller decoder needs to identify the following sequences:
232 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
233 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
234 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
235 // Note 1: the bitstream may start at any time. We therefore need to sync.
236 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
237 //-----------------------------------------------------------------------------
240 // Lookup-Table to decide if 4 raw bits are a modulation.
241 // We accept the following:
242 // 0001 - a 3 tick wide pause
243 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
244 // 0111 - a 2 tick wide pause shifted left
245 // 1001 - a 2 tick wide pause shifted right
246 const bool Mod_Miller_LUT
[] = {
247 FALSE
, TRUE
, FALSE
, TRUE
, FALSE
, FALSE
, FALSE
, TRUE
,
248 FALSE
, TRUE
, FALSE
, FALSE
, FALSE
, FALSE
, FALSE
, FALSE
250 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
251 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
255 Uart
.state
= STATE_UNSYNCD
;
257 Uart
.len
= 0; // number of decoded data bytes
258 Uart
.parityLen
= 0; // number of decoded parity bytes
259 Uart
.shiftReg
= 0; // shiftreg to hold decoded data bits
260 Uart
.parityBits
= 0; // holds 8 parity bits
265 void UartInit(uint8_t *data
, uint8_t *parity
)
268 Uart
.parity
= parity
;
269 Uart
.fourBits
= 0x00000000; // clear the buffer for 4 Bits
273 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
274 static RAMFUNC
bool MillerDecoding(uint8_t bit
, uint32_t non_real_time
)
277 Uart
.fourBits
= (Uart
.fourBits
<< 8) | bit
;
279 if (Uart
.state
== STATE_UNSYNCD
) { // not yet synced
281 Uart
.syncBit
= 9999; // not set
282 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
283 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
284 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
285 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
286 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
287 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
288 if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 0)) == ISO14443A_STARTBIT_PATTERN
>> 0) Uart
.syncBit
= 7;
289 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 1)) == ISO14443A_STARTBIT_PATTERN
>> 1) Uart
.syncBit
= 6;
290 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 2)) == ISO14443A_STARTBIT_PATTERN
>> 2) Uart
.syncBit
= 5;
291 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 3)) == ISO14443A_STARTBIT_PATTERN
>> 3) Uart
.syncBit
= 4;
292 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 4)) == ISO14443A_STARTBIT_PATTERN
>> 4) Uart
.syncBit
= 3;
293 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 5)) == ISO14443A_STARTBIT_PATTERN
>> 5) Uart
.syncBit
= 2;
294 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 6)) == ISO14443A_STARTBIT_PATTERN
>> 6) Uart
.syncBit
= 1;
295 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 7)) == ISO14443A_STARTBIT_PATTERN
>> 7) Uart
.syncBit
= 0;
297 if (Uart
.syncBit
!= 9999) { // found a sync bit
298 Uart
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
299 Uart
.startTime
-= Uart
.syncBit
;
300 Uart
.endTime
= Uart
.startTime
;
301 Uart
.state
= STATE_START_OF_COMMUNICATION
;
306 if (IsMillerModulationNibble1(Uart
.fourBits
>> Uart
.syncBit
)) {
307 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation in both halves - error
309 } else { // Modulation in first half = Sequence Z = logic "0"
310 if (Uart
.state
== STATE_MILLER_X
) { // error - must not follow after X
314 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
315 Uart
.state
= STATE_MILLER_Z
;
316 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 6;
317 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
318 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
319 Uart
.parityBits
<<= 1; // make room for the parity bit
320 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
323 if((Uart
.len
&0x0007) == 0) { // every 8 data bytes
324 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
331 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation second half = Sequence X = logic "1"
333 Uart
.shiftReg
= (Uart
.shiftReg
>> 1) | 0x100; // add a 1 to the shiftreg
334 Uart
.state
= STATE_MILLER_X
;
335 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 2;
336 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
337 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
338 Uart
.parityBits
<<= 1; // make room for the new parity bit
339 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
342 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
343 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
347 } else { // no modulation in both halves - Sequence Y
348 if (Uart
.state
== STATE_MILLER_Z
|| Uart
.state
== STATE_MILLER_Y
) { // Y after logic "0" - End of Communication
349 Uart
.state
= STATE_UNSYNCD
;
350 Uart
.bitCount
--; // last "0" was part of EOC sequence
351 Uart
.shiftReg
<<= 1; // drop it
352 if(Uart
.bitCount
> 0) { // if we decoded some bits
353 Uart
.shiftReg
>>= (9 - Uart
.bitCount
); // right align them
354 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff); // add last byte to the output
355 Uart
.parityBits
<<= 1; // add a (void) parity bit
356 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align parity bits
357 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store it
359 } else if (Uart
.len
& 0x0007) { // there are some parity bits to store
360 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align remaining parity bits
361 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store them
364 return TRUE
; // we are finished with decoding the raw data sequence
366 UartReset(); // Nothing received - start over
369 if (Uart
.state
== STATE_START_OF_COMMUNICATION
) { // error - must not follow directly after SOC
371 } else { // a logic "0"
373 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
374 Uart
.state
= STATE_MILLER_Y
;
375 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
376 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
377 Uart
.parityBits
<<= 1; // make room for the parity bit
378 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
381 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
382 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
392 return FALSE
; // not finished yet, need more data
397 //=============================================================================
398 // ISO 14443 Type A - Manchester decoder
399 //=============================================================================
401 // This decoder is used when the PM3 acts as a reader.
402 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
403 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
404 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
405 // The Manchester decoder needs to identify the following sequences:
406 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
407 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
408 // 8 ticks unmodulated: Sequence F = end of communication
409 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
410 // Note 1: the bitstream may start at any time. We therefore need to sync.
411 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
414 // Lookup-Table to decide if 4 raw bits are a modulation.
415 // We accept three or four "1" in any position
416 const bool Mod_Manchester_LUT
[] = {
417 FALSE
, FALSE
, FALSE
, FALSE
, FALSE
, FALSE
, FALSE
, TRUE
,
418 FALSE
, FALSE
, FALSE
, TRUE
, FALSE
, TRUE
, TRUE
, TRUE
421 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
422 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
427 Demod
.state
= DEMOD_UNSYNCD
;
428 Demod
.len
= 0; // number of decoded data bytes
430 Demod
.shiftReg
= 0; // shiftreg to hold decoded data bits
431 Demod
.parityBits
= 0; //
432 Demod
.collisionPos
= 0; // Position of collision bit
433 Demod
.twoBits
= 0xffff; // buffer for 2 Bits
439 void DemodInit(uint8_t *data
, uint8_t *parity
)
442 Demod
.parity
= parity
;
446 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
447 static RAMFUNC
int ManchesterDecoding(uint8_t bit
, uint16_t offset
, uint32_t non_real_time
)
450 Demod
.twoBits
= (Demod
.twoBits
<< 8) | bit
;
452 if (Demod
.state
== DEMOD_UNSYNCD
) {
454 if (Demod
.highCnt
< 2) { // wait for a stable unmodulated signal
455 if (Demod
.twoBits
== 0x0000) {
461 Demod
.syncBit
= 0xFFFF; // not set
462 if ((Demod
.twoBits
& 0x7700) == 0x7000) Demod
.syncBit
= 7;
463 else if ((Demod
.twoBits
& 0x3B80) == 0x3800) Demod
.syncBit
= 6;
464 else if ((Demod
.twoBits
& 0x1DC0) == 0x1C00) Demod
.syncBit
= 5;
465 else if ((Demod
.twoBits
& 0x0EE0) == 0x0E00) Demod
.syncBit
= 4;
466 else if ((Demod
.twoBits
& 0x0770) == 0x0700) Demod
.syncBit
= 3;
467 else if ((Demod
.twoBits
& 0x03B8) == 0x0380) Demod
.syncBit
= 2;
468 else if ((Demod
.twoBits
& 0x01DC) == 0x01C0) Demod
.syncBit
= 1;
469 else if ((Demod
.twoBits
& 0x00EE) == 0x00E0) Demod
.syncBit
= 0;
470 if (Demod
.syncBit
!= 0xFFFF) {
471 Demod
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
472 Demod
.startTime
-= Demod
.syncBit
;
473 Demod
.bitCount
= offset
; // number of decoded data bits
474 Demod
.state
= DEMOD_MANCHESTER_DATA
;
480 if (IsManchesterModulationNibble1(Demod
.twoBits
>> Demod
.syncBit
)) { // modulation in first half
481 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // ... and in second half = collision
482 if (!Demod
.collisionPos
) {
483 Demod
.collisionPos
= (Demod
.len
<< 3) + Demod
.bitCount
;
485 } // modulation in first half only - Sequence D = 1
487 Demod
.shiftReg
= (Demod
.shiftReg
>> 1) | 0x100; // in both cases, add a 1 to the shiftreg
488 if(Demod
.bitCount
== 9) { // if we decoded a full byte (including parity)
489 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
490 Demod
.parityBits
<<= 1; // make room for the parity bit
491 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
494 if((Demod
.len
&0x0007) == 0) { // every 8 data bytes
495 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits
496 Demod
.parityBits
= 0;
499 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1) - 4;
500 } else { // no modulation in first half
501 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // and modulation in second half = Sequence E = 0
503 Demod
.shiftReg
= (Demod
.shiftReg
>> 1); // add a 0 to the shiftreg
504 if(Demod
.bitCount
>= 9) { // if we decoded a full byte (including parity)
505 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
506 Demod
.parityBits
<<= 1; // make room for the new parity bit
507 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
510 if ((Demod
.len
&0x0007) == 0) { // every 8 data bytes
511 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits1
512 Demod
.parityBits
= 0;
515 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1);
516 } else { // no modulation in both halves - End of communication
517 if(Demod
.bitCount
> 0) { // there are some remaining data bits
518 Demod
.shiftReg
>>= (9 - Demod
.bitCount
); // right align the decoded bits
519 Demod
.output
[Demod
.len
++] = Demod
.shiftReg
& 0xff; // and add them to the output
520 Demod
.parityBits
<<= 1; // add a (void) parity bit
521 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
522 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
524 } else if (Demod
.len
& 0x0007) { // there are some parity bits to store
525 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
526 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
529 return TRUE
; // we are finished with decoding the raw data sequence
530 } else { // nothing received. Start over
538 return FALSE
; // not finished yet, need more data
541 //=============================================================================
542 // Finally, a `sniffer' for ISO 14443 Type A
543 // Both sides of communication!
544 //=============================================================================
546 //-----------------------------------------------------------------------------
547 // Record the sequence of commands sent by the reader to the tag, with
548 // triggering so that we start recording at the point that the tag is moved
550 //-----------------------------------------------------------------------------
551 void RAMFUNC
SnoopIso14443a(uint8_t param
) {
553 // bit 0 - trigger from first card answer
554 // bit 1 - trigger from first reader 7-bit request
558 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
560 // Allocate memory from BigBuf for some buffers
561 // free all previous allocations first
564 // The command (reader -> tag) that we're receiving.
565 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
566 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
568 // The response (tag -> reader) that we're receiving.
569 uint8_t *receivedResponse
= BigBuf_malloc(MAX_FRAME_SIZE
);
570 uint8_t *receivedResponsePar
= BigBuf_malloc(MAX_PARITY_SIZE
);
572 // The DMA buffer, used to stream samples from the FPGA
573 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
579 uint8_t *data
= dmaBuf
;
580 uint8_t previous_data
= 0;
583 bool TagIsActive
= FALSE
;
584 bool ReaderIsActive
= FALSE
;
586 // Set up the demodulator for tag -> reader responses.
587 DemodInit(receivedResponse
, receivedResponsePar
);
589 // Set up the demodulator for the reader -> tag commands
590 UartInit(receivedCmd
, receivedCmdPar
);
592 // Setup and start DMA.
593 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
);
595 // We won't start recording the frames that we acquire until we trigger;
596 // a good trigger condition to get started is probably when we see a
597 // response from the tag.
598 // triggered == FALSE -- to wait first for card
599 bool triggered
= !(param
& 0x03);
601 // And now we loop, receiving samples.
602 for(uint32_t rsamples
= 0; TRUE
; ) {
605 DbpString("cancelled by button");
612 int register readBufDataP
= data
- dmaBuf
;
613 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
;
614 if (readBufDataP
<= dmaBufDataP
){
615 dataLen
= dmaBufDataP
- readBufDataP
;
617 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
;
619 // test for length of buffer
620 if(dataLen
> maxDataLen
) {
621 maxDataLen
= dataLen
;
622 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
623 Dbprintf("blew circular buffer! dataLen=%d", dataLen
);
627 if(dataLen
< 1) continue;
629 // primary buffer was stopped( <-- we lost data!
630 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
631 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
632 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
633 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
635 // secondary buffer sets as primary, secondary buffer was stopped
636 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
637 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
638 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
643 if (rsamples
& 0x01) { // Need two samples to feed Miller and Manchester-Decoder
645 if(!TagIsActive
) { // no need to try decoding reader data if the tag is sending
646 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
647 if (MillerDecoding(readerdata
, (rsamples
-1)*4)) {
650 // check - if there is a short 7bit request from reader
651 if ((!triggered
) && (param
& 0x02) && (Uart
.len
== 1) && (Uart
.bitCount
== 7)) triggered
= TRUE
;
654 if (!LogTrace(receivedCmd
,
656 Uart
.startTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
657 Uart
.endTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
661 /* And ready to receive another command. */
663 /* And also reset the demod code, which might have been */
664 /* false-triggered by the commands from the reader. */
668 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
671 if(!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
672 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
673 if(ManchesterDecoding(tagdata
, 0, (rsamples
-1)*4)) {
676 if (!LogTrace(receivedResponse
,
678 Demod
.startTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
679 Demod
.endTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
683 if ((!triggered
) && (param
& 0x01)) triggered
= TRUE
;
685 // And ready to receive another response.
687 // And reset the Miller decoder including itS (now outdated) input buffer
688 UartInit(receivedCmd
, receivedCmdPar
);
692 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
696 previous_data
= *data
;
699 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
704 DbpString("COMMAND FINISHED");
707 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen
, Uart
.state
, Uart
.len
);
708 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart
.output
[0]);
712 //-----------------------------------------------------------------------------
713 // Prepare tag messages
714 //-----------------------------------------------------------------------------
715 static void CodeIso14443aAsTagPar(const uint8_t *cmd
, uint16_t len
, uint8_t *parity
)
719 // Correction bit, might be removed when not needed
724 ToSendStuffBit(1); // 1
730 ToSend
[++ToSendMax
] = SEC_D
;
731 LastProxToAirDuration
= 8 * ToSendMax
- 4;
733 for(uint16_t i
= 0; i
< len
; i
++) {
737 for(uint16_t j
= 0; j
< 8; j
++) {
739 ToSend
[++ToSendMax
] = SEC_D
;
741 ToSend
[++ToSendMax
] = SEC_E
;
746 // Get the parity bit
747 if (parity
[i
>>3] & (0x80>>(i
&0x0007))) {
748 ToSend
[++ToSendMax
] = SEC_D
;
749 LastProxToAirDuration
= 8 * ToSendMax
- 4;
751 ToSend
[++ToSendMax
] = SEC_E
;
752 LastProxToAirDuration
= 8 * ToSendMax
;
757 ToSend
[++ToSendMax
] = SEC_F
;
759 // Convert from last byte pos to length
763 static void CodeIso14443aAsTag(const uint8_t *cmd
, uint16_t len
)
765 uint8_t par
[MAX_PARITY_SIZE
];
767 GetParity(cmd
, len
, par
);
768 CodeIso14443aAsTagPar(cmd
, len
, par
);
772 static void Code4bitAnswerAsTag(uint8_t cmd
)
778 // Correction bit, might be removed when not needed
783 ToSendStuffBit(1); // 1
789 ToSend
[++ToSendMax
] = SEC_D
;
792 for(i
= 0; i
< 4; i
++) {
794 ToSend
[++ToSendMax
] = SEC_D
;
795 LastProxToAirDuration
= 8 * ToSendMax
- 4;
797 ToSend
[++ToSendMax
] = SEC_E
;
798 LastProxToAirDuration
= 8 * ToSendMax
;
804 ToSend
[++ToSendMax
] = SEC_F
;
806 // Convert from last byte pos to length
810 //-----------------------------------------------------------------------------
811 // Wait for commands from reader
812 // Stop when button is pressed
813 // Or return TRUE when command is captured
814 //-----------------------------------------------------------------------------
815 static int GetIso14443aCommandFromReader(uint8_t *received
, uint8_t *parity
, int *len
)
817 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
818 // only, since we are receiving, not transmitting).
819 // Signal field is off with the appropriate LED
821 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
823 // Now run a `software UART' on the stream of incoming samples.
824 UartInit(received
, parity
);
827 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
832 if(BUTTON_PRESS()) return FALSE
;
834 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
835 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
836 if(MillerDecoding(b
, 0)) {
844 static int EmSendCmd14443aRaw(uint8_t *resp
, uint16_t respLen
, bool correctionNeeded
);
845 int EmSend4bitEx(uint8_t resp
, bool correctionNeeded
);
846 int EmSend4bit(uint8_t resp
);
847 int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, bool correctionNeeded
, uint8_t *par
);
848 int EmSendCmdEx(uint8_t *resp
, uint16_t respLen
, bool correctionNeeded
);
849 int EmSendCmd(uint8_t *resp
, uint16_t respLen
);
850 int EmSendCmdPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
);
851 bool EmLogTrace(uint8_t *reader_data
, uint16_t reader_len
, uint32_t reader_StartTime
, uint32_t reader_EndTime
, uint8_t *reader_Parity
,
852 uint8_t *tag_data
, uint16_t tag_len
, uint32_t tag_StartTime
, uint32_t tag_EndTime
, uint8_t *tag_Parity
);
854 static uint8_t* free_buffer_pointer
;
861 uint32_t ProxToAirDuration
;
862 } tag_response_info_t
;
864 bool prepare_tag_modulation(tag_response_info_t
* response_info
, size_t max_buffer_size
) {
865 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
866 // This will need the following byte array for a modulation sequence
867 // 144 data bits (18 * 8)
870 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
871 // 1 just for the case
873 // 166 bytes, since every bit that needs to be send costs us a byte
877 // Prepare the tag modulation bits from the message
878 CodeIso14443aAsTag(response_info
->response
,response_info
->response_n
);
880 // Make sure we do not exceed the free buffer space
881 if (ToSendMax
> max_buffer_size
) {
882 Dbprintf("Out of memory, when modulating bits for tag answer:");
883 Dbhexdump(response_info
->response_n
,response_info
->response
,false);
887 // Copy the byte array, used for this modulation to the buffer position
888 memcpy(response_info
->modulation
,ToSend
,ToSendMax
);
890 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
891 response_info
->modulation_n
= ToSendMax
;
892 response_info
->ProxToAirDuration
= LastProxToAirDuration
;
898 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
899 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
900 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
901 // -> need 273 bytes buffer
902 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
904 bool prepare_allocated_tag_modulation(tag_response_info_t
* response_info
) {
905 // Retrieve and store the current buffer index
906 response_info
->modulation
= free_buffer_pointer
;
908 // Determine the maximum size we can use from our buffer
909 size_t max_buffer_size
= ALLOCATED_TAG_MODULATION_BUFFER_SIZE
;
911 // Forward the prepare tag modulation function to the inner function
912 if (prepare_tag_modulation(response_info
, max_buffer_size
)) {
913 // Update the free buffer offset
914 free_buffer_pointer
+= ToSendMax
;
921 //-----------------------------------------------------------------------------
922 // Main loop of simulated tag: receive commands from reader, decide what
923 // response to send, and send it.
924 //-----------------------------------------------------------------------------
925 void SimulateIso14443aTag(int tagType
, int uid_1st
, int uid_2nd
, byte_t
* data
)
929 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
930 uint8_t response1
[2];
933 case 1: { // MIFARE Classic
934 // Says: I am Mifare 1k - original line
939 case 2: { // MIFARE Ultralight
940 // Says: I am a stupid memory tag, no crypto
945 case 3: { // MIFARE DESFire
946 // Says: I am a DESFire tag, ph33r me
951 case 4: { // ISO/IEC 14443-4
952 // Says: I am a javacard (JCOP)
957 case 5: { // MIFARE TNP3XXX
964 Dbprintf("Error: unkown tagtype (%d)",tagType
);
969 // The second response contains the (mandatory) first 24 bits of the UID
970 uint8_t response2
[5] = {0x00};
972 // Check if the uid uses the (optional) part
973 uint8_t response2a
[5] = {0x00};
977 num_to_bytes(uid_1st
,3,response2
+1);
978 num_to_bytes(uid_2nd
,4,response2a
);
979 response2a
[4] = response2a
[0] ^ response2a
[1] ^ response2a
[2] ^ response2a
[3];
981 // Configure the ATQA and SAK accordingly
982 response1
[0] |= 0x40;
985 num_to_bytes(uid_1st
,4,response2
);
986 // Configure the ATQA and SAK accordingly
987 response1
[0] &= 0xBF;
991 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
992 response2
[4] = response2
[0] ^ response2
[1] ^ response2
[2] ^ response2
[3];
994 // Prepare the mandatory SAK (for 4 and 7 byte UID)
995 uint8_t response3
[3] = {0x00};
997 ComputeCrc14443(CRC_14443_A
, response3
, 1, &response3
[1], &response3
[2]);
999 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1000 uint8_t response3a
[3] = {0x00};
1001 response3a
[0] = sak
& 0xFB;
1002 ComputeCrc14443(CRC_14443_A
, response3a
, 1, &response3a
[1], &response3a
[2]);
1004 uint8_t response5
[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1005 uint8_t response6
[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1006 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1007 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1008 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1009 // TC(1) = 0x02: CID supported, NAD not supported
1010 ComputeCrc14443(CRC_14443_A
, response6
, 4, &response6
[4], &response6
[5]);
1012 #define TAG_RESPONSE_COUNT 7
1013 tag_response_info_t responses
[TAG_RESPONSE_COUNT
] = {
1014 { .response
= response1
, .response_n
= sizeof(response1
) }, // Answer to request - respond with card type
1015 { .response
= response2
, .response_n
= sizeof(response2
) }, // Anticollision cascade1 - respond with uid
1016 { .response
= response2a
, .response_n
= sizeof(response2a
) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1017 { .response
= response3
, .response_n
= sizeof(response3
) }, // Acknowledge select - cascade 1
1018 { .response
= response3a
, .response_n
= sizeof(response3a
) }, // Acknowledge select - cascade 2
1019 { .response
= response5
, .response_n
= sizeof(response5
) }, // Authentication answer (random nonce)
1020 { .response
= response6
, .response_n
= sizeof(response6
) }, // dummy ATS (pseudo-ATR), answer to RATS
1023 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1024 // Such a response is less time critical, so we can prepare them on the fly
1025 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1026 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1027 uint8_t dynamic_response_buffer
[DYNAMIC_RESPONSE_BUFFER_SIZE
];
1028 uint8_t dynamic_modulation_buffer
[DYNAMIC_MODULATION_BUFFER_SIZE
];
1029 tag_response_info_t dynamic_response_info
= {
1030 .response
= dynamic_response_buffer
,
1032 .modulation
= dynamic_modulation_buffer
,
1036 // We need to listen to the high-frequency, peak-detected path.
1037 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1039 BigBuf_free_keep_EM();
1041 // allocate buffers:
1042 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
1043 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
1044 free_buffer_pointer
= BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE
);
1050 // Prepare the responses of the anticollision phase
1051 // there will be not enough time to do this at the moment the reader sends it REQA
1052 for (size_t i
=0; i
<TAG_RESPONSE_COUNT
; i
++) {
1053 prepare_allocated_tag_modulation(&responses
[i
]);
1058 // To control where we are in the protocol
1062 // Just to allow some checks
1068 tag_response_info_t
* p_response
;
1072 // Clean receive command buffer
1073 if(!GetIso14443aCommandFromReader(receivedCmd
, receivedCmdPar
, &len
)) {
1074 DbpString("Button press");
1080 // Okay, look at the command now.
1082 if(receivedCmd
[0] == 0x26) { // Received a REQUEST
1083 p_response
= &responses
[0]; order
= 1;
1084 } else if(receivedCmd
[0] == 0x52) { // Received a WAKEUP
1085 p_response
= &responses
[0]; order
= 6;
1086 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x93) { // Received request for UID (cascade 1)
1087 p_response
= &responses
[1]; order
= 2;
1088 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x95) { // Received request for UID (cascade 2)
1089 p_response
= &responses
[2]; order
= 20;
1090 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x93) { // Received a SELECT (cascade 1)
1091 p_response
= &responses
[3]; order
= 3;
1092 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x95) { // Received a SELECT (cascade 2)
1093 p_response
= &responses
[4]; order
= 30;
1094 } else if(receivedCmd
[0] == 0x30) { // Received a (plain) READ
1095 EmSendCmdEx(data
+(4*receivedCmd
[1]),16,false);
1096 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1097 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1099 } else if(receivedCmd
[0] == 0x50) { // Received a HALT
1102 LogTrace(receivedCmd
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
1105 } else if(receivedCmd
[0] == 0x60 || receivedCmd
[0] == 0x61) { // Received an authentication request
1106 p_response
= &responses
[5]; order
= 7;
1107 } else if(receivedCmd
[0] == 0xE0) { // Received a RATS request
1108 if (tagType
== 1 || tagType
== 2) { // RATS not supported
1109 EmSend4bit(CARD_NACK_NA
);
1112 p_response
= &responses
[6]; order
= 70;
1114 } else if (order
== 7 && len
== 8) { // Received {nr] and {ar} (part of authentication)
1116 LogTrace(receivedCmd
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
1118 uint32_t nr
= bytes_to_num(receivedCmd
,4);
1119 uint32_t ar
= bytes_to_num(receivedCmd
+4,4);
1120 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr
,ar
);
1122 // Check for ISO 14443A-4 compliant commands, look at left nibble
1123 switch (receivedCmd
[0]) {
1126 case 0x0A: { // IBlock (command)
1127 dynamic_response_info
.response
[0] = receivedCmd
[0];
1128 dynamic_response_info
.response
[1] = 0x00;
1129 dynamic_response_info
.response
[2] = 0x90;
1130 dynamic_response_info
.response
[3] = 0x00;
1131 dynamic_response_info
.response_n
= 4;
1135 case 0x1B: { // Chaining command
1136 dynamic_response_info
.response
[0] = 0xaa | ((receivedCmd
[0]) & 1);
1137 dynamic_response_info
.response_n
= 2;
1142 dynamic_response_info
.response
[0] = receivedCmd
[0] ^ 0x11;
1143 dynamic_response_info
.response_n
= 2;
1147 memcpy(dynamic_response_info
.response
,"\xAB\x00",2);
1148 dynamic_response_info
.response_n
= 2;
1152 case 0xC2: { // Readers sends deselect command
1153 memcpy(dynamic_response_info
.response
,"\xCA\x00",2);
1154 dynamic_response_info
.response_n
= 2;
1158 // Never seen this command before
1160 LogTrace(receivedCmd
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
1162 Dbprintf("Received unknown command (len=%d):",len
);
1163 Dbhexdump(len
,receivedCmd
,false);
1165 dynamic_response_info
.response_n
= 0;
1169 if (dynamic_response_info
.response_n
> 0) {
1170 // Copy the CID from the reader query
1171 dynamic_response_info
.response
[1] = receivedCmd
[1];
1173 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1174 AppendCrc14443a(dynamic_response_info
.response
,dynamic_response_info
.response_n
);
1175 dynamic_response_info
.response_n
+= 2;
1177 if (prepare_tag_modulation(&dynamic_response_info
,DYNAMIC_MODULATION_BUFFER_SIZE
) == false) {
1178 Dbprintf("Error preparing tag response");
1180 LogTrace(receivedCmd
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
1184 p_response
= &dynamic_response_info
;
1188 // Count number of wakeups received after a halt
1189 if(order
== 6 && lastorder
== 5) { happened
++; }
1191 // Count number of other messages after a halt
1192 if(order
!= 6 && lastorder
== 5) { happened2
++; }
1194 if(cmdsRecvd
> 999) {
1195 DbpString("1000 commands later...");
1200 if (p_response
!= NULL
) {
1201 EmSendCmd14443aRaw(p_response
->modulation
, p_response
->modulation_n
, receivedCmd
[0] == 0x52);
1202 // do the tracing for the previous reader request and this tag answer:
1203 uint8_t par
[MAX_PARITY_SIZE
];
1204 GetParity(p_response
->response
, p_response
->response_n
, par
);
1206 EmLogTrace(Uart
.output
,
1208 Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
,
1209 Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
,
1211 p_response
->response
,
1212 p_response
->response_n
,
1213 LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_TAG
,
1214 (LastTimeProxToAirStart
+ p_response
->ProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_TAG
,
1219 Dbprintf("Trace Full. Simulation stopped.");
1224 Dbprintf("%x %x %x", happened
, happened2
, cmdsRecvd
);
1226 BigBuf_free_keep_EM();
1230 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1231 // of bits specified in the delay parameter.
1232 void PrepareDelayedTransfer(uint16_t delay
)
1234 uint8_t bitmask
= 0;
1235 uint8_t bits_to_shift
= 0;
1236 uint8_t bits_shifted
= 0;
1240 for (uint16_t i
= 0; i
< delay
; i
++) {
1241 bitmask
|= (0x01 << i
);
1243 ToSend
[ToSendMax
++] = 0x00;
1244 for (uint16_t i
= 0; i
< ToSendMax
; i
++) {
1245 bits_to_shift
= ToSend
[i
] & bitmask
;
1246 ToSend
[i
] = ToSend
[i
] >> delay
;
1247 ToSend
[i
] = ToSend
[i
] | (bits_shifted
<< (8 - delay
));
1248 bits_shifted
= bits_to_shift
;
1254 //-------------------------------------------------------------------------------------
1255 // Transmit the command (to the tag) that was placed in ToSend[].
1256 // Parameter timing:
1257 // if NULL: transfer at next possible time, taking into account
1258 // request guard time and frame delay time
1259 // if == 0: transfer immediately and return time of transfer
1260 // if != 0: delay transfer until time specified
1261 //-------------------------------------------------------------------------------------
1262 static void TransmitFor14443a(const uint8_t *cmd
, uint16_t len
, uint32_t *timing
)
1265 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_MOD
);
1267 uint32_t ThisTransferTime
= 0;
1270 if(*timing
== 0) { // Measure time
1271 *timing
= (GetCountSspClk() + 8) & 0xfffffff8;
1273 PrepareDelayedTransfer(*timing
& 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1275 if(MF_DBGLEVEL
>= 4 && GetCountSspClk() >= (*timing
& 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1276 while(GetCountSspClk() < (*timing
& 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1277 LastTimeProxToAirStart
= *timing
;
1279 ThisTransferTime
= ((MAX(NextTransferTime
, GetCountSspClk()) & 0xfffffff8) + 8);
1280 while(GetCountSspClk() < ThisTransferTime
);
1281 LastTimeProxToAirStart
= ThisTransferTime
;
1285 AT91C_BASE_SSC
->SSC_THR
= SEC_Y
;
1289 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1290 AT91C_BASE_SSC
->SSC_THR
= cmd
[c
];
1298 NextTransferTime
= MAX(NextTransferTime
, LastTimeProxToAirStart
+ REQUEST_GUARD_TIME
);
1302 //-----------------------------------------------------------------------------
1303 // Prepare reader command (in bits, support short frames) to send to FPGA
1304 //-----------------------------------------------------------------------------
1305 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd
, uint16_t bits
, const uint8_t *parity
)
1313 // Start of Communication (Seq. Z)
1314 ToSend
[++ToSendMax
] = SEC_Z
;
1315 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1318 size_t bytecount
= nbytes(bits
);
1319 // Generate send structure for the data bits
1320 for (i
= 0; i
< bytecount
; i
++) {
1321 // Get the current byte to send
1323 size_t bitsleft
= MIN((bits
-(i
*8)),8);
1325 for (j
= 0; j
< bitsleft
; j
++) {
1328 ToSend
[++ToSendMax
] = SEC_X
;
1329 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1334 ToSend
[++ToSendMax
] = SEC_Z
;
1335 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1338 ToSend
[++ToSendMax
] = SEC_Y
;
1345 // Only transmit parity bit if we transmitted a complete byte
1346 if (j
== 8 && parity
!= NULL
) {
1347 // Get the parity bit
1348 if (parity
[i
>>3] & (0x80 >> (i
&0x0007))) {
1350 ToSend
[++ToSendMax
] = SEC_X
;
1351 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1356 ToSend
[++ToSendMax
] = SEC_Z
;
1357 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1360 ToSend
[++ToSendMax
] = SEC_Y
;
1367 // End of Communication: Logic 0 followed by Sequence Y
1370 ToSend
[++ToSendMax
] = SEC_Z
;
1371 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1374 ToSend
[++ToSendMax
] = SEC_Y
;
1377 ToSend
[++ToSendMax
] = SEC_Y
;
1379 // Convert to length of command:
1383 //-----------------------------------------------------------------------------
1384 // Prepare reader command to send to FPGA
1385 //-----------------------------------------------------------------------------
1386 void CodeIso14443aAsReaderPar(const uint8_t *cmd
, uint16_t len
, const uint8_t *parity
)
1388 CodeIso14443aBitsAsReaderPar(cmd
, len
*8, parity
);
1392 //-----------------------------------------------------------------------------
1393 // Wait for commands from reader
1394 // Stop when button is pressed (return 1) or field was gone (return 2)
1395 // Or return 0 when command is captured
1396 //-----------------------------------------------------------------------------
1397 static int EmGetCmd(uint8_t *received
, uint16_t *len
, uint8_t *parity
)
1401 uint32_t timer
= 0, vtime
= 0;
1405 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1406 // only, since we are receiving, not transmitting).
1407 // Signal field is off with the appropriate LED
1409 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1411 // Set ADC to read field strength
1412 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_SWRST
;
1413 AT91C_BASE_ADC
->ADC_MR
=
1414 ADC_MODE_PRESCALE(63) |
1415 ADC_MODE_STARTUP_TIME(1) |
1416 ADC_MODE_SAMPLE_HOLD_TIME(15);
1417 AT91C_BASE_ADC
->ADC_CHER
= ADC_CHANNEL(ADC_CHAN_HF
);
1419 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
;
1421 // Now run a 'software UART' on the stream of incoming samples.
1422 UartInit(received
, parity
);
1425 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1430 if (BUTTON_PRESS()) return 1;
1432 // test if the field exists
1433 if (AT91C_BASE_ADC
->ADC_SR
& ADC_END_OF_CONVERSION(ADC_CHAN_HF
)) {
1435 analogAVG
+= AT91C_BASE_ADC
->ADC_CDR
[ADC_CHAN_HF
];
1436 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
;
1437 if (analogCnt
>= 32) {
1438 if ((MAX_ADC_HF_VOLTAGE
* (analogAVG
/ analogCnt
) >> 10) < MF_MINFIELDV
) {
1439 vtime
= GetTickCount();
1440 if (!timer
) timer
= vtime
;
1441 // 50ms no field --> card to idle state
1442 if (vtime
- timer
> 50) return 2;
1444 if (timer
) timer
= 0;
1450 // receive and test the miller decoding
1451 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1452 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1453 if(MillerDecoding(b
, 0)) {
1463 static int EmSendCmd14443aRaw(uint8_t *resp
, uint16_t respLen
, bool correctionNeeded
)
1467 uint32_t ThisTransferTime
;
1469 // Modulate Manchester
1470 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_MOD
);
1472 // include correction bit if necessary
1473 if (Uart
.parityBits
& 0x01) {
1474 correctionNeeded
= TRUE
;
1476 if(correctionNeeded
) {
1477 // 1236, so correction bit needed
1483 // clear receiving shift register and holding register
1484 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1485 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1486 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1487 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1489 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1490 for (uint16_t j
= 0; j
< 5; j
++) { // allow timeout - better late than never
1491 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1492 if (AT91C_BASE_SSC
->SSC_RHR
) break;
1495 while ((ThisTransferTime
= GetCountSspClk()) & 0x00000007);
1498 AT91C_BASE_SSC
->SSC_THR
= SEC_F
;
1501 for(; i
< respLen
; ) {
1502 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1503 AT91C_BASE_SSC
->SSC_THR
= resp
[i
++];
1504 FpgaSendQueueDelay
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1507 if(BUTTON_PRESS()) {
1512 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1513 uint8_t fpga_queued_bits
= FpgaSendQueueDelay
>> 3;
1514 for (i
= 0; i
<= fpga_queued_bits
/8 + 1; ) {
1515 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1516 AT91C_BASE_SSC
->SSC_THR
= SEC_F
;
1517 FpgaSendQueueDelay
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1522 LastTimeProxToAirStart
= ThisTransferTime
+ (correctionNeeded
?8:0);
1527 int EmSend4bitEx(uint8_t resp
, bool correctionNeeded
){
1528 Code4bitAnswerAsTag(resp
);
1529 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
, correctionNeeded
);
1530 // do the tracing for the previous reader request and this tag answer:
1532 GetParity(&resp
, 1, par
);
1533 EmLogTrace(Uart
.output
,
1535 Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
,
1536 Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
,
1540 LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_TAG
,
1541 (LastTimeProxToAirStart
+ LastProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_TAG
,
1546 int EmSend4bit(uint8_t resp
){
1547 return EmSend4bitEx(resp
, false);
1550 int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, bool correctionNeeded
, uint8_t *par
){
1551 CodeIso14443aAsTagPar(resp
, respLen
, par
);
1552 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
, correctionNeeded
);
1553 // do the tracing for the previous reader request and this tag answer:
1554 EmLogTrace(Uart
.output
,
1556 Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
,
1557 Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
,
1561 LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_TAG
,
1562 (LastTimeProxToAirStart
+ LastProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_TAG
,
1567 int EmSendCmdEx(uint8_t *resp
, uint16_t respLen
, bool correctionNeeded
){
1568 uint8_t par
[MAX_PARITY_SIZE
];
1569 GetParity(resp
, respLen
, par
);
1570 return EmSendCmdExPar(resp
, respLen
, correctionNeeded
, par
);
1573 int EmSendCmd(uint8_t *resp
, uint16_t respLen
){
1574 uint8_t par
[MAX_PARITY_SIZE
];
1575 GetParity(resp
, respLen
, par
);
1576 return EmSendCmdExPar(resp
, respLen
, false, par
);
1579 int EmSendCmdPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
){
1580 return EmSendCmdExPar(resp
, respLen
, false, par
);
1583 bool EmLogTrace(uint8_t *reader_data
, uint16_t reader_len
, uint32_t reader_StartTime
, uint32_t reader_EndTime
, uint8_t *reader_Parity
,
1584 uint8_t *tag_data
, uint16_t tag_len
, uint32_t tag_StartTime
, uint32_t tag_EndTime
, uint8_t *tag_Parity
)
1587 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1588 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1589 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1590 uint16_t reader_modlen
= reader_EndTime
- reader_StartTime
;
1591 uint16_t approx_fdt
= tag_StartTime
- reader_EndTime
;
1592 uint16_t exact_fdt
= (approx_fdt
- 20 + 32)/64 * 64 + 20;
1593 reader_EndTime
= tag_StartTime
- exact_fdt
;
1594 reader_StartTime
= reader_EndTime
- reader_modlen
;
1595 if (!LogTrace(reader_data
, reader_len
, reader_StartTime
, reader_EndTime
, reader_Parity
, TRUE
)) {
1597 } else return(!LogTrace(tag_data
, tag_len
, tag_StartTime
, tag_EndTime
, tag_Parity
, FALSE
));
1603 //-----------------------------------------------------------------------------
1604 // Wait a certain time for tag response
1605 // If a response is captured return TRUE
1606 // If it takes too long return FALSE
1607 //-----------------------------------------------------------------------------
1608 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse
, uint8_t *receivedResponsePar
, uint16_t offset
)
1612 // Set FPGA mode to "reader listen mode", no modulation (listen
1613 // only, since we are receiving, not transmitting).
1614 // Signal field is on with the appropriate LED
1616 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_LISTEN
);
1618 // Now get the answer from the card
1619 DemodInit(receivedResponse
, receivedResponsePar
);
1622 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1628 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1629 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1630 if(ManchesterDecoding(b
, offset
, 0)) {
1631 NextTransferTime
= MAX(NextTransferTime
, Demod
.endTime
- (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/16 + FRAME_DELAY_TIME_PICC_TO_PCD
);
1633 } else if (c
++ > iso14a_timeout
&& Demod
.state
== DEMOD_UNSYNCD
) {
1641 void ReaderTransmitBitsPar(uint8_t* frame
, uint16_t bits
, uint8_t *par
, uint32_t *timing
)
1643 CodeIso14443aBitsAsReaderPar(frame
, bits
, par
);
1645 // Send command to tag
1646 TransmitFor14443a(ToSend
, ToSendMax
, timing
);
1650 // Log reader command in trace buffer
1652 LogTrace(frame
, nbytes(bits
), LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_READER
, (LastTimeProxToAirStart
+ LastProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_READER
, par
, TRUE
);
1657 void ReaderTransmitPar(uint8_t* frame
, uint16_t len
, uint8_t *par
, uint32_t *timing
)
1659 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1663 void ReaderTransmitBits(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1665 // Generate parity and redirect
1666 uint8_t par
[MAX_PARITY_SIZE
];
1667 GetParity(frame
, len
/8, par
);
1668 ReaderTransmitBitsPar(frame
, len
, par
, timing
);
1672 void ReaderTransmit(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1674 // Generate parity and redirect
1675 uint8_t par
[MAX_PARITY_SIZE
];
1676 GetParity(frame
, len
, par
);
1677 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1680 int ReaderReceiveOffset(uint8_t* receivedAnswer
, uint16_t offset
, uint8_t *parity
)
1682 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, offset
)) return FALSE
;
1684 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, FALSE
);
1689 int ReaderReceive(uint8_t *receivedAnswer
, uint8_t *parity
)
1691 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, 0)) return FALSE
;
1693 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, FALSE
);
1698 /* performs iso14443a anticollision procedure
1699 * fills the uid pointer unless NULL
1700 * fills resp_data unless NULL */
1701 int iso14443a_select_card(byte_t
*uid_ptr
, iso14a_card_select_t
*p_hi14a_card
, uint32_t *cuid_ptr
) {
1702 uint8_t wupa
[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1703 uint8_t sel_all
[] = { 0x93,0x20 };
1704 uint8_t sel_uid
[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1705 uint8_t rats
[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1706 uint8_t resp
[MAX_FRAME_SIZE
]; // theoretically. A usual RATS will be much smaller
1707 uint8_t resp_par
[MAX_PARITY_SIZE
];
1709 size_t uid_resp_len
;
1711 uint8_t sak
= 0x04; // cascade uid
1712 int cascade_level
= 0;
1715 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1716 ReaderTransmitBitsPar(wupa
,7,0, NULL
);
1719 if(!ReaderReceive(resp
, resp_par
)) return 0;
1722 memcpy(p_hi14a_card
->atqa
, resp
, 2);
1723 p_hi14a_card
->uidlen
= 0;
1724 memset(p_hi14a_card
->uid
,0,10);
1729 memset(uid_ptr
,0,10);
1732 // check for proprietary anticollision:
1733 if ((resp
[0] & 0x1F) == 0) {
1737 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1738 // which case we need to make a cascade 2 request and select - this is a long UID
1739 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1740 for(; sak
& 0x04; cascade_level
++) {
1741 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1742 sel_uid
[0] = sel_all
[0] = 0x93 + cascade_level
* 2;
1745 ReaderTransmit(sel_all
, sizeof(sel_all
), NULL
);
1746 if (!ReaderReceive(resp
, resp_par
)) return 0;
1748 if (Demod
.collisionPos
) { // we had a collision and need to construct the UID bit by bit
1749 memset(uid_resp
, 0, 4);
1750 uint16_t uid_resp_bits
= 0;
1751 uint16_t collision_answer_offset
= 0;
1752 // anti-collision-loop:
1753 while (Demod
.collisionPos
) {
1754 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod
.collisionPos
);
1755 for (uint16_t i
= collision_answer_offset
; i
< Demod
.collisionPos
; i
++, uid_resp_bits
++) { // add valid UID bits before collision point
1756 uint16_t UIDbit
= (resp
[i
/8] >> (i
% 8)) & 0x01;
1757 uid_resp
[uid_resp_bits
/ 8] |= UIDbit
<< (uid_resp_bits
% 8);
1759 uid_resp
[uid_resp_bits
/8] |= 1 << (uid_resp_bits
% 8); // next time select the card(s) with a 1 in the collision position
1761 // construct anticollosion command:
1762 sel_uid
[1] = ((2 + uid_resp_bits
/8) << 4) | (uid_resp_bits
& 0x07); // length of data in bytes and bits
1763 for (uint16_t i
= 0; i
<= uid_resp_bits
/8; i
++) {
1764 sel_uid
[2+i
] = uid_resp
[i
];
1766 collision_answer_offset
= uid_resp_bits
%8;
1767 ReaderTransmitBits(sel_uid
, 16 + uid_resp_bits
, NULL
);
1768 if (!ReaderReceiveOffset(resp
, collision_answer_offset
, resp_par
)) return 0;
1770 // finally, add the last bits and BCC of the UID
1771 for (uint16_t i
= collision_answer_offset
; i
< (Demod
.len
-1)*8; i
++, uid_resp_bits
++) {
1772 uint16_t UIDbit
= (resp
[i
/8] >> (i
%8)) & 0x01;
1773 uid_resp
[uid_resp_bits
/8] |= UIDbit
<< (uid_resp_bits
% 8);
1776 } else { // no collision, use the response to SELECT_ALL as current uid
1777 memcpy(uid_resp
, resp
, 4);
1781 // calculate crypto UID. Always use last 4 Bytes.
1783 *cuid_ptr
= bytes_to_num(uid_resp
, 4);
1786 // Construct SELECT UID command
1787 sel_uid
[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1788 memcpy(sel_uid
+2, uid_resp
, 4); // the UID
1789 sel_uid
[6] = sel_uid
[2] ^ sel_uid
[3] ^ sel_uid
[4] ^ sel_uid
[5]; // calculate and add BCC
1790 AppendCrc14443a(sel_uid
, 7); // calculate and add CRC
1791 ReaderTransmit(sel_uid
, sizeof(sel_uid
), NULL
);
1794 if (!ReaderReceive(resp
, resp_par
)) return 0;
1797 // Test if more parts of the uid are coming
1798 if ((sak
& 0x04) /* && uid_resp[0] == 0x88 */) {
1799 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1800 // http://www.nxp.com/documents/application_note/AN10927.pdf
1801 uid_resp
[0] = uid_resp
[1];
1802 uid_resp
[1] = uid_resp
[2];
1803 uid_resp
[2] = uid_resp
[3];
1809 memcpy(uid_ptr
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1813 memcpy(p_hi14a_card
->uid
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1814 p_hi14a_card
->uidlen
+= uid_resp_len
;
1819 p_hi14a_card
->sak
= sak
;
1820 p_hi14a_card
->ats_len
= 0;
1823 // non iso14443a compliant tag
1824 if( (sak
& 0x20) == 0) return 2;
1826 // Request for answer to select
1827 AppendCrc14443a(rats
, 2);
1828 ReaderTransmit(rats
, sizeof(rats
), NULL
);
1830 if (!(len
= ReaderReceive(resp
, resp_par
))) return 0;
1834 memcpy(p_hi14a_card
->ats
, resp
, sizeof(p_hi14a_card
->ats
));
1835 p_hi14a_card
->ats_len
= len
;
1838 // reset the PCB block number
1839 iso14_pcb_blocknum
= 0;
1841 // set default timeout based on ATS
1842 iso14a_set_ATS_timeout(resp
);
1847 void iso14443a_setup(uint8_t fpga_minor_mode
) {
1848 FpgaDownloadAndGo(FPGA_BITSTREAM_HF
);
1849 // Set up the synchronous serial port
1851 // connect Demodulated Signal to ADC:
1852 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
1854 // Signal field is on with the appropriate LED
1855 if (fpga_minor_mode
== FPGA_HF_ISO14443A_READER_MOD
1856 || fpga_minor_mode
== FPGA_HF_ISO14443A_READER_LISTEN
) {
1861 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| fpga_minor_mode
);
1868 NextTransferTime
= 2*DELAY_ARM2AIR_AS_READER
;
1869 iso14a_set_timeout(1050); // 10ms default
1872 int iso14_apdu(uint8_t *cmd
, uint16_t cmd_len
, void *data
) {
1873 uint8_t parity
[MAX_PARITY_SIZE
];
1874 uint8_t real_cmd
[cmd_len
+4];
1875 real_cmd
[0] = 0x0a; //I-Block
1876 // put block number into the PCB
1877 real_cmd
[0] |= iso14_pcb_blocknum
;
1878 real_cmd
[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1879 memcpy(real_cmd
+2, cmd
, cmd_len
);
1880 AppendCrc14443a(real_cmd
,cmd_len
+2);
1882 ReaderTransmit(real_cmd
, cmd_len
+4, NULL
);
1883 size_t len
= ReaderReceive(data
, parity
);
1884 uint8_t *data_bytes
= (uint8_t *) data
;
1886 return 0; //DATA LINK ERROR
1887 // if we received an I- or R(ACK)-Block with a block number equal to the
1888 // current block number, toggle the current block number
1889 else if (len
>= 4 // PCB+CID+CRC = 4 bytes
1890 && ((data_bytes
[0] & 0xC0) == 0 // I-Block
1891 || (data_bytes
[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1892 && (data_bytes
[0] & 0x01) == iso14_pcb_blocknum
) // equal block numbers
1894 iso14_pcb_blocknum
^= 1;
1900 //-----------------------------------------------------------------------------
1901 // Read an ISO 14443a tag. Send out commands and store answers.
1903 //-----------------------------------------------------------------------------
1904 void ReaderIso14443a(UsbCommand
*c
)
1906 iso14a_command_t param
= c
->arg
[0];
1907 uint8_t *cmd
= c
->d
.asBytes
;
1908 size_t len
= c
->arg
[1] & 0xffff;
1909 size_t lenbits
= c
->arg
[1] >> 16;
1910 uint32_t timeout
= c
->arg
[2];
1912 byte_t buf
[USB_CMD_DATA_SIZE
];
1913 uint8_t par
[MAX_PARITY_SIZE
];
1915 if(param
& ISO14A_CONNECT
) {
1921 if(param
& ISO14A_REQUEST_TRIGGER
) {
1922 iso14a_set_trigger(TRUE
);
1925 if(param
& ISO14A_CONNECT
) {
1926 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN
);
1927 if(!(param
& ISO14A_NO_SELECT
)) {
1928 iso14a_card_select_t
*card
= (iso14a_card_select_t
*)buf
;
1929 arg0
= iso14443a_select_card(NULL
,card
,NULL
);
1930 cmd_send(CMD_ACK
,arg0
,card
->uidlen
,0,buf
,sizeof(iso14a_card_select_t
));
1934 if(param
& ISO14A_SET_TIMEOUT
) {
1935 iso14a_set_timeout(timeout
);
1938 if(param
& ISO14A_APDU
) {
1939 arg0
= iso14_apdu(cmd
, len
, buf
);
1940 cmd_send(CMD_ACK
,arg0
,0,0,buf
,sizeof(buf
));
1943 if(param
& ISO14A_RAW
) {
1944 if(param
& ISO14A_APPEND_CRC
) {
1945 if(param
& ISO14A_TOPAZMODE
) {
1946 AppendCrc14443b(cmd
,len
);
1948 AppendCrc14443a(cmd
,len
);
1951 if (lenbits
) lenbits
+= 16;
1953 if(lenbits
>0) { // want to send a specific number of bits (e.g. short commands)
1954 if(param
& ISO14A_TOPAZMODE
) {
1955 int bits_to_send
= lenbits
;
1957 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 7), NULL
, NULL
); // first byte is always short (7bits) and no parity
1959 while (bits_to_send
> 0) {
1960 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 8), NULL
, NULL
); // following bytes are 8 bit and no parity
1964 GetParity(cmd
, lenbits
/8, par
);
1965 ReaderTransmitBitsPar(cmd
, lenbits
, par
, NULL
); // bytes are 8 bit with odd parity
1967 } else { // want to send complete bytes only
1968 if(param
& ISO14A_TOPAZMODE
) {
1970 ReaderTransmitBitsPar(&cmd
[i
++], 7, NULL
, NULL
); // first byte: 7 bits, no paritiy
1972 ReaderTransmitBitsPar(&cmd
[i
++], 8, NULL
, NULL
); // following bytes: 8 bits, no paritiy
1975 ReaderTransmit(cmd
,len
, NULL
); // 8 bits, odd parity
1978 arg0
= ReaderReceive(buf
, par
);
1979 cmd_send(CMD_ACK
,arg0
,0,0,buf
,sizeof(buf
));
1982 if(param
& ISO14A_REQUEST_TRIGGER
) {
1983 iso14a_set_trigger(FALSE
);
1986 if(param
& ISO14A_NO_DISCONNECT
) {
1990 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1995 // Determine the distance between two nonces.
1996 // Assume that the difference is small, but we don't know which is first.
1997 // Therefore try in alternating directions.
1998 int32_t dist_nt(uint32_t nt1
, uint32_t nt2
) {
2001 uint32_t nttmp1
, nttmp2
;
2003 if (nt1
== nt2
) return 0;
2008 for (i
= 1; i
< 32768; i
++) {
2009 nttmp1
= prng_successor(nttmp1
, 1);
2010 if (nttmp1
== nt2
) return i
;
2011 nttmp2
= prng_successor(nttmp2
, 1);
2012 if (nttmp2
== nt1
) return -i
;
2015 return(-99999); // either nt1 or nt2 are invalid nonces
2019 //-----------------------------------------------------------------------------
2020 // Recover several bits of the cypher stream. This implements (first stages of)
2021 // the algorithm described in "The Dark Side of Security by Obscurity and
2022 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2023 // (article by Nicolas T. Courtois, 2009)
2024 //-----------------------------------------------------------------------------
2025 void ReaderMifare(bool first_try
)
2028 uint8_t mf_auth
[] = { 0x60,0x00,0xf5,0x7b };
2029 uint8_t mf_nr_ar
[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2030 static uint8_t mf_nr_ar3
;
2032 uint8_t receivedAnswer
[MAX_MIFARE_FRAME_SIZE
];
2033 uint8_t receivedAnswerPar
[MAX_MIFARE_PARITY_SIZE
];
2036 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2039 // free eventually allocated BigBuf memory. We want all for tracing.
2046 uint8_t par
[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2047 static byte_t par_low
= 0;
2049 uint8_t uid
[10] ={0};
2053 uint32_t previous_nt
= 0;
2054 static uint32_t nt_attacked
= 0;
2055 byte_t par_list
[8] = {0x00};
2056 byte_t ks_list
[8] = {0x00};
2058 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2059 static uint32_t sync_time
;
2060 static int32_t sync_cycles
;
2061 int catch_up_cycles
= 0;
2062 int last_catch_up
= 0;
2063 uint16_t elapsed_prng_sequences
;
2064 uint16_t consecutive_resyncs
= 0;
2069 sync_time
= GetCountSspClk() & 0xfffffff8;
2070 sync_cycles
= PRNG_SEQUENCE_LENGTH
; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2075 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2077 mf_nr_ar
[3] = mf_nr_ar3
;
2086 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2087 #define MAX_SYNC_TRIES 32
2088 #define NUM_DEBUG_INFOS 8 // per strategy
2089 #define MAX_STRATEGY 3
2090 uint16_t unexpected_random
= 0;
2091 uint16_t sync_tries
= 0;
2092 int16_t debug_info_nr
= -1;
2093 uint16_t strategy
= 0;
2094 int32_t debug_info
[MAX_STRATEGY
][NUM_DEBUG_INFOS
];
2095 uint32_t select_time
;
2098 for(uint16_t i
= 0; TRUE
; i
++) {
2103 // Test if the action was cancelled
2104 if(BUTTON_PRESS()) {
2109 if (strategy
== 2) {
2110 // test with additional hlt command
2112 int len
= mifare_sendcmd_short(NULL
, false, 0x50, 0x00, receivedAnswer
, receivedAnswerPar
, &halt_time
);
2113 if (len
&& MF_DBGLEVEL
>= 3) {
2114 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len
);
2118 if (strategy
== 3) {
2119 // test with FPGA power off/on
2120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2122 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2126 if(!iso14443a_select_card(uid
, NULL
, &cuid
)) {
2127 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Can't select card");
2130 select_time
= GetCountSspClk();
2132 elapsed_prng_sequences
= 1;
2133 if (debug_info_nr
== -1) {
2134 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
+ catch_up_cycles
;
2135 catch_up_cycles
= 0;
2137 // if we missed the sync time already, advance to the next nonce repeat
2138 while(GetCountSspClk() > sync_time
) {
2139 elapsed_prng_sequences
++;
2140 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
;
2143 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2144 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2146 // collect some information on tag nonces for debugging:
2147 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2148 if (strategy
== 0) {
2149 // nonce distances at fixed time after card select:
2150 sync_time
= select_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2151 } else if (strategy
== 1) {
2152 // nonce distances at fixed time between authentications:
2153 sync_time
= sync_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2154 } else if (strategy
== 2) {
2155 // nonce distances at fixed time after halt:
2156 sync_time
= halt_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2158 // nonce_distances at fixed time after power on
2159 sync_time
= DEBUG_FIXED_SYNC_CYCLES
;
2161 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2164 // Receive the (4 Byte) "random" nonce
2165 if (!ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2166 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2171 nt
= bytes_to_num(receivedAnswer
, 4);
2173 // Transmit reader nonce with fake par
2174 ReaderTransmitPar(mf_nr_ar
, sizeof(mf_nr_ar
), par
, NULL
);
2176 if (first_try
&& previous_nt
&& !nt_attacked
) { // we didn't calibrate our clock yet
2177 int nt_distance
= dist_nt(previous_nt
, nt
);
2178 if (nt_distance
== 0) {
2181 if (nt_distance
== -99999) { // invalid nonce received
2182 unexpected_random
++;
2183 if (unexpected_random
> MAX_UNEXPECTED_RANDOM
) {
2184 isOK
= -3; // Card has an unpredictable PRNG. Give up
2187 continue; // continue trying...
2190 if (++sync_tries
> MAX_SYNC_TRIES
) {
2191 if (strategy
> MAX_STRATEGY
|| MF_DBGLEVEL
< 3) {
2192 isOK
= -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2194 } else { // continue for a while, just to collect some debug info
2195 debug_info
[strategy
][debug_info_nr
] = nt_distance
;
2197 if (debug_info_nr
== NUM_DEBUG_INFOS
) {
2204 sync_cycles
= (sync_cycles
- nt_distance
/elapsed_prng_sequences
);
2205 if (sync_cycles
<= 0) {
2206 sync_cycles
+= PRNG_SEQUENCE_LENGTH
;
2208 if (MF_DBGLEVEL
>= 3) {
2209 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i
, nt_distance
, elapsed_prng_sequences
, sync_cycles
);
2215 if ((nt
!= nt_attacked
) && nt_attacked
) { // we somehow lost sync. Try to catch up again...
2216 catch_up_cycles
= -dist_nt(nt_attacked
, nt
);
2217 if (catch_up_cycles
== 99999) { // invalid nonce received. Don't resync on that one.
2218 catch_up_cycles
= 0;
2221 catch_up_cycles
/= elapsed_prng_sequences
;
2222 if (catch_up_cycles
== last_catch_up
) {
2223 consecutive_resyncs
++;
2226 last_catch_up
= catch_up_cycles
;
2227 consecutive_resyncs
= 0;
2229 if (consecutive_resyncs
< 3) {
2230 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i
, -catch_up_cycles
, consecutive_resyncs
);
2233 sync_cycles
= sync_cycles
+ catch_up_cycles
;
2234 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i
, -catch_up_cycles
, sync_cycles
);
2236 catch_up_cycles
= 0;
2237 consecutive_resyncs
= 0;
2242 consecutive_resyncs
= 0;
2244 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2245 if (ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2246 catch_up_cycles
= 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2249 par_low
= par
[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2253 if(led_on
) LED_B_ON(); else LED_B_OFF();
2255 par_list
[nt_diff
] = SwapBits(par
[0], 8);
2256 ks_list
[nt_diff
] = receivedAnswer
[0] ^ 0x05;
2258 // Test if the information is complete
2259 if (nt_diff
== 0x07) {
2264 nt_diff
= (nt_diff
+ 1) & 0x07;
2265 mf_nr_ar
[3] = (mf_nr_ar
[3] & 0x1F) | (nt_diff
<< 5);
2268 if (nt_diff
== 0 && first_try
)
2271 if (par
[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2276 par
[0] = ((par
[0] & 0x1F) + 1) | par_low
;
2282 mf_nr_ar
[3] &= 0x1F;
2285 if (MF_DBGLEVEL
>= 3) {
2286 for (uint16_t i
= 0; i
<= MAX_STRATEGY
; i
++) {
2287 for(uint16_t j
= 0; j
< NUM_DEBUG_INFOS
; j
++) {
2288 Dbprintf("collected debug info[%d][%d] = %d", i
, j
, debug_info
[i
][j
]);
2295 memcpy(buf
+ 0, uid
, 4);
2296 num_to_bytes(nt
, 4, buf
+ 4);
2297 memcpy(buf
+ 8, par_list
, 8);
2298 memcpy(buf
+ 16, ks_list
, 8);
2299 memcpy(buf
+ 24, mf_nr_ar
, 4);
2301 cmd_send(CMD_ACK
, isOK
, 0, 0, buf
, 28);
2304 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2323 *MIFARE 1K simulate.
2326 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2327 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2328 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2329 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2330 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2332 void Mifare1ksim(uint8_t flags
, uint8_t exitAfterNReads
, uint8_t arg2
, uint8_t *datain
)
2334 int cardSTATE
= MFEMUL_NOFIELD
;
2336 int vHf
= 0; // in mV
2338 uint32_t selTimer
= 0;
2339 uint32_t authTimer
= 0;
2341 uint8_t cardWRBL
= 0;
2342 uint8_t cardAUTHSC
= 0;
2343 uint8_t cardAUTHKEY
= 0xff; // no authentication
2344 uint32_t cardRr
= 0;
2346 //uint32_t rn_enc = 0;
2348 uint32_t cardINTREG
= 0;
2349 uint8_t cardINTBLOCK
= 0;
2350 struct Crypto1State mpcs
= {0, 0};
2351 struct Crypto1State
*pcs
;
2353 uint32_t numReads
= 0;//Counts numer of times reader read a block
2354 uint8_t receivedCmd
[MAX_MIFARE_FRAME_SIZE
];
2355 uint8_t receivedCmd_par
[MAX_MIFARE_PARITY_SIZE
];
2356 uint8_t response
[MAX_MIFARE_FRAME_SIZE
];
2357 uint8_t response_par
[MAX_MIFARE_PARITY_SIZE
];
2359 uint8_t rATQA
[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2360 uint8_t rUIDBCC1
[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2361 uint8_t rUIDBCC2
[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2362 uint8_t rSAK
[] = {0x08, 0xb6, 0xdd};
2363 uint8_t rSAK1
[] = {0x04, 0xda, 0x17};
2365 uint8_t rAUTH_NT
[] = {0x01, 0x02, 0x03, 0x04};
2366 uint8_t rAUTH_AT
[] = {0x00, 0x00, 0x00, 0x00};
2368 //Here, we collect UID,sector,keytype,NT,AR,NR,NT2,AR2,NR2
2369 // This can be used in a reader-only attack.
2370 // (it can also be retrieved via 'hf 14a list', but hey...
2372 //allow collecting up to 4 sets of nonces to allow recovery of 4 keys (2 keyA & 2 keyB)
2373 // must be set in multiples of 2 (for 1 keyA and 1 keyB)
2374 #define ATTACK_KEY_COUNT 4
2375 nonces_t ar_nr_resp
[ATTACK_KEY_COUNT
];
2376 memset(ar_nr_resp
, 0x00, sizeof(ar_nr_resp
));
2378 uint8_t ar_nr_collected
[ATTACK_KEY_COUNT
];
2379 memset(ar_nr_collected
, 0x00, sizeof(ar_nr_collected
));
2380 // Authenticate response - nonce
2381 uint32_t nonce
= bytes_to_num(rAUTH_NT
, 4);
2383 //-- Determine the UID
2384 // Can be set from emulator memory, incoming data
2385 // and can be 7 or 4 bytes long
2386 if (flags
& FLAG_4B_UID_IN_DATA
)
2388 // 4B uid comes from data-portion of packet
2389 memcpy(rUIDBCC1
,datain
,4);
2390 rUIDBCC1
[4] = rUIDBCC1
[0] ^ rUIDBCC1
[1] ^ rUIDBCC1
[2] ^ rUIDBCC1
[3];
2392 } else if (flags
& FLAG_7B_UID_IN_DATA
) {
2393 // 7B uid comes from data-portion of packet
2394 memcpy(&rUIDBCC1
[1],datain
,3);
2395 memcpy(rUIDBCC2
, datain
+3, 4);
2398 // get UID from emul memory
2399 emlGetMemBt(receivedCmd
, 7, 1);
2400 _7BUID
= !(receivedCmd
[0] == 0x00);
2401 if (!_7BUID
) { // ---------- 4BUID
2402 emlGetMemBt(rUIDBCC1
, 0, 4);
2403 } else { // ---------- 7BUID
2404 emlGetMemBt(&rUIDBCC1
[1], 0, 3);
2405 emlGetMemBt(rUIDBCC2
, 3, 4);
2410 * Regardless of what method was used to set the UID, set fifth byte and modify
2411 * the ATQA for 4 or 7-byte UID
2413 rUIDBCC1
[4] = rUIDBCC1
[0] ^ rUIDBCC1
[1] ^ rUIDBCC1
[2] ^ rUIDBCC1
[3];
2417 rUIDBCC1
[4] = rUIDBCC1
[0] ^ rUIDBCC1
[1] ^ rUIDBCC1
[2] ^ rUIDBCC1
[3];
2418 rUIDBCC2
[4] = rUIDBCC2
[0] ^ rUIDBCC2
[1] ^ rUIDBCC2
[2] ^ rUIDBCC2
[3];
2421 if (MF_DBGLEVEL
>= 1) {
2423 Dbprintf("4B UID: %02x%02x%02x%02x",
2424 rUIDBCC1
[0], rUIDBCC1
[1], rUIDBCC1
[2], rUIDBCC1
[3]);
2426 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2427 rUIDBCC1
[0], rUIDBCC1
[1], rUIDBCC1
[2], rUIDBCC1
[3],
2428 rUIDBCC2
[0], rUIDBCC2
[1] ,rUIDBCC2
[2], rUIDBCC2
[3]);
2432 // We need to listen to the high-frequency, peak-detected path.
2433 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
2435 // free eventually allocated BigBuf memory but keep Emulator Memory
2436 BigBuf_free_keep_EM();
2443 bool finished
= FALSE
;
2444 while (!BUTTON_PRESS() && !finished
) {
2447 // find reader field
2448 if (cardSTATE
== MFEMUL_NOFIELD
) {
2449 vHf
= (MAX_ADC_HF_VOLTAGE
* AvgAdc(ADC_CHAN_HF
)) >> 10;
2450 if (vHf
> MF_MINFIELDV
) {
2451 cardSTATE_TO_IDLE();
2455 if(cardSTATE
== MFEMUL_NOFIELD
) continue;
2459 res
= EmGetCmd(receivedCmd
, &len
, receivedCmd_par
);
2460 if (res
== 2) { //Field is off!
2461 cardSTATE
= MFEMUL_NOFIELD
;
2464 } else if (res
== 1) {
2465 break; //return value 1 means button press
2468 // REQ or WUP request in ANY state and WUP in HALTED state
2469 if (len
== 1 && ((receivedCmd
[0] == 0x26 && cardSTATE
!= MFEMUL_HALTED
) || receivedCmd
[0] == 0x52)) {
2470 selTimer
= GetTickCount();
2471 EmSendCmdEx(rATQA
, sizeof(rATQA
), (receivedCmd
[0] == 0x52));
2472 cardSTATE
= MFEMUL_SELECT1
;
2474 // init crypto block
2477 crypto1_destroy(pcs
);
2482 switch (cardSTATE
) {
2483 case MFEMUL_NOFIELD
:
2486 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2489 case MFEMUL_SELECT1
:{
2491 if (len
== 2 && (receivedCmd
[0] == 0x93 && receivedCmd
[1] == 0x20)) {
2492 if (MF_DBGLEVEL
>= 4) Dbprintf("SELECT ALL received");
2493 EmSendCmd(rUIDBCC1
, sizeof(rUIDBCC1
));
2497 if (MF_DBGLEVEL
>= 4 && len
== 9 && receivedCmd
[0] == 0x93 && receivedCmd
[1] == 0x70 )
2499 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd
[2],receivedCmd
[3],receivedCmd
[4],receivedCmd
[5]);
2503 (receivedCmd
[0] == 0x93 && receivedCmd
[1] == 0x70 && memcmp(&receivedCmd
[2], rUIDBCC1
, 4) == 0)) {
2504 EmSendCmd(_7BUID
?rSAK1
:rSAK
, _7BUID
?sizeof(rSAK1
):sizeof(rSAK
));
2505 cuid
= bytes_to_num(rUIDBCC1
, 4);
2507 cardSTATE
= MFEMUL_WORK
;
2509 if (MF_DBGLEVEL
>= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer
);
2512 cardSTATE
= MFEMUL_SELECT2
;
2520 cardSTATE_TO_IDLE();
2521 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2525 uint32_t ar
= bytes_to_num(receivedCmd
, 4);
2526 uint32_t nr
= bytes_to_num(&receivedCmd
[4], 4);
2528 //Collect AR/NR per key/sector
2529 if(flags
& FLAG_NR_AR_ATTACK
) {
2530 for (uint8_t i
= 0; i
< ATTACK_KEY_COUNT
; i
++) {
2531 if(cardAUTHKEY
> 0 && i
< (ATTACK_KEY_COUNT
/2) ) {
2532 i
=ATTACK_KEY_COUNT
/2; //keyB skip to keyB
2533 } else if (cardAUTHKEY
== 0 && i
== ATTACK_KEY_COUNT
/2) {
2534 break; //should not get here - quit
2536 // if first auth for sector, or matches sector of previous auth
2537 if ( ar_nr_collected
[i
]==0 || (cardAUTHSC
== ar_nr_resp
[i
].sector
&& ar_nr_collected
[i
] > 0) ) {
2538 if(ar_nr_collected
[i
] < 2) {
2539 if(ar_nr_resp
[ar_nr_collected
[i
]].ar
!= ar
)
2540 {// Avoid duplicates... probably not necessary, ar should vary.
2541 if (ar_nr_collected
[i
]==0) {
2542 ar_nr_resp
[i
].cuid
= cuid
;
2543 ar_nr_resp
[i
].sector
= cardAUTHSC
;
2544 ar_nr_resp
[i
].nonce
= nonce
;
2545 ar_nr_resp
[i
].ar
= ar
;
2546 ar_nr_resp
[i
].nr
= nr
;
2548 ar_nr_resp
[i
].ar2
= ar
;
2549 ar_nr_resp
[i
].nr2
= nr
;
2551 ar_nr_collected
[i
]++;
2560 crypto1_word(pcs
, ar
, 1);
2561 cardRr
= nr
^ crypto1_word(pcs
, 0, 0);
2564 if (cardRr
!= prng_successor(nonce
, 64)){
2565 if (MF_DBGLEVEL
>= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2566 cardAUTHSC
, cardAUTHKEY
== 0 ? 'A' : 'B',
2567 cardRr
, prng_successor(nonce
, 64));
2568 // Shouldn't we respond anything here?
2569 // Right now, we don't nack or anything, which causes the
2570 // reader to do a WUPA after a while. /Martin
2571 // -- which is the correct response. /piwi
2572 cardSTATE_TO_IDLE();
2573 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2578 ans
= prng_successor(nonce
, 96) ^ crypto1_word(pcs
, 0, 0);
2580 num_to_bytes(ans
, 4, rAUTH_AT
);
2582 EmSendCmd(rAUTH_AT
, sizeof(rAUTH_AT
));
2584 cardSTATE
= MFEMUL_WORK
;
2585 if (MF_DBGLEVEL
>= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2586 cardAUTHSC
, cardAUTHKEY
== 0 ? 'A' : 'B',
2587 GetTickCount() - authTimer
);
2590 case MFEMUL_SELECT2
:{
2592 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2595 if (len
== 2 && (receivedCmd
[0] == 0x95 && receivedCmd
[1] == 0x20)) {
2596 EmSendCmd(rUIDBCC2
, sizeof(rUIDBCC2
));
2602 (receivedCmd
[0] == 0x95 && receivedCmd
[1] == 0x70 && memcmp(&receivedCmd
[2], rUIDBCC2
, 4) == 0)) {
2603 EmSendCmd(rSAK
, sizeof(rSAK
));
2604 cuid
= bytes_to_num(rUIDBCC2
, 4);
2605 cardSTATE
= MFEMUL_WORK
;
2607 if (MF_DBGLEVEL
>= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer
);
2611 // i guess there is a command). go into the work state.
2613 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2616 cardSTATE
= MFEMUL_WORK
;
2618 //intentional fall-through to the next case-stmt
2623 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2627 bool encrypted_data
= (cardAUTHKEY
!= 0xFF) ;
2629 if(encrypted_data
) {
2631 mf_crypto1_decrypt(pcs
, receivedCmd
, len
);
2634 if (len
== 4 && (receivedCmd
[0] == 0x60 || receivedCmd
[0] == 0x61)) {
2635 authTimer
= GetTickCount();
2636 cardAUTHSC
= receivedCmd
[1] / 4; // received block num
2637 cardAUTHKEY
= receivedCmd
[0] - 0x60;
2638 crypto1_destroy(pcs
);//Added by martin
2639 crypto1_create(pcs
, emlGetKey(cardAUTHSC
, cardAUTHKEY
));
2641 if (!encrypted_data
) { // first authentication
2642 if (MF_DBGLEVEL
>= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd
[1] ,receivedCmd
[1],cardAUTHKEY
);
2644 crypto1_word(pcs
, cuid
^ nonce
, 0);//Update crypto state
2645 num_to_bytes(nonce
, 4, rAUTH_AT
); // Send nonce
2646 } else { // nested authentication
2647 if (MF_DBGLEVEL
>= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd
[1] ,receivedCmd
[1],cardAUTHKEY
);
2648 ans
= nonce
^ crypto1_word(pcs
, cuid
^ nonce
, 0);
2649 num_to_bytes(ans
, 4, rAUTH_AT
);
2652 EmSendCmd(rAUTH_AT
, sizeof(rAUTH_AT
));
2653 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2654 cardSTATE
= MFEMUL_AUTH1
;
2658 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2659 // BUT... ACK --> NACK
2660 if (len
== 1 && receivedCmd
[0] == CARD_ACK
) {
2661 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2665 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2666 if (len
== 1 && receivedCmd
[0] == CARD_NACK_NA
) {
2667 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_ACK
));
2672 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2676 if(receivedCmd
[0] == 0x30 // read block
2677 || receivedCmd
[0] == 0xA0 // write block
2678 || receivedCmd
[0] == 0xC0 // inc
2679 || receivedCmd
[0] == 0xC1 // dec
2680 || receivedCmd
[0] == 0xC2 // restore
2681 || receivedCmd
[0] == 0xB0) { // transfer
2682 if (receivedCmd
[1] >= 16 * 4) {
2683 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2684 if (MF_DBGLEVEL
>= 2) Dbprintf("Reader tried to operate (0x%02x) on out of range block: %d (0x%02x), nacking",receivedCmd
[0],receivedCmd
[1],receivedCmd
[1]);
2688 if (receivedCmd
[1] / 4 != cardAUTHSC
) {
2689 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2690 if (MF_DBGLEVEL
>= 2) Dbprintf("Reader tried to operate (0x%02x) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd
[0],receivedCmd
[1],cardAUTHSC
);
2695 if (receivedCmd
[0] == 0x30) {
2696 if (MF_DBGLEVEL
>= 4) {
2697 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd
[1],receivedCmd
[1]);
2699 emlGetMem(response
, receivedCmd
[1], 1);
2700 AppendCrc14443a(response
, 16);
2701 mf_crypto1_encrypt(pcs
, response
, 18, response_par
);
2702 EmSendCmdPar(response
, 18, response_par
);
2704 if(exitAfterNReads
> 0 && numReads
== exitAfterNReads
) {
2705 Dbprintf("%d reads done, exiting", numReads
);
2711 if (receivedCmd
[0] == 0xA0) {
2712 if (MF_DBGLEVEL
>= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd
[1],receivedCmd
[1]);
2713 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_ACK
));
2714 cardSTATE
= MFEMUL_WRITEBL2
;
2715 cardWRBL
= receivedCmd
[1];
2718 // increment, decrement, restore
2719 if (receivedCmd
[0] == 0xC0 || receivedCmd
[0] == 0xC1 || receivedCmd
[0] == 0xC2) {
2720 if (MF_DBGLEVEL
>= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd
[0],receivedCmd
[1],receivedCmd
[1]);
2721 if (emlCheckValBl(receivedCmd
[1])) {
2722 if (MF_DBGLEVEL
>= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2723 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2726 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_ACK
));
2727 if (receivedCmd
[0] == 0xC1)
2728 cardSTATE
= MFEMUL_INTREG_INC
;
2729 if (receivedCmd
[0] == 0xC0)
2730 cardSTATE
= MFEMUL_INTREG_DEC
;
2731 if (receivedCmd
[0] == 0xC2)
2732 cardSTATE
= MFEMUL_INTREG_REST
;
2733 cardWRBL
= receivedCmd
[1];
2737 if (receivedCmd
[0] == 0xB0) {
2738 if (MF_DBGLEVEL
>= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd
[0],receivedCmd
[1],receivedCmd
[1]);
2739 if (emlSetValBl(cardINTREG
, cardINTBLOCK
, receivedCmd
[1]))
2740 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2742 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_ACK
));
2746 if (receivedCmd
[0] == 0x50 && receivedCmd
[1] == 0x00) {
2749 cardSTATE
= MFEMUL_HALTED
;
2750 if (MF_DBGLEVEL
>= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer
);
2751 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2755 if (receivedCmd
[0] == 0xe0) {//RATS
2756 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2759 // command not allowed
2760 if (MF_DBGLEVEL
>= 4) Dbprintf("Received command not allowed, nacking");
2761 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2764 case MFEMUL_WRITEBL2
:{
2766 mf_crypto1_decrypt(pcs
, receivedCmd
, len
);
2767 emlSetMem(receivedCmd
, cardWRBL
, 1);
2768 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_ACK
));
2769 cardSTATE
= MFEMUL_WORK
;
2771 cardSTATE_TO_IDLE();
2772 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2777 case MFEMUL_INTREG_INC
:{
2778 mf_crypto1_decrypt(pcs
, receivedCmd
, len
);
2779 memcpy(&ans
, receivedCmd
, 4);
2780 if (emlGetValBl(&cardINTREG
, &cardINTBLOCK
, cardWRBL
)) {
2781 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2782 cardSTATE_TO_IDLE();
2785 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2786 cardINTREG
= cardINTREG
+ ans
;
2787 cardSTATE
= MFEMUL_WORK
;
2790 case MFEMUL_INTREG_DEC
:{
2791 mf_crypto1_decrypt(pcs
, receivedCmd
, len
);
2792 memcpy(&ans
, receivedCmd
, 4);
2793 if (emlGetValBl(&cardINTREG
, &cardINTBLOCK
, cardWRBL
)) {
2794 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2795 cardSTATE_TO_IDLE();
2798 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2799 cardINTREG
= cardINTREG
- ans
;
2800 cardSTATE
= MFEMUL_WORK
;
2803 case MFEMUL_INTREG_REST
:{
2804 mf_crypto1_decrypt(pcs
, receivedCmd
, len
);
2805 memcpy(&ans
, receivedCmd
, 4);
2806 if (emlGetValBl(&cardINTREG
, &cardINTBLOCK
, cardWRBL
)) {
2807 EmSend4bit(mf_crypto1_encrypt4bit(pcs
, CARD_NACK_NA
));
2808 cardSTATE_TO_IDLE();
2811 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, TRUE
);
2812 cardSTATE
= MFEMUL_WORK
;
2818 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2821 if(flags
& FLAG_NR_AR_ATTACK
&& MF_DBGLEVEL
>= 1)
2823 for ( uint8_t i
= 0; i
< ATTACK_KEY_COUNT
; i
++) {
2824 if (ar_nr_collected
[i
] == 2) {
2825 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i
<ATTACK_KEY_COUNT
/2) ? "keyA" : "keyB", ar_nr_resp
[i
].sector
);
2826 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2827 ar_nr_resp
[i
].cuid
, //UID
2828 ar_nr_resp
[i
].nonce
, //NT
2829 ar_nr_resp
[i
].ar
, //AR1
2830 ar_nr_resp
[i
].nr
, //NR1
2831 ar_nr_resp
[i
].ar2
, //AR2
2832 ar_nr_resp
[i
].nr2
//NR2
2837 if (MF_DBGLEVEL
>= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing
, BigBuf_get_traceLen());
2839 if(flags
& FLAG_INTERACTIVE
)// Interactive mode flag, means we need to send ACK
2841 //May just aswell send the collected ar_nr in the response aswell
2842 cmd_send(CMD_ACK
,CMD_SIMULATE_MIFARE_CARD
,0,0,&ar_nr_resp
,sizeof(ar_nr_resp
));
2849 //-----------------------------------------------------------------------------
2852 //-----------------------------------------------------------------------------
2853 void RAMFUNC
SniffMifare(uint8_t param
) {
2855 // bit 0 - trigger from first card answer
2856 // bit 1 - trigger from first reader 7-bit request
2858 // C(red) A(yellow) B(green)
2860 // init trace buffer
2864 // The command (reader -> tag) that we're receiving.
2865 // The length of a received command will in most cases be no more than 18 bytes.
2866 // So 32 should be enough!
2867 uint8_t receivedCmd
[MAX_MIFARE_FRAME_SIZE
];
2868 uint8_t receivedCmdPar
[MAX_MIFARE_PARITY_SIZE
];
2869 // The response (tag -> reader) that we're receiving.
2870 uint8_t receivedResponse
[MAX_MIFARE_FRAME_SIZE
];
2871 uint8_t receivedResponsePar
[MAX_MIFARE_PARITY_SIZE
];
2873 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
2875 // free eventually allocated BigBuf memory
2877 // allocate the DMA buffer, used to stream samples from the FPGA
2878 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
2879 uint8_t *data
= dmaBuf
;
2880 uint8_t previous_data
= 0;
2883 bool ReaderIsActive
= FALSE
;
2884 bool TagIsActive
= FALSE
;
2886 // Set up the demodulator for tag -> reader responses.
2887 DemodInit(receivedResponse
, receivedResponsePar
);
2889 // Set up the demodulator for the reader -> tag commands
2890 UartInit(receivedCmd
, receivedCmdPar
);
2892 // Setup for the DMA.
2893 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2900 // And now we loop, receiving samples.
2901 for(uint32_t sniffCounter
= 0; TRUE
; ) {
2903 if(BUTTON_PRESS()) {
2904 DbpString("cancelled by button");
2911 if ((sniffCounter
& 0x0000FFFF) == 0) { // from time to time
2912 // check if a transaction is completed (timeout after 2000ms).
2913 // if yes, stop the DMA transfer and send what we have so far to the client
2914 if (MfSniffSend(2000)) {
2915 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2919 ReaderIsActive
= FALSE
;
2920 TagIsActive
= FALSE
;
2921 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2925 int register readBufDataP
= data
- dmaBuf
; // number of bytes we have processed so far
2926 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
; // number of bytes already transferred
2927 if (readBufDataP
<= dmaBufDataP
){ // we are processing the same block of data which is currently being transferred
2928 dataLen
= dmaBufDataP
- readBufDataP
; // number of bytes still to be processed
2930 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
; // number of bytes still to be processed
2932 // test for length of buffer
2933 if(dataLen
> maxDataLen
) { // we are more behind than ever...
2934 maxDataLen
= dataLen
;
2935 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
2936 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen
);
2940 if(dataLen
< 1) continue;
2942 // primary buffer was stopped ( <-- we lost data!
2943 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
2944 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
2945 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
2946 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
2948 // secondary buffer sets as primary, secondary buffer was stopped
2949 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
2950 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
2951 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
2956 if (sniffCounter
& 0x01) {
2958 if(!TagIsActive
) { // no need to try decoding tag data if the reader is sending
2959 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
2960 if(MillerDecoding(readerdata
, (sniffCounter
-1)*4)) {
2962 if (MfSniffLogic(receivedCmd
, Uart
.len
, Uart
.parity
, Uart
.bitCount
, TRUE
)) break;
2964 /* And ready to receive another command. */
2965 UartInit(receivedCmd
, receivedCmdPar
);
2967 /* And also reset the demod code */
2970 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
2973 if(!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending
2974 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
2975 if(ManchesterDecoding(tagdata
, 0, (sniffCounter
-1)*4)) {
2978 if (MfSniffLogic(receivedResponse
, Demod
.len
, Demod
.parity
, Demod
.bitCount
, FALSE
)) break;
2980 // And ready to receive another response.
2982 // And reset the Miller decoder including its (now outdated) input buffer
2983 UartInit(receivedCmd
, receivedCmdPar
);
2985 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
2989 previous_data
= *data
;
2992 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
2998 DbpString("COMMAND FINISHED");
3000 FpgaDisableSscDma();
3003 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen
, Uart
.state
, Uart
.len
);