]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ADD: added the ioprox checksum test to IOdemodFSK
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "usb_cdc.h"
20
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76 /* blank r/w tag data stream
77 ...0000000000000000 01111111
78 1010101010101010101010101010101010101010101010101010101010101010
79 0011010010100001
80 01111111
81 101010101010101[0]000...
82
83 [5555fe852c5555555555555555fe0000]
84 */
85 void ReadTItag(void)
86 {
87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
94
95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
178 if (shift3 & (1<<15) ) {
179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x",
206 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
207 if (crc != (shift2&0xffff)) {
208 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
209 } else {
210 DbpString("Info: CRC is good");
211 }
212 }
213 }
214
215 void WriteTIbyte(uint8_t b)
216 {
217 int i = 0;
218
219 // modulate 8 bits out to the antenna
220 for (i=0; i<8; i++)
221 {
222 if (b&(1<<i)) {
223 // stop modulating antenna
224 LOW(GPIO_SSC_DOUT);
225 SpinDelayUs(1000);
226 // modulate antenna
227 HIGH(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 } else {
230 // stop modulating antenna
231 LOW(GPIO_SSC_DOUT);
232 SpinDelayUs(300);
233 // modulate antenna
234 HIGH(GPIO_SSC_DOUT);
235 SpinDelayUs(1700);
236 }
237 }
238 }
239
240 void AcquireTiType(void)
241 {
242 int i, j, n;
243 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
244 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
245 #define TIBUFLEN 1250
246
247 // clear buffer
248 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
249 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
250
251 // Set up the synchronous serial port
252 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
253 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
254
255 // steal this pin from the SSP and use it to control the modulation
256 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
257 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
258
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
261
262 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
263 // 48/2 = 24 MHz clock must be divided by 12
264 AT91C_BASE_SSC->SSC_CMR = 12;
265
266 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
267 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
268 AT91C_BASE_SSC->SSC_TCMR = 0;
269 AT91C_BASE_SSC->SSC_TFMR = 0;
270
271 LED_D_ON();
272
273 // modulate antenna
274 HIGH(GPIO_SSC_DOUT);
275
276 // Charge TI tag for 50ms.
277 SpinDelay(50);
278
279 // stop modulating antenna and listen
280 LOW(GPIO_SSC_DOUT);
281
282 LED_D_OFF();
283
284 i = 0;
285 for(;;) {
286 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
287 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
288 i++; if(i >= TIBUFLEN) break;
289 }
290 WDT_HIT();
291 }
292
293 // return stolen pin to SSP
294 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
295 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
296
297 char *dest = (char *)BigBuf_get_addr();
298 n = TIBUFLEN*32;
299 // unpack buffer
300 for (i=TIBUFLEN-1; i>=0; i--) {
301 for (j=0; j<32; j++) {
302 if(BigBuf[i] & (1 << j)) {
303 dest[--n] = 1;
304 } else {
305 dest[--n] = -1;
306 }
307 }
308 }
309 }
310
311 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
312 // if crc provided, it will be written with the data verbatim (even if bogus)
313 // if not provided a valid crc will be computed from the data and written.
314 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
315 {
316 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
317 if(crc == 0) {
318 crc = update_crc16(crc, (idlo)&0xff);
319 crc = update_crc16(crc, (idlo>>8)&0xff);
320 crc = update_crc16(crc, (idlo>>16)&0xff);
321 crc = update_crc16(crc, (idlo>>24)&0xff);
322 crc = update_crc16(crc, (idhi)&0xff);
323 crc = update_crc16(crc, (idhi>>8)&0xff);
324 crc = update_crc16(crc, (idhi>>16)&0xff);
325 crc = update_crc16(crc, (idhi>>24)&0xff);
326 }
327 Dbprintf("Writing to tag: %x%08x, crc=%x",
328 (unsigned int) idhi, (unsigned int) idlo, crc);
329
330 // TI tags charge at 134.2Khz
331 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
332 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
333 // connects to SSP_DIN and the SSP_DOUT logic level controls
334 // whether we're modulating the antenna (high)
335 // or listening to the antenna (low)
336 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
337 LED_A_ON();
338
339 // steal this pin from the SSP and use it to control the modulation
340 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
341 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
342
343 // writing algorithm:
344 // a high bit consists of a field off for 1ms and field on for 1ms
345 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
346 // initiate a charge time of 50ms (field on) then immediately start writing bits
347 // start by writing 0xBB (keyword) and 0xEB (password)
348 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
349 // finally end with 0x0300 (write frame)
350 // all data is sent lsb firts
351 // finish with 15ms programming time
352
353 // modulate antenna
354 HIGH(GPIO_SSC_DOUT);
355 SpinDelay(50); // charge time
356
357 WriteTIbyte(0xbb); // keyword
358 WriteTIbyte(0xeb); // password
359 WriteTIbyte( (idlo )&0xff );
360 WriteTIbyte( (idlo>>8 )&0xff );
361 WriteTIbyte( (idlo>>16)&0xff );
362 WriteTIbyte( (idlo>>24)&0xff );
363 WriteTIbyte( (idhi )&0xff );
364 WriteTIbyte( (idhi>>8 )&0xff );
365 WriteTIbyte( (idhi>>16)&0xff );
366 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
367 WriteTIbyte( (crc )&0xff ); // crc lo
368 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
369 WriteTIbyte(0x00); // write frame lo
370 WriteTIbyte(0x03); // write frame hi
371 HIGH(GPIO_SSC_DOUT);
372 SpinDelay(50); // programming time
373
374 LED_A_OFF();
375
376 // get TI tag data into the buffer
377 AcquireTiType();
378
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
380 DbpString("Now use tiread to check");
381 }
382
383 void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
384 {
385 int i;
386 uint8_t *tab = BigBuf_get_addr();
387
388 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
389 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
390
391 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
392
393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
395
396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
398
399 i = 0;
400 for(;;) {
401 //wait until SSC_CLK goes HIGH
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS() || usb_poll()) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409 if (ledcontrol)
410 LED_D_ON();
411
412 if(tab[i])
413 OPEN_COIL();
414 else
415 SHORT_COIL();
416
417 if (ledcontrol)
418 LED_D_OFF();
419 //wait until SSC_CLK goes LOW
420 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
421 if(BUTTON_PRESS()) {
422 DbpString("Stopped");
423 return;
424 }
425 WDT_HIT();
426 }
427
428 i++;
429 if(i == period) {
430
431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
438 }
439
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor, int t0)
442 {
443 }
444
445 // compose fc/8 fc/10 waveform (FSK2)
446 static void fc(int c, int *n)
447 {
448 uint8_t *dest = BigBuf_get_addr();
449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
462
463 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
477 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 }
491 }
492 }
493 // compose fc/X fc/Y waveform (FSKx)
494 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
495 {
496 uint8_t *dest = BigBuf_get_addr();
497 uint8_t halfFC = fc/2;
498 uint8_t wavesPerClock = clock/fc;
499 uint8_t mod = clock % fc; //modifier
500 uint8_t modAdj = fc/mod; //how often to apply modifier
501 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
502 // loop through clock - step field clock
503 for (uint8_t idx=0; idx < wavesPerClock; idx++){
504 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
506 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
507 *n += fc;
508 }
509 if (mod>0) (*modCnt)++;
510 if ((mod>0) && modAdjOk){ //fsk2
511 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
512 memset(dest+(*n), 0, fc-halfFC);
513 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
514 *n += fc;
515 }
516 }
517 if (mod>0 && !modAdjOk){ //fsk1
518 memset(dest+(*n), 0, mod-(mod/2));
519 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
520 *n += mod;
521 }
522 }
523
524 // prepare a waveform pattern in the buffer based on the ID given then
525 // simulate a HID tag until the button is pressed
526 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
527 {
528 int n=0, i=0;
529 /*
530 HID tag bitstream format
531 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
532 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
533 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
534 A fc8 is inserted before every 4 bits
535 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
536 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
537 */
538
539 if (hi>0xFFF) {
540 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
541 return;
542 }
543 fc(0,&n);
544 // special start of frame marker containing invalid bit sequences
545 fc(8, &n); fc(8, &n); // invalid
546 fc(8, &n); fc(10, &n); // logical 0
547 fc(10, &n); fc(10, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549
550 WDT_HIT();
551 // manchester encode bits 43 to 32
552 for (i=11; i>=0; i--) {
553 if ((i%4)==3) fc(0,&n);
554 if ((hi>>i)&1) {
555 fc(10, &n); fc(8, &n); // low-high transition
556 } else {
557 fc(8, &n); fc(10, &n); // high-low transition
558 }
559 }
560
561 WDT_HIT();
562 // manchester encode bits 31 to 0
563 for (i=31; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((lo>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 if (ledcontrol)
573 LED_A_ON();
574 SimulateTagLowFrequency(n, 0, ledcontrol);
575
576 if (ledcontrol)
577 LED_A_OFF();
578 }
579
580 // prepare a waveform pattern in the buffer based on the ID given then
581 // simulate a FSK tag until the button is pressed
582 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
583 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
584 {
585 int ledcontrol=1;
586 int n=0, i=0;
587 uint8_t fcHigh = arg1 >> 8;
588 uint8_t fcLow = arg1 & 0xFF;
589 uint16_t modCnt = 0;
590 uint8_t clk = arg2 & 0xFF;
591 uint8_t invert = (arg2 >> 8) & 1;
592
593 for (i=0; i<size; i++){
594 if (BitStream[i] == invert){
595 fcAll(fcLow, &n, clk, &modCnt);
596 } else {
597 fcAll(fcHigh, &n, clk, &modCnt);
598 }
599 }
600 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
601 /*Dbprintf("DEBUG: First 32:");
602 uint8_t *dest = BigBuf_get_addr();
603 i=0;
604 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
605 i+=16;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 */
608 if (ledcontrol)
609 LED_A_ON();
610
611 SimulateTagLowFrequency(n, 0, ledcontrol);
612
613 if (ledcontrol)
614 LED_A_OFF();
615 }
616
617 // compose ask waveform for one bit(ASK)
618 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
619 {
620 uint8_t *dest = BigBuf_get_addr();
621 uint8_t halfClk = clock/2;
622 // c = current bit 1 or 0
623 if (manchester==1){
624 memset(dest+(*n), c, halfClk);
625 memset(dest+(*n) + halfClk, c^1, halfClk);
626 } else {
627 memset(dest+(*n), c, clock);
628 }
629 *n += clock;
630 }
631
632 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
633 {
634 uint8_t *dest = BigBuf_get_addr();
635 uint8_t halfClk = clock/2;
636 if (c){
637 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
638 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
639 } else {
640 memset(dest+(*n), c ^ *phase, clock);
641 *phase ^= 1;
642 }
643
644 }
645
646 // args clock, ask/man or askraw, invert, transmission separator
647 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
648 {
649 int ledcontrol = 1;
650 int n=0, i=0;
651 uint8_t clk = (arg1 >> 8) & 0xFF;
652 uint8_t encoding = arg1 & 1;
653 uint8_t separator = arg2 & 1;
654 uint8_t invert = (arg2 >> 8) & 1;
655
656 if (encoding==2){ //biphase
657 uint8_t phase=0;
658 for (i=0; i<size; i++){
659 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
660 }
661 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
662 for (i=0; i<size; i++){
663 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
664 }
665 }
666 } else { // ask/manchester || ask/raw
667 for (i=0; i<size; i++){
668 askSimBit(BitStream[i]^invert, &n, clk, encoding);
669 }
670 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
671 for (i=0; i<size; i++){
672 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
673 }
674 }
675 }
676
677 if (separator==1) Dbprintf("sorry but separator option not yet available");
678
679 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
680 //DEBUG
681 //Dbprintf("First 32:");
682 //uint8_t *dest = BigBuf_get_addr();
683 //i=0;
684 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
685 //i+=16;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687
688 if (ledcontrol)
689 LED_A_ON();
690
691 SimulateTagLowFrequency(n, 0, ledcontrol);
692
693 if (ledcontrol)
694 LED_A_OFF();
695 }
696
697 //carrier can be 2,4 or 8
698 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
699 {
700 uint8_t *dest = BigBuf_get_addr();
701 uint8_t halfWave = waveLen/2;
702 //uint8_t idx;
703 int i = 0;
704 if (phaseChg){
705 // write phase change
706 memset(dest+(*n), *curPhase^1, halfWave);
707 memset(dest+(*n) + halfWave, *curPhase, halfWave);
708 *n += waveLen;
709 *curPhase ^= 1;
710 i += waveLen;
711 }
712 //write each normal clock wave for the clock duration
713 for (; i < clk; i+=waveLen){
714 memset(dest+(*n), *curPhase, halfWave);
715 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
716 *n += waveLen;
717 }
718 }
719
720 // args clock, carrier, invert,
721 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
722 {
723 int ledcontrol=1;
724 int n=0, i=0;
725 uint8_t clk = arg1 >> 8;
726 uint8_t carrier = arg1 & 0xFF;
727 uint8_t invert = arg2 & 0xFF;
728 uint8_t curPhase = 0;
729 for (i=0; i<size; i++){
730 if (BitStream[i] == curPhase){
731 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
732 } else {
733 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
734 }
735 }
736 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
737 //Dbprintf("DEBUG: First 32:");
738 //uint8_t *dest = BigBuf_get_addr();
739 //i=0;
740 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
741 //i+=16;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743
744 if (ledcontrol)
745 LED_A_ON();
746 SimulateTagLowFrequency(n, 0, ledcontrol);
747
748 if (ledcontrol)
749 LED_A_OFF();
750 }
751
752 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
753 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
754 {
755 uint8_t *dest = BigBuf_get_addr();
756 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
757 size_t size = 0;
758 uint32_t hi2=0, hi=0, lo=0;
759 int idx=0;
760 // Configure to go in 125Khz listen mode
761 LFSetupFPGAForADC(95, true);
762
763 while(!BUTTON_PRESS()) {
764
765 WDT_HIT();
766 if (ledcontrol) LED_A_ON();
767
768 DoAcquisition_default(-1,true);
769 // FSK demodulator
770 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
771 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
772
773 if (idx>0 && lo>0){
774 // final loop, go over previously decoded manchester data and decode into usable tag ID
775 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
776 if (hi2 != 0){ //extra large HID tags
777 Dbprintf("TAG ID: %x%08x%08x (%d)",
778 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
779 }else { //standard HID tags <38 bits
780 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
781 uint8_t bitlen = 0;
782 uint32_t fc = 0;
783 uint32_t cardnum = 0;
784 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
785 uint32_t lo2=0;
786 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
787 uint8_t idx3 = 1;
788 while(lo2 > 1){ //find last bit set to 1 (format len bit)
789 lo2=lo2 >> 1;
790 idx3++;
791 }
792 bitlen = idx3+19;
793 fc =0;
794 cardnum=0;
795 if(bitlen == 26){
796 cardnum = (lo>>1)&0xFFFF;
797 fc = (lo>>17)&0xFF;
798 }
799 if(bitlen == 37){
800 cardnum = (lo>>1)&0x7FFFF;
801 fc = ((hi&0xF)<<12)|(lo>>20);
802 }
803 if(bitlen == 34){
804 cardnum = (lo>>1)&0xFFFF;
805 fc= ((hi&1)<<15)|(lo>>17);
806 }
807 if(bitlen == 35){
808 cardnum = (lo>>1)&0xFFFFF;
809 fc = ((hi&1)<<11)|(lo>>21);
810 }
811 }
812 else { //if bit 38 is not set then 37 bit format is used
813 bitlen= 37;
814 fc =0;
815 cardnum=0;
816 if(bitlen==37){
817 cardnum = (lo>>1)&0x7FFFF;
818 fc = ((hi&0xF)<<12)|(lo>>20);
819 }
820 }
821 //Dbprintf("TAG ID: %x%08x (%d)",
822 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
823 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
824 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
825 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
826 }
827 if (findone){
828 if (ledcontrol) LED_A_OFF();
829 *high = hi;
830 *low = lo;
831 return;
832 }
833 // reset
834 hi2 = hi = lo = 0;
835 }
836 WDT_HIT();
837 }
838 DbpString("Stopped");
839 if (ledcontrol) LED_A_OFF();
840 }
841
842 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
843 {
844 uint8_t *dest = BigBuf_get_addr();
845
846 size_t size=0, idx=0;
847 int clk=0, invert=0, errCnt=0, maxErr=20;
848 uint32_t hi=0;
849 uint64_t lo=0;
850 // Configure to go in 125Khz listen mode
851 LFSetupFPGAForADC(95, true);
852
853 while(!BUTTON_PRESS()) {
854
855 WDT_HIT();
856 if (ledcontrol) LED_A_ON();
857
858 DoAcquisition_default(-1,true);
859 size = BigBuf_max_traceLen();
860 //Dbprintf("DEBUG: Buffer got");
861 //askdemod and manchester decode
862 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
863 //Dbprintf("DEBUG: ASK Got");
864 WDT_HIT();
865
866 if (errCnt>=0){
867 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
868 //Dbprintf("DEBUG: EM GOT");
869 if (errCnt){
870 if (size>64){
871 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
872 hi,
873 (uint32_t)(lo>>32),
874 (uint32_t)lo,
875 (uint32_t)(lo&0xFFFF),
876 (uint32_t)((lo>>16LL) & 0xFF),
877 (uint32_t)(lo & 0xFFFFFF));
878 } else {
879 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
880 (uint32_t)(lo>>32),
881 (uint32_t)lo,
882 (uint32_t)(lo&0xFFFF),
883 (uint32_t)((lo>>16LL) & 0xFF),
884 (uint32_t)(lo & 0xFFFFFF));
885 }
886 }
887 if (findone){
888 if (ledcontrol) LED_A_OFF();
889 *high=lo>>32;
890 *low=lo & 0xFFFFFFFF;
891 return;
892 }
893 } else{
894 //Dbprintf("DEBUG: No Tag");
895 }
896 WDT_HIT();
897 lo = 0;
898 clk=0;
899 invert=0;
900 errCnt=0;
901 size=0;
902 }
903 DbpString("Stopped");
904 if (ledcontrol) LED_A_OFF();
905 }
906
907 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
908 {
909 uint8_t *dest = BigBuf_get_addr();
910 int idx=0;
911 uint32_t code=0, code2=0;
912 uint8_t version=0;
913 uint8_t facilitycode=0;
914 uint16_t number=0;
915 uint8_t crc = 0;
916 uint16_t calccrc = 0;
917 // Configure to go in 125Khz listen mode
918 LFSetupFPGAForADC(95, true);
919
920 while(!BUTTON_PRESS()) {
921 WDT_HIT();
922 if (ledcontrol) LED_A_ON();
923 DoAcquisition_default(-1,true);
924 //fskdemod and get start index
925 WDT_HIT();
926 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
927 if (idx>0){
928 //valid tag found
929
930 //Index map
931 //0 10 20 30 40 50 60
932 //| | | | | | |
933 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
934 //-----------------------------------------------------------------------------
935 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
936 //
937 //Checksum:
938 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
939 //preamble F0 E0 01 03 B6 75
940 // How to calc checksum,
941 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
942 // F0 + E0 + 01 + 03 + B6 = 28A
943 // 28A & FF = 8A
944 // FF - 8A = 75
945 // Checksum: 0x75
946 //XSF(version)facility:codeone+codetwo
947 //Handle the data
948 if(findone){ //only print binary if we are doing one
949 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
950 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
951 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
952 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
953 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
954 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
955 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
956 }
957 code = bytebits_to_byte(dest+idx,32);
958 code2 = bytebits_to_byte(dest+idx+32,32);
959 version = bytebits_to_byte(dest+idx+27,8); //14,4
960 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
961 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
962
963 crc = bytebits_to_byte(dest+idx+54,8);
964 for (uint8_t i=1; i<6; ++i)
965 calccrc += bytebits_to_byte(dest+idx+9*i,8);
966 calccrc &= 0xff;
967 calccrc = 0xff - calccrc;
968
969 char *crcStr = (crc == calccrc) ? "ok":"!crc";
970
971 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
972 // if we're only looking for one tag
973 if (findone){
974 if (ledcontrol) LED_A_OFF();
975 //LED_A_OFF();
976 *high=code;
977 *low=code2;
978 return;
979 }
980 code=code2=0;
981 version=facilitycode=0;
982 number=0;
983 idx=0;
984 }
985 WDT_HIT();
986 }
987 DbpString("Stopped");
988 if (ledcontrol) LED_A_OFF();
989 }
990
991 /*------------------------------
992 * T5555/T5557/T5567 routines
993 *------------------------------
994 */
995
996 /* T55x7 configuration register definitions */
997 #define T55x7_POR_DELAY 0x00000001
998 #define T55x7_ST_TERMINATOR 0x00000008
999 #define T55x7_PWD 0x00000010
1000 #define T55x7_MAXBLOCK_SHIFT 5
1001 #define T55x7_AOR 0x00000200
1002 #define T55x7_PSKCF_RF_2 0
1003 #define T55x7_PSKCF_RF_4 0x00000400
1004 #define T55x7_PSKCF_RF_8 0x00000800
1005 #define T55x7_MODULATION_DIRECT 0
1006 #define T55x7_MODULATION_PSK1 0x00001000
1007 #define T55x7_MODULATION_PSK2 0x00002000
1008 #define T55x7_MODULATION_PSK3 0x00003000
1009 #define T55x7_MODULATION_FSK1 0x00004000
1010 #define T55x7_MODULATION_FSK2 0x00005000
1011 #define T55x7_MODULATION_FSK1a 0x00006000
1012 #define T55x7_MODULATION_FSK2a 0x00007000
1013 #define T55x7_MODULATION_MANCHESTER 0x00008000
1014 #define T55x7_MODULATION_BIPHASE 0x00010000
1015 #define T55x7_BITRATE_RF_8 0
1016 #define T55x7_BITRATE_RF_16 0x00040000
1017 #define T55x7_BITRATE_RF_32 0x00080000
1018 #define T55x7_BITRATE_RF_40 0x000C0000
1019 #define T55x7_BITRATE_RF_50 0x00100000
1020 #define T55x7_BITRATE_RF_64 0x00140000
1021 #define T55x7_BITRATE_RF_100 0x00180000
1022 #define T55x7_BITRATE_RF_128 0x001C0000
1023
1024 /* T5555 (Q5) configuration register definitions */
1025 #define T5555_ST_TERMINATOR 0x00000001
1026 #define T5555_MAXBLOCK_SHIFT 0x00000001
1027 #define T5555_MODULATION_MANCHESTER 0
1028 #define T5555_MODULATION_PSK1 0x00000010
1029 #define T5555_MODULATION_PSK2 0x00000020
1030 #define T5555_MODULATION_PSK3 0x00000030
1031 #define T5555_MODULATION_FSK1 0x00000040
1032 #define T5555_MODULATION_FSK2 0x00000050
1033 #define T5555_MODULATION_BIPHASE 0x00000060
1034 #define T5555_MODULATION_DIRECT 0x00000070
1035 #define T5555_INVERT_OUTPUT 0x00000080
1036 #define T5555_PSK_RF_2 0
1037 #define T5555_PSK_RF_4 0x00000100
1038 #define T5555_PSK_RF_8 0x00000200
1039 #define T5555_USE_PWD 0x00000400
1040 #define T5555_USE_AOR 0x00000800
1041 #define T5555_BITRATE_SHIFT 12
1042 #define T5555_FAST_WRITE 0x00004000
1043 #define T5555_PAGE_SELECT 0x00008000
1044
1045 /*
1046 * Relevant times in microsecond
1047 * To compensate antenna falling times shorten the write times
1048 * and enlarge the gap ones.
1049 */
1050 #define START_GAP 50*8 // 10 - 50fc 250
1051 #define WRITE_GAP 20*8 // 8 - 30fc
1052 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
1053 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
1054
1055 // VALUES TAKEN FROM EM4x function: SendForward
1056 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1057 // WRITE_GAP = 128; (16*8)
1058 // WRITE_1 = 256 32*8; (32*8)
1059
1060 // These timings work for 4469/4269/4305 (with the 55*8 above)
1061 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1062
1063 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1064 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1065 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1066 // T0 = TIMER_CLOCK1 / 125000 = 192
1067 // 1 Cycle = 8 microseconds(us)
1068
1069 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1070
1071 // Write one bit to card
1072 void T55xxWriteBit(int bit)
1073 {
1074 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1075 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1076 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1077 if (!bit)
1078 SpinDelayUs(WRITE_0);
1079 else
1080 SpinDelayUs(WRITE_1);
1081 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1082 SpinDelayUs(WRITE_GAP);
1083 }
1084
1085 // Write one card block in page 0, no lock
1086 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1087 {
1088 uint32_t i = 0;
1089
1090 // Set up FPGA, 125kHz
1091 // Wait for config.. (192+8190xPOW)x8 == 67ms
1092 LFSetupFPGAForADC(0, true);
1093
1094 // Now start writting
1095 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1096 SpinDelayUs(START_GAP);
1097
1098 // Opcode
1099 T55xxWriteBit(1);
1100 T55xxWriteBit(0); //Page 0
1101 if (PwdMode == 1){
1102 // Pwd
1103 for (i = 0x80000000; i != 0; i >>= 1)
1104 T55xxWriteBit(Pwd & i);
1105 }
1106 // Lock bit
1107 T55xxWriteBit(0);
1108
1109 // Data
1110 for (i = 0x80000000; i != 0; i >>= 1)
1111 T55xxWriteBit(Data & i);
1112
1113 // Block
1114 for (i = 0x04; i != 0; i >>= 1)
1115 T55xxWriteBit(Block & i);
1116
1117 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1118 // so wait a little more)
1119 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1120 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1121 SpinDelay(20);
1122 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1123 }
1124
1125 // Read one card block in page 0
1126 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1127 {
1128 uint32_t i = 0;
1129 uint8_t *dest = BigBuf_get_addr();
1130 uint16_t bufferlength = BigBuf_max_traceLen();
1131 if ( bufferlength > T55xx_SAMPLES_SIZE )
1132 bufferlength = T55xx_SAMPLES_SIZE;
1133
1134 memset(dest, 0x80, bufferlength);
1135
1136 // Set up FPGA, 125kHz
1137 // Wait for config.. (192+8190xPOW)x8 == 67ms
1138 LFSetupFPGAForADC(0, true);
1139 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1140 SpinDelayUs(START_GAP);
1141
1142 // Opcode
1143 T55xxWriteBit(1);
1144 T55xxWriteBit(0); //Page 0
1145 if (PwdMode == 1){
1146 // Pwd
1147 for (i = 0x80000000; i != 0; i >>= 1)
1148 T55xxWriteBit(Pwd & i);
1149 }
1150 // Lock bit
1151 T55xxWriteBit(0);
1152 // Block
1153 for (i = 0x04; i != 0; i >>= 1)
1154 T55xxWriteBit(Block & i);
1155
1156 // Turn field on to read the response
1157 TurnReadLFOn();
1158
1159 // Now do the acquisition
1160 i = 0;
1161 for(;;) {
1162 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1163 AT91C_BASE_SSC->SSC_THR = 0x43;
1164 LED_D_ON();
1165 }
1166 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1167 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1168 ++i;
1169 LED_D_OFF();
1170 if (i >= bufferlength) break;
1171 }
1172 }
1173
1174 cmd_send(CMD_ACK,0,0,0,0,0);
1175 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1176 LED_D_OFF();
1177 }
1178
1179 // Read card traceability data (page 1)
1180 void T55xxReadTrace(void){
1181
1182 uint32_t i = 0;
1183 uint8_t *dest = BigBuf_get_addr();
1184 uint16_t bufferlength = BigBuf_max_traceLen();
1185 if ( bufferlength > T55xx_SAMPLES_SIZE )
1186 bufferlength = T55xx_SAMPLES_SIZE;
1187
1188 memset(dest, 0x80, bufferlength);
1189
1190 LFSetupFPGAForADC(0, true);
1191 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1192 SpinDelayUs(START_GAP);
1193
1194 // Opcode
1195 T55xxWriteBit(1);
1196 T55xxWriteBit(1); //Page 1
1197
1198 // Turn field on to read the response
1199 TurnReadLFOn();
1200
1201 // Now do the acquisition
1202 for(;;) {
1203 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1204 AT91C_BASE_SSC->SSC_THR = 0x43;
1205 LED_D_ON();
1206 }
1207 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1208 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1209 ++i;
1210 LED_D_OFF();
1211
1212 if (i >= bufferlength) break;
1213 }
1214 }
1215
1216 cmd_send(CMD_ACK,0,0,0,0,0);
1217 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1218 LED_D_OFF();
1219 }
1220
1221 void TurnReadLFOn(){
1222 //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1223 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1224 // Give it a bit of time for the resonant antenna to settle.
1225 //SpinDelay(30);
1226 SpinDelayUs(8*150);
1227 }
1228
1229 /*-------------- Cloning routines -----------*/
1230 // Copy HID id to card and setup block 0 config
1231 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1232 {
1233 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1234 int last_block = 0;
1235
1236 if (longFMT){
1237 // Ensure no more than 84 bits supplied
1238 if (hi2>0xFFFFF) {
1239 DbpString("Tags can only have 84 bits.");
1240 return;
1241 }
1242 // Build the 6 data blocks for supplied 84bit ID
1243 last_block = 6;
1244 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1245 for (int i=0;i<4;i++) {
1246 if (hi2 & (1<<(19-i)))
1247 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1248 else
1249 data1 |= (1<<((3-i)*2)); // 0 -> 01
1250 }
1251
1252 data2 = 0;
1253 for (int i=0;i<16;i++) {
1254 if (hi2 & (1<<(15-i)))
1255 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1256 else
1257 data2 |= (1<<((15-i)*2)); // 0 -> 01
1258 }
1259
1260 data3 = 0;
1261 for (int i=0;i<16;i++) {
1262 if (hi & (1<<(31-i)))
1263 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1264 else
1265 data3 |= (1<<((15-i)*2)); // 0 -> 01
1266 }
1267
1268 data4 = 0;
1269 for (int i=0;i<16;i++) {
1270 if (hi & (1<<(15-i)))
1271 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1272 else
1273 data4 |= (1<<((15-i)*2)); // 0 -> 01
1274 }
1275
1276 data5 = 0;
1277 for (int i=0;i<16;i++) {
1278 if (lo & (1<<(31-i)))
1279 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1280 else
1281 data5 |= (1<<((15-i)*2)); // 0 -> 01
1282 }
1283
1284 data6 = 0;
1285 for (int i=0;i<16;i++) {
1286 if (lo & (1<<(15-i)))
1287 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1288 else
1289 data6 |= (1<<((15-i)*2)); // 0 -> 01
1290 }
1291 }
1292 else {
1293 // Ensure no more than 44 bits supplied
1294 if (hi>0xFFF) {
1295 DbpString("Tags can only have 44 bits.");
1296 return;
1297 }
1298
1299 // Build the 3 data blocks for supplied 44bit ID
1300 last_block = 3;
1301
1302 data1 = 0x1D000000; // load preamble
1303
1304 for (int i=0;i<12;i++) {
1305 if (hi & (1<<(11-i)))
1306 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1307 else
1308 data1 |= (1<<((11-i)*2)); // 0 -> 01
1309 }
1310
1311 data2 = 0;
1312 for (int i=0;i<16;i++) {
1313 if (lo & (1<<(31-i)))
1314 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1315 else
1316 data2 |= (1<<((15-i)*2)); // 0 -> 01
1317 }
1318
1319 data3 = 0;
1320 for (int i=0;i<16;i++) {
1321 if (lo & (1<<(15-i)))
1322 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1323 else
1324 data3 |= (1<<((15-i)*2)); // 0 -> 01
1325 }
1326 }
1327
1328 LED_D_ON();
1329 // Program the data blocks for supplied ID
1330 // and the block 0 for HID format
1331 T55xxWriteBlock(data1,1,0,0);
1332 T55xxWriteBlock(data2,2,0,0);
1333 T55xxWriteBlock(data3,3,0,0);
1334
1335 if (longFMT) { // if long format there are 6 blocks
1336 T55xxWriteBlock(data4,4,0,0);
1337 T55xxWriteBlock(data5,5,0,0);
1338 T55xxWriteBlock(data6,6,0,0);
1339 }
1340
1341 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1342 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1343 T55x7_MODULATION_FSK2a |
1344 last_block << T55x7_MAXBLOCK_SHIFT,
1345 0,0,0);
1346
1347 LED_D_OFF();
1348
1349 DbpString("DONE!");
1350 }
1351
1352 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1353 {
1354 int data1=0, data2=0; //up to six blocks for long format
1355
1356 data1 = hi; // load preamble
1357 data2 = lo;
1358
1359 LED_D_ON();
1360 // Program the data blocks for supplied ID
1361 // and the block 0 for HID format
1362 T55xxWriteBlock(data1,1,0,0);
1363 T55xxWriteBlock(data2,2,0,0);
1364
1365 //Config Block
1366 T55xxWriteBlock(0x00147040,0,0,0);
1367 LED_D_OFF();
1368
1369 DbpString("DONE!");
1370 }
1371
1372 // Define 9bit header for EM410x tags
1373 #define EM410X_HEADER 0x1FF
1374 #define EM410X_ID_LENGTH 40
1375
1376 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1377 {
1378 int i, id_bit;
1379 uint64_t id = EM410X_HEADER;
1380 uint64_t rev_id = 0; // reversed ID
1381 int c_parity[4]; // column parity
1382 int r_parity = 0; // row parity
1383 uint32_t clock = 0;
1384
1385 // Reverse ID bits given as parameter (for simpler operations)
1386 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1387 if (i < 32) {
1388 rev_id = (rev_id << 1) | (id_lo & 1);
1389 id_lo >>= 1;
1390 } else {
1391 rev_id = (rev_id << 1) | (id_hi & 1);
1392 id_hi >>= 1;
1393 }
1394 }
1395
1396 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1397 id_bit = rev_id & 1;
1398
1399 if (i % 4 == 0) {
1400 // Don't write row parity bit at start of parsing
1401 if (i)
1402 id = (id << 1) | r_parity;
1403 // Start counting parity for new row
1404 r_parity = id_bit;
1405 } else {
1406 // Count row parity
1407 r_parity ^= id_bit;
1408 }
1409
1410 // First elements in column?
1411 if (i < 4)
1412 // Fill out first elements
1413 c_parity[i] = id_bit;
1414 else
1415 // Count column parity
1416 c_parity[i % 4] ^= id_bit;
1417
1418 // Insert ID bit
1419 id = (id << 1) | id_bit;
1420 rev_id >>= 1;
1421 }
1422
1423 // Insert parity bit of last row
1424 id = (id << 1) | r_parity;
1425
1426 // Fill out column parity at the end of tag
1427 for (i = 0; i < 4; ++i)
1428 id = (id << 1) | c_parity[i];
1429
1430 // Add stop bit
1431 id <<= 1;
1432
1433 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1434 LED_D_ON();
1435
1436 // Write EM410x ID
1437 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1438 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1439
1440 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1441 if (card) {
1442 // Clock rate is stored in bits 8-15 of the card value
1443 clock = (card & 0xFF00) >> 8;
1444 Dbprintf("Clock rate: %d", clock);
1445 switch (clock)
1446 {
1447 case 32:
1448 clock = T55x7_BITRATE_RF_32;
1449 break;
1450 case 16:
1451 clock = T55x7_BITRATE_RF_16;
1452 break;
1453 case 0:
1454 // A value of 0 is assumed to be 64 for backwards-compatibility
1455 // Fall through...
1456 case 64:
1457 clock = T55x7_BITRATE_RF_64;
1458 break;
1459 default:
1460 Dbprintf("Invalid clock rate: %d", clock);
1461 return;
1462 }
1463
1464 // Writing configuration for T55x7 tag
1465 T55xxWriteBlock(clock |
1466 T55x7_MODULATION_MANCHESTER |
1467 2 << T55x7_MAXBLOCK_SHIFT,
1468 0, 0, 0);
1469 }
1470 else
1471 // Writing configuration for T5555(Q5) tag
1472 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1473 T5555_MODULATION_MANCHESTER |
1474 2 << T5555_MAXBLOCK_SHIFT,
1475 0, 0, 0);
1476
1477 LED_D_OFF();
1478 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1479 (uint32_t)(id >> 32), (uint32_t)id);
1480 }
1481
1482 // Clone Indala 64-bit tag by UID to T55x7
1483 void CopyIndala64toT55x7(int hi, int lo)
1484 {
1485
1486 //Program the 2 data blocks for supplied 64bit UID
1487 // and the block 0 for Indala64 format
1488 T55xxWriteBlock(hi,1,0,0);
1489 T55xxWriteBlock(lo,2,0,0);
1490 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1491 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1492 T55x7_MODULATION_PSK1 |
1493 2 << T55x7_MAXBLOCK_SHIFT,
1494 0, 0, 0);
1495 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1496 // T5567WriteBlock(0x603E1042,0);
1497
1498 DbpString("DONE!");
1499
1500 }
1501
1502 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1503 {
1504
1505 //Program the 7 data blocks for supplied 224bit UID
1506 // and the block 0 for Indala224 format
1507 T55xxWriteBlock(uid1,1,0,0);
1508 T55xxWriteBlock(uid2,2,0,0);
1509 T55xxWriteBlock(uid3,3,0,0);
1510 T55xxWriteBlock(uid4,4,0,0);
1511 T55xxWriteBlock(uid5,5,0,0);
1512 T55xxWriteBlock(uid6,6,0,0);
1513 T55xxWriteBlock(uid7,7,0,0);
1514 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1515 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1516 T55x7_MODULATION_PSK1 |
1517 7 << T55x7_MAXBLOCK_SHIFT,
1518 0,0,0);
1519 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1520 // T5567WriteBlock(0x603E10E2,0);
1521
1522 DbpString("DONE!");
1523
1524 }
1525
1526
1527 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1528 #define max(x,y) ( x<y ? y:x)
1529
1530 int DemodPCF7931(uint8_t **outBlocks) {
1531
1532 uint8_t bits[256] = {0x00};
1533 uint8_t blocks[8][16];
1534 uint8_t *dest = BigBuf_get_addr();
1535
1536 int GraphTraceLen = BigBuf_max_traceLen();
1537 if ( GraphTraceLen > 18000 )
1538 GraphTraceLen = 18000;
1539
1540
1541 int i, j, lastval, bitidx, half_switch;
1542 int clock = 64;
1543 int tolerance = clock / 8;
1544 int pmc, block_done;
1545 int lc, warnings = 0;
1546 int num_blocks = 0;
1547 int lmin=128, lmax=128;
1548 uint8_t dir;
1549
1550 LFSetupFPGAForADC(95, true);
1551 DoAcquisition_default(0, true);
1552
1553 lmin = 64;
1554 lmax = 192;
1555
1556 i = 2;
1557
1558 /* Find first local max/min */
1559 if(dest[1] > dest[0]) {
1560 while(i < GraphTraceLen) {
1561 if( !(dest[i] > dest[i-1]) && dest[i] > lmax)
1562 break;
1563 i++;
1564 }
1565 dir = 0;
1566 }
1567 else {
1568 while(i < GraphTraceLen) {
1569 if( !(dest[i] < dest[i-1]) && dest[i] < lmin)
1570 break;
1571 i++;
1572 }
1573 dir = 1;
1574 }
1575
1576 lastval = i++;
1577 half_switch = 0;
1578 pmc = 0;
1579 block_done = 0;
1580
1581 for (bitidx = 0; i < GraphTraceLen; i++)
1582 {
1583 if ( (dest[i-1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i-1] < dest[i] && dir == 0 && dest[i] < lmin))
1584 {
1585 lc = i - lastval;
1586 lastval = i;
1587
1588 // Switch depending on lc length:
1589 // Tolerance is 1/8 of clock rate (arbitrary)
1590 if (abs(lc-clock/4) < tolerance) {
1591 // 16T0
1592 if((i - pmc) == lc) { /* 16T0 was previous one */
1593 /* It's a PMC ! */
1594 i += (128+127+16+32+33+16)-1;
1595 lastval = i;
1596 pmc = 0;
1597 block_done = 1;
1598 }
1599 else {
1600 pmc = i;
1601 }
1602 } else if (abs(lc-clock/2) < tolerance) {
1603 // 32TO
1604 if((i - pmc) == lc) { /* 16T0 was previous one */
1605 /* It's a PMC ! */
1606 i += (128+127+16+32+33)-1;
1607 lastval = i;
1608 pmc = 0;
1609 block_done = 1;
1610 }
1611 else if(half_switch == 1) {
1612 bits[bitidx++] = 0;
1613 half_switch = 0;
1614 }
1615 else
1616 half_switch++;
1617 } else if (abs(lc-clock) < tolerance) {
1618 // 64TO
1619 bits[bitidx++] = 1;
1620 } else {
1621 // Error
1622 warnings++;
1623 if (warnings > 10)
1624 {
1625 Dbprintf("Error: too many detection errors, aborting.");
1626 return 0;
1627 }
1628 }
1629
1630 if(block_done == 1) {
1631 if(bitidx == 128) {
1632 for(j=0; j<16; j++) {
1633 blocks[num_blocks][j] = 128*bits[j*8+7]+
1634 64*bits[j*8+6]+
1635 32*bits[j*8+5]+
1636 16*bits[j*8+4]+
1637 8*bits[j*8+3]+
1638 4*bits[j*8+2]+
1639 2*bits[j*8+1]+
1640 bits[j*8];
1641
1642 }
1643 num_blocks++;
1644 }
1645 bitidx = 0;
1646 block_done = 0;
1647 half_switch = 0;
1648 }
1649 if(i < GraphTraceLen)
1650 dir =(dest[i-1] > dest[i]) ? 0 : 1;
1651 }
1652 if(bitidx==255)
1653 bitidx=0;
1654 warnings = 0;
1655 if(num_blocks == 4) break;
1656 }
1657 memcpy(outBlocks, blocks, 16*num_blocks);
1658 return num_blocks;
1659 }
1660
1661 int IsBlock0PCF7931(uint8_t *Block) {
1662 // Assume RFU means 0 :)
1663 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1664 return 1;
1665 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1666 return 1;
1667 return 0;
1668 }
1669
1670 int IsBlock1PCF7931(uint8_t *Block) {
1671 // Assume RFU means 0 :)
1672 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1673 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1674 return 1;
1675
1676 return 0;
1677 }
1678
1679 #define ALLOC 16
1680
1681 void ReadPCF7931() {
1682 uint8_t Blocks[8][17];
1683 uint8_t tmpBlocks[4][16];
1684 int i, j, ind, ind2, n;
1685 int num_blocks = 0;
1686 int max_blocks = 8;
1687 int ident = 0;
1688 int error = 0;
1689 int tries = 0;
1690
1691 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1692
1693 do {
1694 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1695 n = DemodPCF7931((uint8_t**)tmpBlocks);
1696 if(!n)
1697 error++;
1698 if(error==10 && num_blocks == 0) {
1699 Dbprintf("Error, no tag or bad tag");
1700 return;
1701 }
1702 else if (tries==20 || error==10) {
1703 Dbprintf("Error reading the tag");
1704 Dbprintf("Here is the partial content");
1705 goto end;
1706 }
1707
1708 for(i=0; i<n; i++)
1709 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1710 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1711 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1712 if(!ident) {
1713 for(i=0; i<n; i++) {
1714 if(IsBlock0PCF7931(tmpBlocks[i])) {
1715 // Found block 0 ?
1716 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1717 // Found block 1!
1718 // \o/
1719 ident = 1;
1720 memcpy(Blocks[0], tmpBlocks[i], 16);
1721 Blocks[0][ALLOC] = 1;
1722 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1723 Blocks[1][ALLOC] = 1;
1724 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1725 // Debug print
1726 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1727 num_blocks = 2;
1728 // Handle following blocks
1729 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1730 if(j==n) j=0;
1731 if(j==i) break;
1732 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1733 Blocks[ind2][ALLOC] = 1;
1734 }
1735 break;
1736 }
1737 }
1738 }
1739 }
1740 else {
1741 for(i=0; i<n; i++) { // Look for identical block in known blocks
1742 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1743 for(j=0; j<max_blocks; j++) {
1744 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1745 // Found an identical block
1746 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1747 if(ind2 < 0)
1748 ind2 = max_blocks;
1749 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1750 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1751 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1752 Blocks[ind2][ALLOC] = 1;
1753 num_blocks++;
1754 if(num_blocks == max_blocks) goto end;
1755 }
1756 }
1757 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1758 if(ind2 > max_blocks)
1759 ind2 = 0;
1760 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1761 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1762 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1763 Blocks[ind2][ALLOC] = 1;
1764 num_blocks++;
1765 if(num_blocks == max_blocks) goto end;
1766 }
1767 }
1768 }
1769 }
1770 }
1771 }
1772 }
1773 tries++;
1774 if (BUTTON_PRESS()) return;
1775 } while (num_blocks != max_blocks);
1776 end:
1777 Dbprintf("-----------------------------------------");
1778 Dbprintf("Memory content:");
1779 Dbprintf("-----------------------------------------");
1780 for(i=0; i<max_blocks; i++) {
1781 if(Blocks[i][ALLOC]==1)
1782 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1783 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1784 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1785 else
1786 Dbprintf("<missing block %d>", i);
1787 }
1788 Dbprintf("-----------------------------------------");
1789
1790 return ;
1791 }
1792
1793
1794 //-----------------------------------
1795 // EM4469 / EM4305 routines
1796 //-----------------------------------
1797 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1798 #define FWD_CMD_WRITE 0xA
1799 #define FWD_CMD_READ 0x9
1800 #define FWD_CMD_DISABLE 0x5
1801
1802
1803 uint8_t forwardLink_data[64]; //array of forwarded bits
1804 uint8_t * forward_ptr; //ptr for forward message preparation
1805 uint8_t fwd_bit_sz; //forwardlink bit counter
1806 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1807
1808 //====================================================================
1809 // prepares command bits
1810 // see EM4469 spec
1811 //====================================================================
1812 //--------------------------------------------------------------------
1813 uint8_t Prepare_Cmd( uint8_t cmd ) {
1814 //--------------------------------------------------------------------
1815
1816 *forward_ptr++ = 0; //start bit
1817 *forward_ptr++ = 0; //second pause for 4050 code
1818
1819 *forward_ptr++ = cmd;
1820 cmd >>= 1;
1821 *forward_ptr++ = cmd;
1822 cmd >>= 1;
1823 *forward_ptr++ = cmd;
1824 cmd >>= 1;
1825 *forward_ptr++ = cmd;
1826
1827 return 6; //return number of emited bits
1828 }
1829
1830 //====================================================================
1831 // prepares address bits
1832 // see EM4469 spec
1833 //====================================================================
1834
1835 //--------------------------------------------------------------------
1836 uint8_t Prepare_Addr( uint8_t addr ) {
1837 //--------------------------------------------------------------------
1838
1839 register uint8_t line_parity;
1840
1841 uint8_t i;
1842 line_parity = 0;
1843 for(i=0;i<6;i++) {
1844 *forward_ptr++ = addr;
1845 line_parity ^= addr;
1846 addr >>= 1;
1847 }
1848
1849 *forward_ptr++ = (line_parity & 1);
1850
1851 return 7; //return number of emited bits
1852 }
1853
1854 //====================================================================
1855 // prepares data bits intreleaved with parity bits
1856 // see EM4469 spec
1857 //====================================================================
1858
1859 //--------------------------------------------------------------------
1860 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1861 //--------------------------------------------------------------------
1862
1863 register uint8_t line_parity;
1864 register uint8_t column_parity;
1865 register uint8_t i, j;
1866 register uint16_t data;
1867
1868 data = data_low;
1869 column_parity = 0;
1870
1871 for(i=0; i<4; i++) {
1872 line_parity = 0;
1873 for(j=0; j<8; j++) {
1874 line_parity ^= data;
1875 column_parity ^= (data & 1) << j;
1876 *forward_ptr++ = data;
1877 data >>= 1;
1878 }
1879 *forward_ptr++ = line_parity;
1880 if(i == 1)
1881 data = data_hi;
1882 }
1883
1884 for(j=0; j<8; j++) {
1885 *forward_ptr++ = column_parity;
1886 column_parity >>= 1;
1887 }
1888 *forward_ptr = 0;
1889
1890 return 45; //return number of emited bits
1891 }
1892
1893 //====================================================================
1894 // Forward Link send function
1895 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1896 // fwd_bit_count set with number of bits to be sent
1897 //====================================================================
1898 void SendForward(uint8_t fwd_bit_count) {
1899
1900 fwd_write_ptr = forwardLink_data;
1901 fwd_bit_sz = fwd_bit_count;
1902
1903 LED_D_ON();
1904
1905 //Field on
1906 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1907 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1908 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1909
1910 // Give it a bit of time for the resonant antenna to settle.
1911 // And for the tag to fully power up
1912 SpinDelay(150);
1913
1914 // force 1st mod pulse (start gap must be longer for 4305)
1915 fwd_bit_sz--; //prepare next bit modulation
1916 fwd_write_ptr++;
1917 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1918 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1919 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1920 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1921 SpinDelayUs(16*8); //16 cycles on (8us each)
1922
1923 // now start writting
1924 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1925 if(((*fwd_write_ptr++) & 1) == 1)
1926 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1927 else {
1928 //These timings work for 4469/4269/4305 (with the 55*8 above)
1929 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1930 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1931 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1932 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1933 SpinDelayUs(9*8); //16 cycles on (8us each)
1934 }
1935 }
1936 }
1937
1938 void EM4xLogin(uint32_t Password) {
1939
1940 uint8_t fwd_bit_count;
1941
1942 forward_ptr = forwardLink_data;
1943 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1944 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1945
1946 SendForward(fwd_bit_count);
1947
1948 //Wait for command to complete
1949 SpinDelay(20);
1950
1951 }
1952
1953 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1954
1955 uint8_t *dest = BigBuf_get_addr();
1956 uint16_t bufferlength = BigBuf_max_traceLen();
1957 uint32_t i = 0;
1958
1959 // Clear destination buffer before sending the command 0x80 = average.
1960 memset(dest, 0x80, bufferlength);
1961
1962 uint8_t fwd_bit_count;
1963
1964 //If password mode do login
1965 if (PwdMode == 1) EM4xLogin(Pwd);
1966
1967 forward_ptr = forwardLink_data;
1968 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1969 fwd_bit_count += Prepare_Addr( Address );
1970
1971 // Connect the A/D to the peak-detected low-frequency path.
1972 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1973 // Now set up the SSC to get the ADC samples that are now streaming at us.
1974 FpgaSetupSsc();
1975
1976 SendForward(fwd_bit_count);
1977
1978 // Now do the acquisition
1979 i = 0;
1980 for(;;) {
1981 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1982 AT91C_BASE_SSC->SSC_THR = 0x43;
1983 }
1984 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1985 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1986 ++i;
1987 if (i >= bufferlength) break;
1988 }
1989 }
1990
1991 cmd_send(CMD_ACK,0,0,0,0,0);
1992 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1993 LED_D_OFF();
1994 }
1995
1996 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1997
1998 uint8_t fwd_bit_count;
1999
2000 //If password mode do login
2001 if (PwdMode == 1) EM4xLogin(Pwd);
2002
2003 forward_ptr = forwardLink_data;
2004 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2005 fwd_bit_count += Prepare_Addr( Address );
2006 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
2007
2008 SendForward(fwd_bit_count);
2009
2010 //Wait for write to complete
2011 SpinDelay(20);
2012 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2013 LED_D_OFF();
2014 }
Proxmark3 GIT tracking
Impressum, Datenschutz