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[proxmark3-svn] / fpga / hi_get_trace.v
1 //-----------------------------------------------------------------------------
2 //
3 // piwi, Feb 2019
4 //-----------------------------------------------------------------------------
5
6 module hi_get_trace(
7 ck_1356megb,
8 adc_d, trace_enable, major_mode,
9 ssp_frame, ssp_din, ssp_clk
10 );
11 input ck_1356megb;
12 input [7:0] adc_d;
13 input trace_enable;
14 input [2:0] major_mode;
15 output ssp_frame, ssp_din, ssp_clk;
16
17 // constants for some major_modes:
18 `define OFF 3'b111
19 `define GET_TRACE 3'b101
20
21
22 // clock divider
23 reg [6:0] clock_cnt;
24 always @(negedge ck_1356megb)
25 begin
26 clock_cnt <= clock_cnt + 1;
27 end
28
29 // sample at 13,56MHz / 8. The highest signal frequency (subcarrier) is 848,5kHz, i.e. in this case we oversample by a factor of 2
30 reg [2:0] sample_clock;
31 always @(negedge ck_1356megb)
32 begin
33 if (sample_clock == 3'd3)
34 sample_clock <= 3'd0;
35 else
36 sample_clock <= sample_clock + 1;
37 end
38
39
40 reg [11:0] addr;
41 reg [11:0] start_addr;
42 reg [2:0] previous_major_mode;
43 reg write_enable1;
44 reg write_enable2;
45 always @(negedge ck_1356megb)
46 begin
47 previous_major_mode <= major_mode;
48 if (major_mode == `GET_TRACE)
49 begin
50 write_enable1 <= 1'b0;
51 write_enable2 <= 1'b0;
52 if (previous_major_mode != `GET_TRACE) // just switched into GET_TRACE mode
53 addr <= start_addr;
54 if (clock_cnt == 7'd0)
55 begin
56 if (addr == 12'd3071)
57 addr <= 12'd0;
58 else
59 addr <= addr + 1;
60 end
61 end
62 else if (major_mode != `OFF)
63 begin
64 if (trace_enable)
65 begin
66 if (addr[11] == 1'b0)
67 begin
68 write_enable1 <= 1'b1;
69 write_enable2 <= 1'b0;
70 end
71 else
72 begin
73 write_enable1 <= 1'b0;
74 write_enable2 <= 1'b1;
75 end
76 if (sample_clock == 3'b000)
77 begin
78 if (addr == 12'd3071)
79 begin
80 addr <= 12'd0;
81 write_enable1 <= 1'b1;
82 write_enable2 <= 1'b0;
83 end
84 else
85 addr <= addr + 1;
86 end
87 end
88 else
89 begin
90 write_enable1 <= 1'b0;
91 write_enable2 <= 1'b0;
92 start_addr <= addr;
93 end
94 end
95 else // major_mode == `OFF
96 begin
97 write_enable1 <= 1'b0;
98 write_enable2 <= 1'b0;
99 if (previous_major_mode != `OFF && previous_major_mode != `GET_TRACE) // just switched off
100 start_addr <= addr;
101 end
102 end
103
104
105 // (2+1)k RAM
106 reg [7:0] D_out1, D_out2;
107 reg [7:0] ram1 [2047:0];
108 reg [7:0] ram2 [1023:0];
109
110 always @(negedge ck_1356megb)
111 begin
112 if (write_enable1)
113 begin
114 ram1[addr[10:0]] <= adc_d;
115 D_out1 <= adc_d;
116 end
117 else
118 D_out1 <= ram1[addr[10:0]];
119 if (write_enable2)
120 begin
121 ram2[addr[9:0]] <= adc_d;
122 D_out2 <= adc_d;
123 end
124 else
125 D_out2 <= ram2[addr[9:0]];
126 end
127
128
129 // SSC communication to ARM
130 reg ssp_clk;
131 reg ssp_frame;
132 reg [7:0] shift_out;
133
134 always @(negedge ck_1356megb)
135 begin
136 if(clock_cnt[3:0] == 4'd0) // update shift register every 16 clock cycles
137 begin
138 if(clock_cnt[6:4] == 3'd0) // either load new value
139 begin
140 if (addr[11] == 1'b0)
141 shift_out <= D_out1;
142 else
143 shift_out <= D_out2;
144 end
145 else // or shift left
146 shift_out[7:1] <= shift_out[6:0];
147 end
148
149 ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz
150
151 if(clock_cnt[6:4] == 3'b000) // set ssp_frame for 0...31
152 ssp_frame <= 1'b1;
153 else
154 ssp_frame <= 1'b0;
155
156 end
157
158 assign ssp_din = shift_out[7];
159
160 endmodule
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