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Add explicit PHDRs to bootrom to properly separate data and bss
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1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "string.h"
15
16 #include "legicrf.h"
17 #include "legic_prng.h"
18 #include "crc.h"
19
20 static struct legic_frame {
21 int bits;
22 uint32_t data;
23 } current_frame;
24
25 static crc_t legic_crc;
26
27 AT91PS_TC timer;
28
29 static void setup_timer(void)
30 {
31 /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
32 * this it won't be terribly accurate but should be good enough.
33 */
34 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
35 timer = AT91C_BASE_TC1;
36 timer->TC_CCR = AT91C_TC_CLKDIS;
37 timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3;
38 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
39
40 /* At TIMER_CLOCK3 (MCK/32) */
41 #define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
42 #define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
43 #define RWD_TIME_PAUSE 30 /* 20us */
44 #define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
45 #define TAG_TIME_BIT 150 /* 100us for every bit */
46 #define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */
47
48 }
49
50 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
51
52 /* Send a frame in reader mode, the FPGA must have been set up by
53 * LegicRfReader
54 */
55 static void frame_send_rwd(uint32_t data, int bits)
56 {
57 /* Start clock */
58 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
59 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
60
61 int i;
62 for(i=0; i<bits; i++) {
63 int starttime = timer->TC_CV;
64 int pause_end = starttime + RWD_TIME_PAUSE, bit_end;
65 int bit = data & 1;
66 data = data >> 1;
67
68 if(bit ^ legic_prng_get_bit()) {
69 bit_end = starttime + RWD_TIME_1;
70 } else {
71 bit_end = starttime + RWD_TIME_0;
72 }
73
74 /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
75 * RWD_TIME_x, where x is the bit to be transmitted */
76 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
77 while(timer->TC_CV < pause_end) ;
78 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
79 legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */
80
81 while(timer->TC_CV < bit_end) ;
82 }
83
84 {
85 /* One final pause to mark the end of the frame */
86 int pause_end = timer->TC_CV + RWD_TIME_PAUSE;
87 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
88 while(timer->TC_CV < pause_end) ;
89 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
90 }
91
92 /* Reset the timer, to measure time until the start of the tag frame */
93 timer->TC_CCR = AT91C_TC_SWTRG;
94 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
95 }
96
97 /* Receive a frame from the card in reader emulation mode, the FPGA and
98 * timer must have been set up by LegicRfReader and frame_send_rwd.
99 *
100 * The LEGIC RF protocol from card to reader does not include explicit
101 * frame start/stop information or length information. The reader must
102 * know beforehand how many bits it wants to receive. (Notably: a card
103 * sending a stream of 0-bits is indistinguishable from no card present.)
104 *
105 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
106 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
107 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
108 * for edges. Count the edges in each bit interval. If they are approximately
109 * 0 this was a 0-bit, if they are approximately equal to the number of edges
110 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
111 * timer that's still running from frame_send_rwd in order to get a synchronization
112 * with the frame that we just sent.
113 *
114 * FIXME: Because we're relying on the hysteresis to just do the right thing
115 * the range is severely reduced (and you'll probably also need a good antenna).
116 * So this should be fixed some time in the future for a proper receiver.
117 */
118 static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt)
119 {
120 uint32_t the_bit = 1; /* Use a bitmask to save on shifts */
121 uint32_t data=0;
122 int i, old_level=0, edges=0;
123 int next_bit_at = TAG_TIME_WAIT;
124
125
126 if(bits > 16)
127 bits = 16;
128
129 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
130 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
131
132 /* we have some time now, precompute the cipher
133 * since we cannot compute it on the fly while reading */
134 legic_prng_forward(2);
135
136 if(crypt)
137 {
138 for(i=0; i<bits; i++) {
139 data |= legic_prng_get_bit() << i;
140 legic_prng_forward(1);
141 }
142 }
143
144 while(timer->TC_CV < next_bit_at) ;
145
146 next_bit_at += TAG_TIME_BIT;
147
148 for(i=0; i<bits; i++) {
149 edges = 0;
150
151 while(timer->TC_CV < next_bit_at) {
152 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
153 if(level != old_level)
154 edges++;
155 old_level = level;
156 }
157 next_bit_at += TAG_TIME_BIT;
158
159 if(edges > 20 && edges < 60) { /* expected are 42 edges */
160 data ^= the_bit;
161 }
162
163 the_bit <<= 1;
164 }
165
166 f->data = data;
167 f->bits = bits;
168
169 /* Reset the timer, to synchronize the next frame */
170 timer->TC_CCR = AT91C_TC_SWTRG;
171 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
172 }
173
174 static void frame_clean(struct legic_frame * const f)
175 {
176 f->data = 0;
177 f->bits = 0;
178 }
179
180 static uint32_t perform_setup_phase_rwd(int iv)
181 {
182
183 /* Switch on carrier and let the tag charge for 1ms */
184 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
185 SpinDelay(1);
186
187 legic_prng_init(0); /* no keystream yet */
188 frame_send_rwd(iv, 7);
189 legic_prng_init(iv);
190
191 frame_clean(&current_frame);
192 frame_receive_rwd(&current_frame, 6, 1);
193 legic_prng_forward(1); /* we wait anyways */
194 while(timer->TC_CV < 387) ; /* ~ 258us */
195 frame_send_rwd(0x19, 6);
196
197 return current_frame.data;
198 }
199
200 static void LegicCommonInit(void) {
201 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
202 FpgaSetupSsc();
203 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
204
205 /* Bitbang the transmitter */
206 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
207 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
208 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
209
210 setup_timer();
211
212 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
213 }
214
215 static void switch_off_tag_rwd(void)
216 {
217 /* Switch off carrier, make sure tag is reset */
218 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
219 SpinDelay(10);
220
221 WDT_HIT();
222 }
223 /* calculate crc for a legic command */
224 static int LegicCRC(int byte_index, int value, int cmd_sz) {
225 crc_clear(&legic_crc);
226 crc_update(&legic_crc, 1, 1); /* CMD_READ */
227 crc_update(&legic_crc, byte_index, cmd_sz-1);
228 crc_update(&legic_crc, value, 8);
229 return crc_finish(&legic_crc);
230 }
231
232 int legic_read_byte(int byte_index, int cmd_sz) {
233 int byte;
234
235 legic_prng_forward(4); /* we wait anyways */
236 while(timer->TC_CV < 387) ; /* ~ 258us + 100us*delay */
237
238 frame_send_rwd(1 | (byte_index << 1), cmd_sz);
239 frame_clean(&current_frame);
240
241 frame_receive_rwd(&current_frame, 12, 1);
242
243 byte = current_frame.data & 0xff;
244 if( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) {
245 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz), current_frame.data >> 8);
246 return -1;
247 }
248
249 return byte;
250 }
251
252 /* legic_write_byte() is not included, however it's trivial to implement
253 * and here are some hints on what remains to be done:
254 *
255 * * assemble a write_cmd_frame with crc and send it
256 * * wait until the tag sends back an ACK ('1' bit unencrypted)
257 * * forward the prng based on the timing
258 */
259
260
261 void LegicRfReader(int offset, int bytes) {
262 int byte_index=0, cmd_sz=0, card_sz=0;
263
264 LegicCommonInit();
265
266 memset(BigBuf, 0, 1024);
267
268 DbpString("setting up legic card");
269 uint32_t tag_type = perform_setup_phase_rwd(0x55);
270 switch(tag_type) {
271 case 0x1d:
272 DbpString("MIM 256 card found, reading card ...");
273 cmd_sz = 9;
274 card_sz = 256;
275 break;
276 case 0x3d:
277 DbpString("MIM 1024 card found, reading card ...");
278 cmd_sz = 11;
279 card_sz = 1024;
280 break;
281 default:
282 Dbprintf("Unknown card format: %x",tag_type);
283 switch_off_tag_rwd();
284 return;
285 }
286 if(bytes == -1) {
287 bytes = card_sz;
288 }
289 if(bytes+offset >= card_sz) {
290 bytes = card_sz-offset;
291 }
292
293 switch_off_tag_rwd(); //we lost to mutch time with dprintf
294 perform_setup_phase_rwd(0x55);
295
296 while(byte_index < bytes) {
297 int r = legic_read_byte(byte_index+offset, cmd_sz);
298 if(r == -1) {
299 Dbprintf("aborting");
300 switch_off_tag_rwd();
301 return;
302 }
303 ((uint8_t*)BigBuf)[byte_index] = r;
304 byte_index++;
305 }
306 switch_off_tag_rwd();
307 Dbprintf("Card read, use 'hf legic decode' or 'data hexsamples %d' to view results", (bytes+7) & ~7);
308 }
309
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