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1 //-----------------------------------------------------------------------------
2 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
3 // and the ARM. In the low-frequency modes it passes the data straight
4 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
5 // frequency modes, the FPGA might perform some demodulation first, to
6 // reduce the amount of data that we must send to the ARM.
7 //
8 // I am not really an FPGA/ASIC designer, so I am sure that a lot of this
9 // could be improved.
10 //
11 // Jonathan Westhues, March 2006
12 // iZsh <izsh at fail0verflow.com>, June 2014
13 //-----------------------------------------------------------------------------
14
15 `include "lo_read.v"
16 `include "lo_passthru.v"
17 `include "lo_edge_detect.v"
18 `include "util.v"
19 `include "clk_divider.v"
20
21 module fpga_lf(
22 input spck, output miso, input mosi, input ncs,
23 input pck0, input ck_1356meg, input ck_1356megb,
24 output pwr_lo, output pwr_hi,
25 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
26 input [7:0] adc_d, output adc_clk, output adc_noe,
27 output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
28 input cross_hi, input cross_lo,
29 output dbg
30 );
31
32 //-----------------------------------------------------------------------------
33 // The SPI receiver. This sets up the configuration word, which the rest of
34 // the logic looks at to determine how to connect the A/D and the coil
35 // drivers (i.e., which section gets it). Also assign some symbolic names
36 // to the configuration bits, for use below.
37 //-----------------------------------------------------------------------------
38
39 reg [15:0] shift_reg;
40 reg [7:0] divisor;
41 reg [7:0] conf_word;
42
43 // We switch modes between transmitting to the 13.56 MHz tag and receiving
44 // from it, which means that we must make sure that we can do so without
45 // glitching, or else we will glitch the transmitted carrier.
46 always @(posedge ncs)
47 begin
48 case(shift_reg[15:12])
49 4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
50 4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
51 endcase
52 end
53
54 always @(posedge spck)
55 begin
56 if(~ncs)
57 begin
58 shift_reg[15:1] <= shift_reg[14:0];
59 shift_reg[0] <= mosi;
60 end
61 end
62
63 wire [2:0] major_mode;
64 assign major_mode = conf_word[7:5];
65
66 // For the low-frequency configuration:
67 wire lf_field = conf_word[0];
68
69 //-----------------------------------------------------------------------------
70 // And then we instantiate the modules corresponding to each of the FPGA's
71 // major modes, and use muxes to connect the outputs of the active mode to
72 // the output pins.
73 //-----------------------------------------------------------------------------
74 wire [7:0] pck_cnt;
75 wire pck_divclk;
76 clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
77
78 lo_read lr(
79 pck0, pck_cnt, pck_divclk,
80 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
81 adc_d, lr_adc_clk,
82 lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
83 lr_dbg, lf_field
84 );
85
86 lo_passthru lp(
87 pck_divclk,
88 lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
89 lp_adc_clk,
90 lp_ssp_din, ssp_dout,
91 cross_lo,
92 lp_dbg
93 );
94
95 lo_edge_detect le(
96 pck0, pck_cnt, pck_divclk,
97 le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
98 adc_d, le_adc_clk,
99 le_ssp_frame, ssp_dout, le_ssp_clk,
100 cross_lo,
101 le_dbg,
102 lf_field
103 );
104
105 // Major modes:
106 // 000 -- LF reader (generic)
107 // 001 -- LF edge detect (generic)
108 // 010 -- LF passthrough
109
110 mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
111 mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
112 mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
113 mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
114 mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
115 mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
116 mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
117 mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
118 mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
119 mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
120 mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
121
122 // In all modes, let the ADC's outputs be enabled.
123 assign adc_noe = 1'b0;
124
125 endmodule
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