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REM: cleaning up some commented code.
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
26 * @param useHighFreg
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
30 {
31 /* Make sure the tag is reset */
32 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
33 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
34 SpinDelay(200);
35
36 uint16_t period_0 = periods >> 16;
37 uint16_t period_1 = periods & 0xFFFF;
38
39 // 95 == 125 KHz 88 == 124.8 KHz
40 int divisor_used = (useHighFreq) ? 88 : 95;
41 sample_config sc = { 0,0,1, divisor_used, 0};
42 setSamplingConfig(&sc);
43
44 //clear read buffer
45 BigBuf_Clear_keep_EM();
46
47 LFSetupFPGAForADC(sc.divisor, 1);
48
49 // And a little more time for the tag to fully power up
50 SpinDelay(50);
51
52 // now modulate the reader field
53 while(*command != '\0' && *command != ' ') {
54 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
55 LED_D_OFF();
56 SpinDelayUs(delay_off);
57 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
58
59 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
60 LED_D_ON();
61 if(*(command++) == '0')
62 SpinDelayUs(period_0);
63 else
64 SpinDelayUs(period_1);
65 }
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
67 LED_D_OFF();
68 SpinDelayUs(delay_off);
69 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74 }
75
76 /* blank r/w tag data stream
77 ...0000000000000000 01111111
78 1010101010101010101010101010101010101010101010101010101010101010
79 0011010010100001
80 01111111
81 101010101010101[0]000...
82
83 [5555fe852c5555555555555555fe0000]
84 */
85 void ReadTItag(void)
86 {
87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
94
95 signed char *dest = (signed char *)BigBuf_get_addr();
96 uint16_t n = BigBuf_max_traceLen();
97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
178 if (shift3 & (1<<15) ) {
179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
206 if (crc != (shift2&0xffff)) {
207 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
208 } else {
209 DbpString("Info: CRC is good");
210 }
211 }
212 }
213
214 void WriteTIbyte(uint8_t b)
215 {
216 int i = 0;
217
218 // modulate 8 bits out to the antenna
219 for (i=0; i<8; i++)
220 {
221 if (b&(1<<i)) {
222 // stop modulating antenna
223 LOW(GPIO_SSC_DOUT);
224 SpinDelayUs(1000);
225 // modulate antenna
226 HIGH(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 } else {
229 // stop modulating antenna
230 LOW(GPIO_SSC_DOUT);
231 SpinDelayUs(300);
232 // modulate antenna
233 HIGH(GPIO_SSC_DOUT);
234 SpinDelayUs(1700);
235 }
236 }
237 }
238
239 void AcquireTiType(void)
240 {
241 int i, j, n;
242 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
243 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
244 #define TIBUFLEN 1250
245
246 // clear buffer
247 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
248
249 //clear buffer now so it does not interfere with timing later
250 BigBuf_Clear_ext(false);
251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
288 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
299 n = TIBUFLEN * 32;
300
301 // unpack buffer
302 for (i = TIBUFLEN-1; i >= 0; i--) {
303 for (j = 0; j < 32; j++) {
304 if(buf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311 }
312
313 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314 // if crc provided, it will be written with the data verbatim (even if bogus)
315 // if not provided a valid crc will be computed from the data and written.
316 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317 {
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb first
352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
381 DbpString("Now use `lf ti read` to check");
382 }
383
384 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
385 {
386 int i;
387 uint8_t *tab = BigBuf_get_addr();
388
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
391
392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
395
396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
398
399 i = 0;
400 for(;;) {
401 //wait until SSC_CLK goes HIGH
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS() || usb_poll_validate_length() ) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409 if (ledcontrol) LED_D_ON();
410
411 if(tab[i])
412 OPEN_COIL();
413 else
414 SHORT_COIL();
415
416 if (ledcontrol) LED_D_OFF();
417
418 //wait until SSC_CLK goes LOW
419 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
420 if( BUTTON_PRESS() || usb_poll_validate_length() ) {
421 DbpString("Stopped");
422 return;
423 }
424 WDT_HIT();
425 }
426
427 i++;
428 if(i == period) {
429
430 i = 0;
431 if (gap) {
432 SHORT_COIL();
433 SpinDelayUs(gap);
434 }
435 }
436 }
437 }
438
439 #define DEBUG_FRAME_CONTENTS 1
440 void SimulateTagLowFrequencyBidir(int divisor, int t0)
441 {
442 }
443
444 // compose fc/8 fc/10 waveform (FSK2)
445 static void fc(int c, int *n)
446 {
447 uint8_t *dest = BigBuf_get_addr();
448 int idx;
449
450 // for when we want an fc8 pattern every 4 logical bits
451 if(c==0) {
452 dest[((*n)++)]=1;
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=0;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 }
461
462 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
463 if(c==8) {
464 for (idx=0; idx<6; idx++) {
465 dest[((*n)++)]=1;
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=0;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 }
474 }
475
476 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
477 if(c==10) {
478 for (idx=0; idx<5; idx++) {
479 dest[((*n)++)]=1;
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 }
490 }
491 }
492 // compose fc/X fc/Y waveform (FSKx)
493 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
494 {
495 uint8_t *dest = BigBuf_get_addr();
496 uint8_t halfFC = fc/2;
497 uint8_t wavesPerClock = clock/fc;
498 uint8_t mod = clock % fc; //modifier
499 uint8_t modAdj = fc/mod; //how often to apply modifier
500 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
501 // loop through clock - step field clock
502 for (uint8_t idx=0; idx < wavesPerClock; idx++){
503 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
504 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
505 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
506 *n += fc;
507 }
508 if (mod>0) (*modCnt)++;
509 if ((mod>0) && modAdjOk){ //fsk2
510 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
511 memset(dest+(*n), 0, fc-halfFC);
512 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
513 *n += fc;
514 }
515 }
516 if (mod>0 && !modAdjOk){ //fsk1
517 memset(dest+(*n), 0, mod-(mod/2));
518 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
519 *n += mod;
520 }
521 }
522
523 // prepare a waveform pattern in the buffer based on the ID given then
524 // simulate a HID tag until the button is pressed
525 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
526 {
527 int n=0, i=0;
528 /*
529 HID tag bitstream format
530 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
531 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
532 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
533 A fc8 is inserted before every 4 bits
534 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
535 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
536 */
537
538 if (hi>0xFFF) {
539 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
540 return;
541 }
542 fc(0,&n);
543 // special start of frame marker containing invalid bit sequences
544 fc(8, &n); fc(8, &n); // invalid
545 fc(8, &n); fc(10, &n); // logical 0
546 fc(10, &n); fc(10, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548
549 WDT_HIT();
550 // manchester encode bits 43 to 32
551 for (i=11; i>=0; i--) {
552 if ((i%4)==3) fc(0,&n);
553 if ((hi>>i)&1) {
554 fc(10, &n); fc(8, &n); // low-high transition
555 } else {
556 fc(8, &n); fc(10, &n); // high-low transition
557 }
558 }
559
560 WDT_HIT();
561 // manchester encode bits 31 to 0
562 for (i=31; i>=0; i--) {
563 if ((i%4)==3) fc(0,&n);
564 if ((lo>>i)&1) {
565 fc(10, &n); fc(8, &n); // low-high transition
566 } else {
567 fc(8, &n); fc(10, &n); // high-low transition
568 }
569 }
570
571 if (ledcontrol) LED_A_ON();
572 SimulateTagLowFrequency(n, 0, ledcontrol);
573 if (ledcontrol) LED_A_OFF();
574 }
575
576 // prepare a waveform pattern in the buffer based on the ID given then
577 // simulate a FSK tag until the button is pressed
578 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
579 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
580 {
581 int ledcontrol=1;
582 int n=0, i=0;
583 uint8_t fcHigh = arg1 >> 8;
584 uint8_t fcLow = arg1 & 0xFF;
585 uint16_t modCnt = 0;
586 uint8_t clk = arg2 & 0xFF;
587 uint8_t invert = (arg2 >> 8) & 1;
588
589 for (i=0; i<size; i++){
590 if (BitStream[i] == invert){
591 fcAll(fcLow, &n, clk, &modCnt);
592 } else {
593 fcAll(fcHigh, &n, clk, &modCnt);
594 }
595 }
596 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
597
598 if (ledcontrol) LED_A_ON();
599 SimulateTagLowFrequency(n, 0, ledcontrol);
600 if (ledcontrol) LED_A_OFF();
601 }
602
603 // compose ask waveform for one bit(ASK)
604 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
605 {
606 uint8_t *dest = BigBuf_get_addr();
607 uint8_t halfClk = clock/2;
608 // c = current bit 1 or 0
609 if (manchester==1){
610 memset(dest+(*n), c, halfClk);
611 memset(dest+(*n) + halfClk, c^1, halfClk);
612 } else {
613 memset(dest+(*n), c, clock);
614 }
615 *n += clock;
616 }
617
618 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
619 {
620 uint8_t *dest = BigBuf_get_addr();
621 uint8_t halfClk = clock/2;
622 if (c){
623 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
624 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
625 } else {
626 memset(dest+(*n), c ^ *phase, clock);
627 *phase ^= 1;
628 }
629 *n += clock;
630 }
631
632 static void stAskSimBit(int *n, uint8_t clock) {
633 uint8_t *dest = BigBuf_get_addr();
634 uint8_t halfClk = clock/2;
635 //ST = .5 high .5 low 1.5 high .5 low 1 high
636 memset(dest+(*n), 1, halfClk);
637 memset(dest+(*n) + halfClk, 0, halfClk);
638 memset(dest+(*n) + clock, 1, clock + halfClk);
639 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
640 memset(dest+(*n) + clock*3, 1, clock);
641 *n += clock*4;
642 }
643
644 // args clock, ask/man or askraw, invert, transmission separator
645 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
646 {
647 int ledcontrol = 1;
648 int n=0, i=0;
649 uint8_t clk = (arg1 >> 8) & 0xFF;
650 uint8_t encoding = arg1 & 0xFF;
651 uint8_t separator = arg2 & 1;
652 uint8_t invert = (arg2 >> 8) & 1;
653
654 if (encoding==2){ //biphase
655 uint8_t phase=0;
656 for (i=0; i<size; i++){
657 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
658 }
659 if (phase==1) { //run a second set inverted to keep phase in check
660 for (i=0; i<size; i++){
661 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
662 }
663 }
664 } else { // ask/manchester || ask/raw
665 for (i=0; i<size; i++){
666 askSimBit(BitStream[i]^invert, &n, clk, encoding);
667 }
668 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
669 for (i=0; i<size; i++){
670 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
671 }
672 }
673 }
674 if (separator==1 && encoding == 1)
675 stAskSimBit(&n, clk);
676 else if (separator==1)
677 Dbprintf("sorry but separator option not yet available");
678
679 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
680
681 if (ledcontrol) LED_A_ON();
682 SimulateTagLowFrequency(n, 0, ledcontrol);
683 if (ledcontrol) LED_A_OFF();
684 }
685
686 //carrier can be 2,4 or 8
687 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
688 {
689 uint8_t *dest = BigBuf_get_addr();
690 uint8_t halfWave = waveLen/2;
691 //uint8_t idx;
692 int i = 0;
693 if (phaseChg){
694 // write phase change
695 memset(dest+(*n), *curPhase^1, halfWave);
696 memset(dest+(*n) + halfWave, *curPhase, halfWave);
697 *n += waveLen;
698 *curPhase ^= 1;
699 i += waveLen;
700 }
701 //write each normal clock wave for the clock duration
702 for (; i < clk; i+=waveLen){
703 memset(dest+(*n), *curPhase, halfWave);
704 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
705 *n += waveLen;
706 }
707 }
708
709 // args clock, carrier, invert,
710 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
711 {
712 int ledcontrol = 1;
713 int n=0, i=0;
714 uint8_t clk = arg1 >> 8;
715 uint8_t carrier = arg1 & 0xFF;
716 uint8_t invert = arg2 & 0xFF;
717 uint8_t curPhase = 0;
718 for (i=0; i<size; i++){
719 if (BitStream[i] == curPhase){
720 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
721 } else {
722 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
723 }
724 }
725 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
726
727 if (ledcontrol) LED_A_ON();
728 SimulateTagLowFrequency(n, 0, ledcontrol);
729 if (ledcontrol) LED_A_OFF();
730 }
731
732 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
733 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
734 {
735 uint8_t *dest = BigBuf_get_addr();
736 size_t size = 0;
737 uint32_t hi2=0, hi=0, lo=0;
738 int idx=0;
739 // Configure to go in 125Khz listen mode
740 LFSetupFPGAForADC(95, true);
741
742 //clear read buffer
743 BigBuf_Clear_keep_EM();
744
745 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
746
747 WDT_HIT();
748 if (ledcontrol) LED_A_ON();
749
750 DoAcquisition_default(-1,true);
751 // FSK demodulator
752 size = 50*128*2; //big enough to catch 2 sequences of largest format
753 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
754
755 if (idx>0 && lo>0 && (size==96 || size==192)){
756 // go over previously decoded manchester data and decode into usable tag ID
757 if (hi2 != 0){ //extra large HID tags 88/192 bits
758 Dbprintf("TAG ID: %x%08x%08x (%d)",
759 (unsigned int) hi2,
760 (unsigned int) hi,
761 (unsigned int) lo,
762 (unsigned int) (lo>>1) & 0xFFFF
763 );
764 } else { //standard HID tags 44/96 bits
765 uint8_t bitlen = 0;
766 uint32_t fc = 0;
767 uint32_t cardnum = 0;
768
769 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
770 uint32_t lo2=0;
771 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
772 uint8_t idx3 = 1;
773 while(lo2 > 1){ //find last bit set to 1 (format len bit)
774 lo2=lo2 >> 1;
775 idx3++;
776 }
777 bitlen = idx3+19;
778 fc =0;
779 cardnum=0;
780 if(bitlen == 26){
781 cardnum = (lo>>1)&0xFFFF;
782 fc = (lo>>17)&0xFF;
783 }
784 if(bitlen == 37){
785 cardnum = (lo>>1)&0x7FFFF;
786 fc = ((hi&0xF)<<12)|(lo>>20);
787 }
788 if(bitlen == 34){
789 cardnum = (lo>>1)&0xFFFF;
790 fc= ((hi&1)<<15)|(lo>>17);
791 }
792 if(bitlen == 35){
793 cardnum = (lo>>1)&0xFFFFF;
794 fc = ((hi&1)<<11)|(lo>>21);
795 }
796 }
797 else { //if bit 38 is not set then 37 bit format is used
798 bitlen= 37;
799 fc =0;
800 cardnum=0;
801 if(bitlen==37){
802 cardnum = (lo>>1)&0x7FFFF;
803 fc = ((hi&0xF)<<12)|(lo>>20);
804 }
805 }
806 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
807 (unsigned int) hi,
808 (unsigned int) lo,
809 (unsigned int) (lo>>1) & 0xFFFF,
810 (unsigned int) bitlen,
811 (unsigned int) fc,
812 (unsigned int) cardnum);
813 }
814 if (findone){
815 if (ledcontrol) LED_A_OFF();
816 *high = hi;
817 *low = lo;
818 return;
819 }
820 // reset
821 }
822 hi2 = hi = lo = idx = 0;
823 WDT_HIT();
824 }
825 DbpString("Stopped");
826 if (ledcontrol) LED_A_OFF();
827 }
828
829 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
830 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
831 {
832 uint8_t *dest = BigBuf_get_addr();
833 size_t size;
834 int idx=0;
835 //clear read buffer
836 BigBuf_Clear_keep_EM();
837 // Configure to go in 125Khz listen mode
838 LFSetupFPGAForADC(95, true);
839
840 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
841
842 WDT_HIT();
843 if (ledcontrol) LED_A_ON();
844
845 DoAcquisition_default(-1,true);
846 // FSK demodulator
847 size = 50*128*2; //big enough to catch 2 sequences of largest format
848 idx = AWIDdemodFSK(dest, &size);
849
850 if (idx<=0 || size!=96) continue;
851 // Index map
852 // 0 10 20 30 40 50 60
853 // | | | | | | |
854 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
855 // -----------------------------------------------------------------------------
856 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
857 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
858 // |---26 bit---| |-----117----||-------------142-------------|
859 // b = format bit len, o = odd parity of last 3 bits
860 // f = facility code, c = card number
861 // w = wiegand parity
862 // (26 bit format shown)
863
864 //get raw ID before removing parities
865 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
866 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
867 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
868
869 size = removeParity(dest, idx+8, 4, 1, 88);
870 if (size != 66) continue;
871
872 // Index map
873 // 0 10 20 30 40 50 60
874 // | | | | | | |
875 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
876 // -----------------------------------------------------------------------------
877 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
878 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
879 // |26 bit| |-117--| |-----142------|
880 //
881 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
882 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
883 // |50 bit| |----4000------||-----------2248975-------------|
884 //
885 // b = format bit len, o = odd parity of last 3 bits
886 // f = facility code, c = card number
887 // w = wiegand parity
888
889 uint32_t fc = 0;
890 uint32_t cardnum = 0;
891 uint32_t code1 = 0;
892 uint32_t code2 = 0;
893 uint8_t fmtLen = bytebits_to_byte(dest,8);
894 switch(fmtLen) {
895 case 26:
896 fc = bytebits_to_byte(dest + 9, 8);
897 cardnum = bytebits_to_byte(dest + 17, 16);
898 code1 = bytebits_to_byte(dest + 8,fmtLen);
899 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
900 break;
901 case 50:
902 fc = bytebits_to_byte(dest + 9, 16);
903 cardnum = bytebits_to_byte(dest + 25, 32);
904 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
905 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
906 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
907 break;
908 default:
909 if (fmtLen > 32 ) {
910 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
911 code1 = bytebits_to_byte(dest+8,fmtLen-32);
912 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
913 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
914 } else {
915 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
916 code1 = bytebits_to_byte(dest+8,fmtLen);
917 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
918 }
919 break;
920 }
921 if (findone){
922 if (ledcontrol) LED_A_OFF();
923 return;
924 }
925 idx = 0;
926 WDT_HIT();
927 }
928 DbpString("Stopped");
929 if (ledcontrol) LED_A_OFF();
930 }
931
932 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
933 {
934 uint8_t *dest = BigBuf_get_addr();
935
936 size_t size=0, idx=0;
937 int clk=0, invert=0, errCnt=0, maxErr=20;
938 uint32_t hi=0;
939 uint64_t lo=0;
940 //clear read buffer
941 BigBuf_Clear_keep_EM();
942 // Configure to go in 125Khz listen mode
943 LFSetupFPGAForADC(95, true);
944
945 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
946
947 WDT_HIT();
948 if (ledcontrol) LED_A_ON();
949
950 DoAcquisition_default(-1,true);
951 size = BigBuf_max_traceLen();
952 //askdemod and manchester decode
953 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
954 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
955 WDT_HIT();
956
957 if (errCnt<0) continue;
958
959 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
960 if (errCnt){
961 if (size>64){
962 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
963 hi,
964 (uint32_t)(lo>>32),
965 (uint32_t)lo,
966 (uint32_t)(lo&0xFFFF),
967 (uint32_t)((lo>>16LL) & 0xFF),
968 (uint32_t)(lo & 0xFFFFFF));
969 } else {
970 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
971 (uint32_t)(lo>>32),
972 (uint32_t)lo,
973 (uint32_t)(lo&0xFFFF),
974 (uint32_t)((lo>>16LL) & 0xFF),
975 (uint32_t)(lo & 0xFFFFFF));
976 }
977
978 if (findone){
979 if (ledcontrol) LED_A_OFF();
980 *high=lo>>32;
981 *low=lo & 0xFFFFFFFF;
982 return;
983 }
984 }
985 WDT_HIT();
986 hi = lo = size = idx = 0;
987 clk = invert = errCnt = 0;
988 }
989 DbpString("Stopped");
990 if (ledcontrol) LED_A_OFF();
991 }
992
993 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
994 {
995 uint8_t *dest = BigBuf_get_addr();
996 int idx=0;
997 uint32_t code=0, code2=0;
998 uint8_t version=0;
999 uint8_t facilitycode=0;
1000 uint16_t number=0;
1001 uint8_t crc = 0;
1002 uint16_t calccrc = 0;
1003
1004 //clear read buffer
1005 BigBuf_Clear_keep_EM();
1006
1007 // Configure to go in 125Khz listen mode
1008 LFSetupFPGAForADC(95, true);
1009
1010 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1011 WDT_HIT();
1012 if (ledcontrol) LED_A_ON();
1013 DoAcquisition_default(-1,true);
1014 //fskdemod and get start index
1015 WDT_HIT();
1016 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1017 if (idx<0) continue;
1018 //valid tag found
1019
1020 //Index map
1021 //0 10 20 30 40 50 60
1022 //| | | | | | |
1023 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1024 //-----------------------------------------------------------------------------
1025 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1026 //
1027 //Checksum:
1028 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1029 //preamble F0 E0 01 03 B6 75
1030 // How to calc checksum,
1031 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1032 // F0 + E0 + 01 + 03 + B6 = 28A
1033 // 28A & FF = 8A
1034 // FF - 8A = 75
1035 // Checksum: 0x75
1036 //XSF(version)facility:codeone+codetwo
1037 //Handle the data
1038 if(findone){ //only print binary if we are doing one
1039 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1040 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1041 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1042 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1043 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1044 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1045 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1046 }
1047 code = bytebits_to_byte(dest+idx,32);
1048 code2 = bytebits_to_byte(dest+idx+32,32);
1049 version = bytebits_to_byte(dest+idx+27,8); //14,4
1050 facilitycode = bytebits_to_byte(dest+idx+18,8);
1051 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1052
1053 crc = bytebits_to_byte(dest+idx+54,8);
1054 for (uint8_t i=1; i<6; ++i)
1055 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1056 calccrc &= 0xff;
1057 calccrc = 0xff - calccrc;
1058
1059 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1060
1061 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1062 // if we're only looking for one tag
1063 if (findone){
1064 if (ledcontrol) LED_A_OFF();
1065 *high=code;
1066 *low=code2;
1067 return;
1068 }
1069 code=code2=0;
1070 version=facilitycode=0;
1071 number=0;
1072 idx=0;
1073
1074 WDT_HIT();
1075 }
1076 DbpString("Stopped");
1077 if (ledcontrol) LED_A_OFF();
1078 }
1079
1080 /*------------------------------
1081 * T5555/T5557/T5567/T5577 routines
1082 *------------------------------
1083 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1084 *
1085 * Relevant communication times in microsecond
1086 * To compensate antenna falling times shorten the write times
1087 * and enlarge the gap ones.
1088 * Q5 tags seems to have issues when these values changes.
1089 */
1090
1091 #define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1092 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1093 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1094 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1095 #define READ_GAP 15*8
1096
1097 // VALUES TAKEN FROM EM4x function: SendForward
1098 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1099 // WRITE_GAP = 128; (16*8)
1100 // WRITE_1 = 256 32*8; (32*8)
1101
1102 // These timings work for 4469/4269/4305 (with the 55*8 above)
1103 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1104
1105 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1106 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1107 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1108 // T0 = TIMER_CLOCK1 / 125000 = 192
1109 // 1 Cycle = 8 microseconds(us) == 1 field clock
1110
1111 void TurnReadLFOn(int delay) {
1112 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1113 // Give it a bit of time for the resonant antenna to settle.
1114
1115 // measure antenna strength.
1116 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1117 // where to save it
1118
1119 SpinDelayUs(delay);
1120 }
1121
1122 // Write one bit to card
1123 void T55xxWriteBit(int bit) {
1124 if (!bit)
1125 TurnReadLFOn(WRITE_0);
1126 else
1127 TurnReadLFOn(WRITE_1);
1128 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1129 SpinDelayUs(WRITE_GAP);
1130 }
1131
1132 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1133 void T55xxResetRead(void) {
1134 LED_A_ON();
1135 //clear buffer now so it does not interfere with timing later
1136 BigBuf_Clear_keep_EM();
1137
1138 // Set up FPGA, 125kHz
1139 LFSetupFPGAForADC(95, true);
1140
1141 // Trigger T55x7 in mode.
1142 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1143 SpinDelayUs(START_GAP);
1144
1145 // reset tag - op code 00
1146 T55xxWriteBit(0);
1147 T55xxWriteBit(0);
1148
1149 // Turn field on to read the response
1150 TurnReadLFOn(READ_GAP);
1151
1152 // Acquisition
1153 doT55x7Acquisition(BigBuf_max_traceLen());
1154
1155 // Turn the field off
1156 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1157 cmd_send(CMD_ACK,0,0,0,0,0);
1158 LED_A_OFF();
1159 }
1160
1161 // Write one card block in page 0, no lock
1162 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1163 LED_A_ON();
1164 bool PwdMode = arg & 0x1;
1165 uint8_t Page = (arg & 0x2)>>1;
1166 uint32_t i = 0;
1167
1168 // Set up FPGA, 125kHz
1169 LFSetupFPGAForADC(95, true);
1170
1171 // Trigger T55x7 in mode.
1172 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1173 SpinDelayUs(START_GAP);
1174
1175 // Opcode 10
1176 T55xxWriteBit(1);
1177 T55xxWriteBit(Page); //Page 0
1178 if (PwdMode){
1179 // Send Pwd
1180 for (i = 0x80000000; i != 0; i >>= 1)
1181 T55xxWriteBit(Pwd & i);
1182 }
1183 // Send Lock bit
1184 T55xxWriteBit(0);
1185
1186 // Send Data
1187 for (i = 0x80000000; i != 0; i >>= 1)
1188 T55xxWriteBit(Data & i);
1189
1190 // Send Block number
1191 for (i = 0x04; i != 0; i >>= 1)
1192 T55xxWriteBit(Block & i);
1193
1194 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1195 // so wait a little more)
1196 TurnReadLFOn(20 * 1000);
1197 //could attempt to do a read to confirm write took
1198 // as the tag should repeat back the new block
1199 // until it is reset, but to confirm it we would
1200 // need to know the current block 0 config mode
1201
1202 // turn field off
1203 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1204 LED_A_OFF();
1205 }
1206
1207 // Write one card block in page 0, no lock
1208 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1209 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1210 cmd_send(CMD_ACK,0,0,0,0,0);
1211 }
1212
1213 // Read one card block in page [page]
1214 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1215 LED_A_ON();
1216 bool PwdMode = arg0 & 0x1;
1217 uint8_t Page = (arg0 & 0x2) >> 1;
1218 uint32_t i = 0;
1219 bool RegReadMode = (Block == 0xFF);
1220
1221 //clear buffer now so it does not interfere with timing later
1222 BigBuf_Clear_ext(false);
1223
1224 //make sure block is at max 7
1225 Block &= 0x7;
1226
1227 // Set up FPGA, 125kHz to power up the tag
1228 LFSetupFPGAForADC(95, true);
1229
1230 // Trigger T55x7 Direct Access Mode with start gap
1231 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1232 SpinDelayUs(START_GAP);
1233
1234 // Opcode 1[page]
1235 T55xxWriteBit(1);
1236 T55xxWriteBit(Page); //Page 0
1237
1238 if (PwdMode){
1239 // Send Pwd
1240 for (i = 0x80000000; i != 0; i >>= 1)
1241 T55xxWriteBit(Pwd & i);
1242 }
1243 // Send a zero bit separation
1244 T55xxWriteBit(0);
1245
1246 // Send Block number (if direct access mode)
1247 if (!RegReadMode)
1248 for (i = 0x04; i != 0; i >>= 1)
1249 T55xxWriteBit(Block & i);
1250
1251 // Turn field on to read the response
1252 TurnReadLFOn(READ_GAP);
1253
1254 // Acquisition
1255 doT55x7Acquisition(12000);
1256
1257 // Turn the field off
1258 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1259 cmd_send(CMD_ACK,0,0,0,0,0);
1260 LED_A_OFF();
1261 }
1262
1263 void T55xxWakeUp(uint32_t Pwd){
1264 LED_B_ON();
1265 uint32_t i = 0;
1266
1267 // Set up FPGA, 125kHz
1268 LFSetupFPGAForADC(95, true);
1269
1270 // Trigger T55x7 Direct Access Mode
1271 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1272 SpinDelayUs(START_GAP);
1273
1274 // Opcode 10
1275 T55xxWriteBit(1);
1276 T55xxWriteBit(0); //Page 0
1277
1278 // Send Pwd
1279 for (i = 0x80000000; i != 0; i >>= 1)
1280 T55xxWriteBit(Pwd & i);
1281
1282 // Turn and leave field on to let the begin repeating transmission
1283 TurnReadLFOn(20*1000);
1284 }
1285
1286 /*-------------- Cloning routines -----------*/
1287 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1288 // write last block first and config block last (if included)
1289 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1290 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1291 }
1292
1293 // Copy HID id to card and setup block 0 config
1294 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1295 uint32_t data[] = {0,0,0,0,0,0,0};
1296 uint8_t last_block = 0;
1297
1298 if (longFMT){
1299 // Ensure no more than 84 bits supplied
1300 if (hi2 > 0xFFFFF) {
1301 DbpString("Tags can only have 84 bits.");
1302 return;
1303 }
1304 // Build the 6 data blocks for supplied 84bit ID
1305 last_block = 6;
1306 // load preamble (1D) & long format identifier (9E manchester encoded)
1307 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1308 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1309 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1310 data[3] = manchesterEncode2Bytes(hi >> 16);
1311 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1312 data[5] = manchesterEncode2Bytes(lo >> 16);
1313 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1314 } else {
1315 // Ensure no more than 44 bits supplied
1316 if (hi > 0xFFF) {
1317 DbpString("Tags can only have 44 bits.");
1318 return;
1319 }
1320 // Build the 3 data blocks for supplied 44bit ID
1321 last_block = 3;
1322 // load preamble
1323 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1324 data[2] = manchesterEncode2Bytes(lo >> 16);
1325 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1326 }
1327 // load chip config block
1328 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1329
1330 //TODO add selection of chip for Q5 or T55x7
1331 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1332
1333 LED_D_ON();
1334 // Program the data blocks for supplied ID
1335 // and the block 0 for HID format
1336 WriteT55xx(data, 0, last_block+1);
1337
1338 LED_D_OFF();
1339
1340 DbpString("DONE!");
1341 }
1342
1343 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1344 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1345 //TODO add selection of chip for Q5 or T55x7
1346 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1347 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1348
1349 LED_D_ON();
1350 // Program the data blocks for supplied ID
1351 // and the block 0 config
1352 WriteT55xx(data, 0, 3);
1353 LED_D_OFF();
1354 DbpString("DONE!");
1355 }
1356
1357 // Clone Indala 64-bit tag by UID to T55x7
1358 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1359 //Program the 2 data blocks for supplied 64bit UID
1360 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1361 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1362 //TODO add selection of chip for Q5 or T55x7
1363 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1364
1365 WriteT55xx(data, 0, 3);
1366 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1367 // T5567WriteBlock(0x603E1042,0);
1368 DbpString("DONE!");
1369 }
1370 // Clone Indala 224-bit tag by UID to T55x7
1371 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1372 //Program the 7 data blocks for supplied 224bit UID
1373 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1374 // and the block 0 for Indala224 format
1375 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1376 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1377 //TODO add selection of chip for Q5 or T55x7
1378 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1379 WriteT55xx(data, 0, 8);
1380 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1381 // T5567WriteBlock(0x603E10E2,0);
1382 DbpString("DONE!");
1383 }
1384 // clone viking tag to T55xx
1385 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1386 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1387 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1388 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1389 // Program the data blocks for supplied ID and the block 0 config
1390 WriteT55xx(data, 0, 3);
1391 LED_D_OFF();
1392 cmd_send(CMD_ACK,0,0,0,0,0);
1393 }
1394
1395 // Define 9bit header for EM410x tags
1396 #define EM410X_HEADER 0x1FF
1397 #define EM410X_ID_LENGTH 40
1398
1399 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1400 int i, id_bit;
1401 uint64_t id = EM410X_HEADER;
1402 uint64_t rev_id = 0; // reversed ID
1403 int c_parity[4]; // column parity
1404 int r_parity = 0; // row parity
1405 uint32_t clock = 0;
1406
1407 // Reverse ID bits given as parameter (for simpler operations)
1408 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1409 if (i < 32) {
1410 rev_id = (rev_id << 1) | (id_lo & 1);
1411 id_lo >>= 1;
1412 } else {
1413 rev_id = (rev_id << 1) | (id_hi & 1);
1414 id_hi >>= 1;
1415 }
1416 }
1417
1418 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1419 id_bit = rev_id & 1;
1420
1421 if (i % 4 == 0) {
1422 // Don't write row parity bit at start of parsing
1423 if (i)
1424 id = (id << 1) | r_parity;
1425 // Start counting parity for new row
1426 r_parity = id_bit;
1427 } else {
1428 // Count row parity
1429 r_parity ^= id_bit;
1430 }
1431
1432 // First elements in column?
1433 if (i < 4)
1434 // Fill out first elements
1435 c_parity[i] = id_bit;
1436 else
1437 // Count column parity
1438 c_parity[i % 4] ^= id_bit;
1439
1440 // Insert ID bit
1441 id = (id << 1) | id_bit;
1442 rev_id >>= 1;
1443 }
1444
1445 // Insert parity bit of last row
1446 id = (id << 1) | r_parity;
1447
1448 // Fill out column parity at the end of tag
1449 for (i = 0; i < 4; ++i)
1450 id = (id << 1) | c_parity[i];
1451
1452 // Add stop bit
1453 id <<= 1;
1454
1455 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1456 LED_D_ON();
1457
1458 // Write EM410x ID
1459 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1460
1461 clock = (card & 0xFF00) >> 8;
1462 clock = (clock == 0) ? 64 : clock;
1463 Dbprintf("Clock rate: %d", clock);
1464 if (card & 0xFF) { //t55x7
1465 clock = GetT55xxClockBit(clock);
1466 if (clock == 0) {
1467 Dbprintf("Invalid clock rate: %d", clock);
1468 return;
1469 }
1470 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1471 } else { //t5555 (Q5)
1472 clock = (clock-2)>>1; //n = (RF-2)/2
1473 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1474 }
1475
1476 WriteT55xx(data, 0, 3);
1477
1478 LED_D_OFF();
1479 Dbprintf("Tag %s written with 0x%08x%08x\n",
1480 card ? "T55x7":"T5555",
1481 (uint32_t)(id >> 32),
1482 (uint32_t)id);
1483 }
1484
1485 //-----------------------------------
1486 // EM4469 / EM4305 routines
1487 //-----------------------------------
1488 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1489 #define FWD_CMD_WRITE 0xA
1490 #define FWD_CMD_READ 0x9
1491 #define FWD_CMD_DISABLE 0x5
1492
1493 uint8_t forwardLink_data[64]; //array of forwarded bits
1494 uint8_t * forward_ptr; //ptr for forward message preparation
1495 uint8_t fwd_bit_sz; //forwardlink bit counter
1496 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1497
1498 //====================================================================
1499 // prepares command bits
1500 // see EM4469 spec
1501 //====================================================================
1502 //--------------------------------------------------------------------
1503 // VALUES TAKEN FROM EM4x function: SendForward
1504 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1505 // WRITE_GAP = 128; (16*8)
1506 // WRITE_1 = 256 32*8; (32*8)
1507
1508 // These timings work for 4469/4269/4305 (with the 55*8 above)
1509 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1510
1511 uint8_t Prepare_Cmd( uint8_t cmd ) {
1512
1513 *forward_ptr++ = 0; //start bit
1514 *forward_ptr++ = 0; //second pause for 4050 code
1515
1516 *forward_ptr++ = cmd;
1517 cmd >>= 1;
1518 *forward_ptr++ = cmd;
1519 cmd >>= 1;
1520 *forward_ptr++ = cmd;
1521 cmd >>= 1;
1522 *forward_ptr++ = cmd;
1523
1524 return 6; //return number of emited bits
1525 }
1526
1527 //====================================================================
1528 // prepares address bits
1529 // see EM4469 spec
1530 //====================================================================
1531 uint8_t Prepare_Addr( uint8_t addr ) {
1532
1533 register uint8_t line_parity;
1534
1535 uint8_t i;
1536 line_parity = 0;
1537 for(i=0;i<6;i++) {
1538 *forward_ptr++ = addr;
1539 line_parity ^= addr;
1540 addr >>= 1;
1541 }
1542
1543 *forward_ptr++ = (line_parity & 1);
1544
1545 return 7; //return number of emited bits
1546 }
1547
1548 //====================================================================
1549 // prepares data bits intreleaved with parity bits
1550 // see EM4469 spec
1551 //====================================================================
1552 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1553
1554 register uint8_t line_parity;
1555 register uint8_t column_parity;
1556 register uint8_t i, j;
1557 register uint16_t data;
1558
1559 data = data_low;
1560 column_parity = 0;
1561
1562 for(i=0; i<4; i++) {
1563 line_parity = 0;
1564 for(j=0; j<8; j++) {
1565 line_parity ^= data;
1566 column_parity ^= (data & 1) << j;
1567 *forward_ptr++ = data;
1568 data >>= 1;
1569 }
1570 *forward_ptr++ = line_parity;
1571 if(i == 1)
1572 data = data_hi;
1573 }
1574
1575 for(j=0; j<8; j++) {
1576 *forward_ptr++ = column_parity;
1577 column_parity >>= 1;
1578 }
1579 *forward_ptr = 0;
1580
1581 return 45; //return number of emited bits
1582 }
1583
1584 //====================================================================
1585 // Forward Link send function
1586 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1587 // fwd_bit_count set with number of bits to be sent
1588 //====================================================================
1589 void SendForward(uint8_t fwd_bit_count) {
1590
1591 fwd_write_ptr = forwardLink_data;
1592 fwd_bit_sz = fwd_bit_count;
1593
1594 LED_D_ON();
1595
1596 // Set up FPGA, 125kHz
1597 LFSetupFPGAForADC(95, true);
1598
1599 // force 1st mod pulse (start gap must be longer for 4305)
1600 fwd_bit_sz--; //prepare next bit modulation
1601 fwd_write_ptr++;
1602 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1603 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1604 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1605 SpinDelayUs(16*8); //16 cycles on (8us each)
1606
1607 // now start writting
1608 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1609 if(((*fwd_write_ptr++) & 1) == 1)
1610 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1611 else {
1612 //These timings work for 4469/4269/4305 (with the 55*8 above)
1613 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1614 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1615 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1616 SpinDelayUs(9*8); //16 cycles on (8us each)
1617 }
1618 }
1619 }
1620
1621 void EM4xLogin(uint32_t Password) {
1622
1623 uint8_t fwd_bit_count;
1624
1625 forward_ptr = forwardLink_data;
1626 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1627 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1628
1629 SendForward(fwd_bit_count);
1630
1631 //Wait for command to complete
1632 SpinDelay(20);
1633 }
1634
1635 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1636
1637 uint8_t fwd_bit_count;
1638 uint8_t *dest = BigBuf_get_addr();
1639 uint16_t bufsize = BigBuf_max_traceLen();
1640 uint32_t i = 0;
1641
1642 // Clear destination buffer before sending the command
1643 BigBuf_Clear_ext(false);
1644
1645 //If password mode do login
1646 if (PwdMode == 1) EM4xLogin(Pwd);
1647
1648 forward_ptr = forwardLink_data;
1649 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1650 fwd_bit_count += Prepare_Addr( Address );
1651
1652 // Connect the A/D to the peak-detected low-frequency path.
1653 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1654 // Now set up the SSC to get the ADC samples that are now streaming at us.
1655 FpgaSetupSsc();
1656
1657 SendForward(fwd_bit_count);
1658
1659 // Now do the acquisition
1660 i = 0;
1661 for(;;) {
1662 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1663 AT91C_BASE_SSC->SSC_THR = 0x43;
1664 }
1665 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1666 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1667 ++i;
1668 if (i >= bufsize) break;
1669 }
1670 }
1671
1672 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1673 cmd_send(CMD_ACK,0,0,0,0,0);
1674 LED_D_OFF();
1675 }
1676
1677 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1678
1679 uint8_t fwd_bit_count;
1680
1681 //If password mode do login
1682 if (PwdMode == 1) EM4xLogin(Pwd);
1683
1684 forward_ptr = forwardLink_data;
1685 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1686 fwd_bit_count += Prepare_Addr( Address );
1687 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1688
1689 SendForward(fwd_bit_count);
1690
1691 //Wait for write to complete
1692 SpinDelay(20);
1693 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1694 LED_D_OFF();
1695 }
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