3 pck0 - input main 24Mhz clock (PLL / 4)
4 [7:0] adc_d - input data from A/D converter
5 lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
7 pwr_lo - output to coil drivers (ssp_clk / 8)
8 adc_clk - output A/D clock signal
9 ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
10 ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
11 ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
13 ck_1356meg - input unused
14 ck_1356megb - input unused
15 ssp_dout - input unused
16 cross_hi - input unused
17 cross_lo - input unused
19 pwr_hi - output unused, tied low
20 pwr_oe1 - output unused, undefined
21 pwr_oe2 - output unused, undefined
22 pwr_oe3 - output unused, undefined
23 pwr_oe4 - output unused, undefined
24 dbg - output alias for adc_clk
27 module testbed_lo_read;
52 .ck_1356meg(ck_1356meg),
53 .ck_1356megb(ck_1356megb),
62 .ssp_frame(ssp_frame),
69 .lo_is_125khz(lo_is_125khz),
73 integer idx, i, adc_val=8;
76 always #5 pck0 = !pck0;
82 adc_val = (adc_val *2) + 53;
93 divisor = 255; //min 16, 95=125Khz, max 255
95 // simulate 4 A/D cycles at 125Khz
96 for (i = 0 ; i < 8 ; i = i + 1) begin