1 `include "lo_simulate.v"
4 pck0 - input main 24Mhz clock (PLL / 4)
5 [7:0] adc_d - input data from A/D converter
8 pwr_lo - output to coil drivers (ssp_clk / 8)
9 adc_clk - output A/D clock signal
10 ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
11 ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
12 ssp_clk - output SSP clock signal
14 ck_1356meg - input unused
15 ck_1356megb - input unused
16 ssp_dout - input unused
17 cross_hi - input unused
18 cross_lo - input unused
20 pwr_hi - output unused, tied low
21 pwr_oe1 - output unused, undefined
22 pwr_oe2 - output unused, undefined
23 pwr_oe3 - output unused, undefined
24 pwr_oe4 - output unused, undefined
25 dbg - output alias for adc_clk
28 module testbed_lo_simulate;
50 lo_simulate #(5,200) dut(
52 .ck_1356meg(ck_1356meg),
53 .ck_1356megb(ck_1356megb),
62 .ssp_frame(ssp_frame),
75 always #5 pck0 = !pck0;
77 //cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)
81 counter = counter + 1;
82 if (counter == 192) begin
95 for (i = 0 ; i < 4096 ; i = i + 1) begin