]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
CHG: removed a -L path for OSX
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 #ifndef SHORT_COIL
23 # define SHORT_COIL() LOW(GPIO_SSC_DOUT)
24 #endif
25 #ifndef OPEN_COIL
26 # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
27 #endif
28
29 /**
30 * Function to do a modulation and then get samples.
31 * @param delay_off
32 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
33 * @param useHighFreg
34 * @param command
35 */
36 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
37 {
38 /* Make sure the tag is reset */
39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
41 SpinDelay(200);
42
43 uint16_t period_0 = periods >> 16;
44 uint16_t period_1 = periods & 0xFFFF;
45
46 // 95 == 125 KHz 88 == 124.8 KHz
47 int divisor_used = (useHighFreq) ? 88 : 95;
48 sample_config sc = { 0,0,1, divisor_used, 0};
49 setSamplingConfig(&sc);
50
51 //clear read buffer
52 BigBuf_Clear_keep_EM();
53
54 LFSetupFPGAForADC(sc.divisor, 1);
55
56 // And a little more time for the tag to fully power up
57 SpinDelay(50);
58
59 // now modulate the reader field
60 while(*command != '\0' && *command != ' ') {
61 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
62 LED_D_OFF();
63 WaitUS(delay_off);
64 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
65
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
67 LED_D_ON();
68 if(*(command++) == '0')
69 WaitUS(period_0);
70 else
71 WaitUS(period_1);
72 }
73 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
74 LED_D_OFF();
75 WaitUS(delay_off);
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
78
79 // now do the read
80 DoAcquisition_config(false);
81 }
82
83 /* blank r/w tag data stream
84 ...0000000000000000 01111111
85 1010101010101010101010101010101010101010101010101010101010101010
86 0011010010100001
87 01111111
88 101010101010101[0]000...
89
90 [5555fe852c5555555555555555fe0000]
91 */
92 void ReadTItag(void)
93 {
94 StartTicks();
95 // some hardcoded initial params
96 // when we read a TI tag we sample the zerocross line at 2Mhz
97 // TI tags modulate a 1 as 16 cycles of 123.2Khz
98 // TI tags modulate a 0 as 16 cycles of 134.2Khz
99 #define FSAMPLE 2000000
100 #define FREQLO 123200
101 #define FREQHI 134200
102
103 signed char *dest = (signed char *)BigBuf_get_addr();
104 uint16_t n = BigBuf_max_traceLen();
105 // 128 bit shift register [shift3:shift2:shift1:shift0]
106 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
107
108 int i, cycles=0, samples=0;
109 // how many sample points fit in 16 cycles of each frequency
110 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
111 // when to tell if we're close enough to one freq or another
112 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
113
114 // TI tags charge at 134.2Khz
115 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
117
118 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
119 // connects to SSP_DIN and the SSP_DOUT logic level controls
120 // whether we're modulating the antenna (high)
121 // or listening to the antenna (low)
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
123
124 // get TI tag data into the buffer
125 AcquireTiType();
126
127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
128
129 for (i=0; i<n-1; i++) {
130 // count cycles by looking for lo to hi zero crossings
131 if ( (dest[i]<0) && (dest[i+1]>0) ) {
132 cycles++;
133 // after 16 cycles, measure the frequency
134 if (cycles>15) {
135 cycles=0;
136 samples=i-samples; // number of samples in these 16 cycles
137
138 // TI bits are coming to us lsb first so shift them
139 // right through our 128 bit right shift register
140 shift0 = (shift0>>1) | (shift1 << 31);
141 shift1 = (shift1>>1) | (shift2 << 31);
142 shift2 = (shift2>>1) | (shift3 << 31);
143 shift3 >>= 1;
144
145 // check if the cycles fall close to the number
146 // expected for either the low or high frequency
147 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
148 // low frequency represents a 1
149 shift3 |= (1<<31);
150 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
151 // high frequency represents a 0
152 } else {
153 // probably detected a gay waveform or noise
154 // use this as gaydar or discard shift register and start again
155 shift3 = shift2 = shift1 = shift0 = 0;
156 }
157 samples = i;
158
159 // for each bit we receive, test if we've detected a valid tag
160
161 // if we see 17 zeroes followed by 6 ones, we might have a tag
162 // remember the bits are backwards
163 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
164 // if start and end bytes match, we have a tag so break out of the loop
165 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
166 cycles = 0xF0B; //use this as a flag (ugly but whatever)
167 break;
168 }
169 }
170 }
171 }
172 }
173
174 // if flag is set we have a tag
175 if (cycles!=0xF0B) {
176 DbpString("Info: No valid tag detected.");
177 } else {
178 // put 64 bit data into shift1 and shift0
179 shift0 = (shift0>>24) | (shift1 << 8);
180 shift1 = (shift1>>24) | (shift2 << 8);
181
182 // align 16 bit crc into lower half of shift2
183 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
184
185 // if r/w tag, check ident match
186 if (shift3 & (1<<15) ) {
187 DbpString("Info: TI tag is rewriteable");
188 // only 15 bits compare, last bit of ident is not valid
189 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
190 DbpString("Error: Ident mismatch!");
191 } else {
192 DbpString("Info: TI tag ident is valid");
193 }
194 } else {
195 DbpString("Info: TI tag is readonly");
196 }
197
198 // WARNING the order of the bytes in which we calc crc below needs checking
199 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
200 // bytes in reverse or something
201 // calculate CRC
202 uint32_t crc=0;
203
204 crc = update_crc16(crc, (shift0)&0xff);
205 crc = update_crc16(crc, (shift0>>8)&0xff);
206 crc = update_crc16(crc, (shift0>>16)&0xff);
207 crc = update_crc16(crc, (shift0>>24)&0xff);
208 crc = update_crc16(crc, (shift1)&0xff);
209 crc = update_crc16(crc, (shift1>>8)&0xff);
210 crc = update_crc16(crc, (shift1>>16)&0xff);
211 crc = update_crc16(crc, (shift1>>24)&0xff);
212
213 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
214 if (crc != (shift2&0xffff)) {
215 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
216 } else {
217 DbpString("Info: CRC is good");
218 }
219 }
220 StopTicks();
221 }
222
223 void WriteTIbyte(uint8_t b)
224 {
225 int i = 0;
226
227 // modulate 8 bits out to the antenna
228 for (i=0; i<8; i++)
229 {
230 if ( b & ( 1 << i ) ) {
231 // stop modulating antenna 1ms
232 LOW(GPIO_SSC_DOUT);
233 WaitUS(1000);
234 // modulate antenna 1ms
235 HIGH(GPIO_SSC_DOUT);
236 WaitUS(1000);
237 } else {
238 // stop modulating antenna 1ms
239 LOW(GPIO_SSC_DOUT);
240 WaitUS(300);
241 // modulate antenna 1m
242 HIGH(GPIO_SSC_DOUT);
243 WaitUS(1700);
244 }
245 }
246 }
247
248 void AcquireTiType(void)
249 {
250 int i, j, n;
251 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
252 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
253 #define TIBUFLEN 1250
254
255 // clear buffer
256 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
257
258 //clear buffer now so it does not interfere with timing later
259 BigBuf_Clear_ext(false);
260
261 // Set up the synchronous serial port
262 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
263 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
264
265 // steal this pin from the SSP and use it to control the modulation
266 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
267 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
268
269 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
270 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
271
272 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
273 // 48/2 = 24 MHz clock must be divided by 12
274 AT91C_BASE_SSC->SSC_CMR = 12;
275
276 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
277 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
278 AT91C_BASE_SSC->SSC_TCMR = 0;
279 AT91C_BASE_SSC->SSC_TFMR = 0;
280 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
281 LED_D_ON();
282
283 // modulate antenna
284 HIGH(GPIO_SSC_DOUT);
285
286 // Charge TI tag for 50ms.
287 WaitMS(50);
288
289 // stop modulating antenna and listen
290 LOW(GPIO_SSC_DOUT);
291
292 LED_D_OFF();
293
294 i = 0;
295 for(;;) {
296 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
297 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
298 i++; if(i >= TIBUFLEN) break;
299 }
300 WDT_HIT();
301 }
302
303 // return stolen pin to SSP
304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
306
307 char *dest = (char *)BigBuf_get_addr();
308 n = TIBUFLEN * 32;
309
310 // unpack buffer
311 for (i = TIBUFLEN-1; i >= 0; i--) {
312 for (j = 0; j < 32; j++) {
313 if(buf[i] & (1 << j)) {
314 dest[--n] = 1;
315 } else {
316 dest[--n] = -1;
317 }
318 }
319 }
320 }
321
322 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
323 // if crc provided, it will be written with the data verbatim (even if bogus)
324 // if not provided a valid crc will be computed from the data and written.
325 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
326 {
327 StartTicks();
328 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
329 if(crc == 0) {
330 crc = update_crc16(crc, (idlo)&0xff);
331 crc = update_crc16(crc, (idlo>>8)&0xff);
332 crc = update_crc16(crc, (idlo>>16)&0xff);
333 crc = update_crc16(crc, (idlo>>24)&0xff);
334 crc = update_crc16(crc, (idhi)&0xff);
335 crc = update_crc16(crc, (idhi>>8)&0xff);
336 crc = update_crc16(crc, (idhi>>16)&0xff);
337 crc = update_crc16(crc, (idhi>>24)&0xff);
338 }
339 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
340
341 // TI tags charge at 134.2Khz
342 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
343 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
344 // connects to SSP_DIN and the SSP_DOUT logic level controls
345 // whether we're modulating the antenna (high)
346 // or listening to the antenna (low)
347 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
348 LED_A_ON();
349
350 // steal this pin from the SSP and use it to control the modulation
351 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
352 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
353
354 // writing algorithm:
355 // a high bit consists of a field off for 1ms and field on for 1ms
356 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
357 // initiate a charge time of 50ms (field on) then immediately start writing bits
358 // start by writing 0xBB (keyword) and 0xEB (password)
359 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
360 // finally end with 0x0300 (write frame)
361 // all data is sent lsb first
362 // finish with 15ms programming time
363
364 // modulate antenna
365 HIGH(GPIO_SSC_DOUT);
366 WaitMS(50); // charge time
367
368 WriteTIbyte(0xbb); // keyword
369 WriteTIbyte(0xeb); // password
370 WriteTIbyte( (idlo )&0xff );
371 WriteTIbyte( (idlo>>8 )&0xff );
372 WriteTIbyte( (idlo>>16)&0xff );
373 WriteTIbyte( (idlo>>24)&0xff );
374 WriteTIbyte( (idhi )&0xff );
375 WriteTIbyte( (idhi>>8 )&0xff );
376 WriteTIbyte( (idhi>>16)&0xff );
377 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
378 WriteTIbyte( (crc )&0xff ); // crc lo
379 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
380 WriteTIbyte(0x00); // write frame lo
381 WriteTIbyte(0x03); // write frame hi
382 HIGH(GPIO_SSC_DOUT);
383 WaitMS(50); // programming time
384
385 LED_A_OFF();
386
387 // get TI tag data into the buffer
388 AcquireTiType();
389
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
391 DbpString("Now use `lf ti read` to check");
392 StopTicks();
393 }
394
395 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
396 {
397 int i = 0;
398 uint8_t *buf = BigBuf_get_addr();
399
400 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
401 //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
402 //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE );
403
404 // set frequency, get values from 'lf config' command
405 sample_config *sc = getSamplingConfig();
406
407 if ( (sc->divisor == 1) || (sc->divisor < 0) || (sc->divisor > 255) )
408 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
409 else if (sc->divisor == 0)
410 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
411 else
412 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
413
414 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
415
416 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
417 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
418 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
419
420 // power on antenna
421 // OPEN_COIL();
422 // SpinDelay(50);
423
424 for(;;) {
425 WDT_HIT();
426
427 if (ledcontrol) LED_D_ON();
428
429 // wait until SSC_CLK goes HIGH
430 // used as a simple detection of a reader field?
431 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
432 WDT_HIT();
433 if ( usb_poll_validate_length() || BUTTON_PRESS() )
434 goto OUT;
435 }
436
437 if(buf[i])
438 OPEN_COIL();
439 else
440 SHORT_COIL();
441
442 //wait until SSC_CLK goes LOW
443 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
444 WDT_HIT();
445 if ( usb_poll_validate_length() || BUTTON_PRESS() )
446 goto OUT;
447 }
448
449 i++;
450 if(i == period) {
451 i = 0;
452 if (gap) {
453 WDT_HIT();
454 SHORT_COIL();
455 SpinDelayUs(gap);
456 }
457 }
458
459 if (ledcontrol) LED_D_OFF();
460 }
461 OUT:
462 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
463 LED_D_OFF();
464 DbpString("Simulation stopped");
465 return;
466 }
467
468 #define DEBUG_FRAME_CONTENTS 1
469 void SimulateTagLowFrequencyBidir(int divisor, int t0)
470 {
471 }
472
473 // compose fc/8 fc/10 waveform (FSK2)
474 static void fc(int c, int *n)
475 {
476 uint8_t *dest = BigBuf_get_addr();
477 int idx;
478
479 // for when we want an fc8 pattern every 4 logical bits
480 if(c==0) {
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 }
490
491 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
492 if(c==8) {
493 for (idx=0; idx<6; idx++) {
494 dest[((*n)++)]=1;
495 dest[((*n)++)]=1;
496 dest[((*n)++)]=1;
497 dest[((*n)++)]=1;
498 dest[((*n)++)]=0;
499 dest[((*n)++)]=0;
500 dest[((*n)++)]=0;
501 dest[((*n)++)]=0;
502 }
503 }
504
505 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
506 if(c==10) {
507 for (idx=0; idx<5; idx++) {
508 dest[((*n)++)]=1;
509 dest[((*n)++)]=1;
510 dest[((*n)++)]=1;
511 dest[((*n)++)]=1;
512 dest[((*n)++)]=1;
513 dest[((*n)++)]=0;
514 dest[((*n)++)]=0;
515 dest[((*n)++)]=0;
516 dest[((*n)++)]=0;
517 dest[((*n)++)]=0;
518 }
519 }
520 }
521 // compose fc/X fc/Y waveform (FSKx)
522 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
523 {
524 uint8_t *dest = BigBuf_get_addr();
525 uint8_t halfFC = fc/2;
526 uint8_t wavesPerClock = clock/fc;
527 uint8_t mod = clock % fc; //modifier
528 uint8_t modAdj = fc/mod; //how often to apply modifier
529 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
530 // loop through clock - step field clock
531 for (uint8_t idx=0; idx < wavesPerClock; idx++){
532 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
533 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
534 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
535 *n += fc;
536 }
537 if (mod>0) (*modCnt)++;
538 if ((mod>0) && modAdjOk){ //fsk2
539 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
540 memset(dest+(*n), 0, fc-halfFC);
541 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
542 *n += fc;
543 }
544 }
545 if (mod>0 && !modAdjOk){ //fsk1
546 memset(dest+(*n), 0, mod-(mod/2));
547 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
548 *n += mod;
549 }
550 }
551
552 // prepare a waveform pattern in the buffer based on the ID given then
553 // simulate a HID tag until the button is pressed
554 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
555 {
556 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
557 set_tracing(FALSE);
558
559 int n = 0, i = 0;
560 /*
561 HID tag bitstream format
562 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
563 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
564 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
565 A fc8 is inserted before every 4 bits
566 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
567 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
568 */
569
570 if (hi > 0xFFF) {
571 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
572 return;
573 }
574 fc(0,&n);
575 // special start of frame marker containing invalid bit sequences
576 fc(8, &n); fc(8, &n); // invalid
577 fc(8, &n); fc(10, &n); // logical 0
578 fc(10, &n); fc(10, &n); // invalid
579 fc(8, &n); fc(10, &n); // logical 0
580
581 WDT_HIT();
582 // manchester encode bits 43 to 32
583 for (i=11; i>=0; i--) {
584 if ((i%4)==3) fc(0,&n);
585 if ((hi>>i)&1) {
586 fc(10, &n); fc(8, &n); // low-high transition
587 } else {
588 fc(8, &n); fc(10, &n); // high-low transition
589 }
590 }
591
592 WDT_HIT();
593 // manchester encode bits 31 to 0
594 for (i=31; i>=0; i--) {
595 if ((i%4)==3) fc(0,&n);
596 if ((lo>>i)&1) {
597 fc(10, &n); fc(8, &n); // low-high transition
598 } else {
599 fc(8, &n); fc(10, &n); // high-low transition
600 }
601 }
602 WDT_HIT();
603
604 if (ledcontrol) LED_A_ON();
605 SimulateTagLowFrequency(n, 0, ledcontrol);
606 if (ledcontrol) LED_A_OFF();
607 }
608
609 // prepare a waveform pattern in the buffer based on the ID given then
610 // simulate a FSK tag until the button is pressed
611 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
612 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
613 {
614 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
615
616 // free eventually allocated BigBuf memory
617 BigBuf_free(); BigBuf_Clear_ext(false);
618 clear_trace();
619 set_tracing(FALSE);
620
621 int ledcontrol = 1, n = 0, i = 0;
622 uint8_t fcHigh = arg1 >> 8;
623 uint8_t fcLow = arg1 & 0xFF;
624 uint16_t modCnt = 0;
625 uint8_t clk = arg2 & 0xFF;
626 uint8_t invert = (arg2 >> 8) & 1;
627
628 for (i=0; i<size; i++){
629
630 if (BitStream[i] == invert)
631 fcAll(fcLow, &n, clk, &modCnt);
632 else
633 fcAll(fcHigh, &n, clk, &modCnt);
634 }
635 WDT_HIT();
636
637 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
638
639 if (ledcontrol) LED_A_ON();
640 SimulateTagLowFrequency(n, 0, ledcontrol);
641 if (ledcontrol) LED_A_OFF();
642 }
643
644 // compose ask waveform for one bit(ASK)
645 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
646 {
647 uint8_t *dest = BigBuf_get_addr();
648 uint8_t halfClk = clock/2;
649 // c = current bit 1 or 0
650 if (manchester==1){
651 memset(dest+(*n), c, halfClk);
652 memset(dest+(*n) + halfClk, c^1, halfClk);
653 } else {
654 memset(dest+(*n), c, clock);
655 }
656 *n += clock;
657 }
658
659 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
660 {
661 uint8_t *dest = BigBuf_get_addr();
662 uint8_t halfClk = clock/2;
663 if (c){
664 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
665 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
666 } else {
667 memset(dest+(*n), c ^ *phase, clock);
668 *phase ^= 1;
669 }
670 *n += clock;
671 }
672
673 static void stAskSimBit(int *n, uint8_t clock) {
674 uint8_t *dest = BigBuf_get_addr();
675 uint8_t halfClk = clock/2;
676 //ST = .5 high .5 low 1.5 high .5 low 1 high
677 memset(dest+(*n), 1, halfClk);
678 memset(dest+(*n) + halfClk, 0, halfClk);
679 memset(dest+(*n) + clock, 1, clock + halfClk);
680 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
681 memset(dest+(*n) + clock*3, 1, clock);
682 *n += clock*4;
683 }
684
685 // args clock, ask/man or askraw, invert, transmission separator
686 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
687 {
688 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
689 set_tracing(FALSE);
690
691 int ledcontrol = 1, n = 0, i = 0;
692 uint8_t clk = (arg1 >> 8) & 0xFF;
693 uint8_t encoding = arg1 & 0xFF;
694 uint8_t separator = arg2 & 1;
695 uint8_t invert = (arg2 >> 8) & 1;
696
697 if (encoding == 2){ //biphase
698 uint8_t phase = 0;
699 for (i=0; i<size; i++){
700 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
701 }
702 if (phase == 1) { //run a second set inverted to keep phase in check
703 for (i=0; i<size; i++){
704 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
705 }
706 }
707 } else { // ask/manchester || ask/raw
708 for (i=0; i<size; i++){
709 askSimBit(BitStream[i]^invert, &n, clk, encoding);
710 }
711 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
712 for (i=0; i<size; i++){
713 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
714 }
715 }
716 }
717 if (separator==1 && encoding == 1)
718 stAskSimBit(&n, clk);
719 else if (separator==1)
720 Dbprintf("sorry but separator option not yet available");
721
722 WDT_HIT();
723
724 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
725
726 if (ledcontrol) LED_A_ON();
727 SimulateTagLowFrequency(n, 0, ledcontrol);
728 if (ledcontrol) LED_A_OFF();
729 }
730
731 //carrier can be 2,4 or 8
732 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
733 {
734 uint8_t *dest = BigBuf_get_addr();
735 uint8_t halfWave = waveLen/2;
736 //uint8_t idx;
737 int i = 0;
738 if (phaseChg){
739 // write phase change
740 memset(dest+(*n), *curPhase^1, halfWave);
741 memset(dest+(*n) + halfWave, *curPhase, halfWave);
742 *n += waveLen;
743 *curPhase ^= 1;
744 i += waveLen;
745 }
746 //write each normal clock wave for the clock duration
747 for (; i < clk; i+=waveLen){
748 memset(dest+(*n), *curPhase, halfWave);
749 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
750 *n += waveLen;
751 }
752 }
753
754 // args clock, carrier, invert,
755 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
756 {
757 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
758 set_tracing(FALSE);
759
760 int ledcontrol = 1, n = 0, i = 0;
761 uint8_t clk = arg1 >> 8;
762 uint8_t carrier = arg1 & 0xFF;
763 uint8_t invert = arg2 & 0xFF;
764 uint8_t curPhase = 0;
765 for (i=0; i<size; i++){
766 if (BitStream[i] == curPhase){
767 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
768 } else {
769 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
770 }
771 }
772
773 WDT_HIT();
774
775 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
776
777 if (ledcontrol) LED_A_ON();
778 SimulateTagLowFrequency(n, 0, ledcontrol);
779 if (ledcontrol) LED_A_OFF();
780 }
781
782 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
783 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
784 {
785 uint8_t *dest = BigBuf_get_addr();
786 size_t size = 0;
787 uint32_t hi2=0, hi=0, lo=0;
788 int idx=0;
789 // Configure to go in 125Khz listen mode
790 LFSetupFPGAForADC(95, true);
791
792 //clear read buffer
793 BigBuf_Clear_keep_EM();
794
795 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
796
797 WDT_HIT();
798 if (ledcontrol) LED_A_ON();
799
800 DoAcquisition_default(-1,true);
801 // FSK demodulator
802 size = 50*128*2; //big enough to catch 2 sequences of largest format
803 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
804
805 if (idx>0 && lo>0 && (size==96 || size==192)){
806 // go over previously decoded manchester data and decode into usable tag ID
807 if (hi2 != 0){ //extra large HID tags 88/192 bits
808 Dbprintf("TAG ID: %x%08x%08x (%d)",
809 (unsigned int) hi2,
810 (unsigned int) hi,
811 (unsigned int) lo,
812 (unsigned int) (lo>>1) & 0xFFFF
813 );
814 } else { //standard HID tags 44/96 bits
815 uint8_t bitlen = 0;
816 uint32_t fc = 0;
817 uint32_t cardnum = 0;
818
819 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
820 uint32_t lo2=0;
821 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
822 uint8_t idx3 = 1;
823 while(lo2 > 1){ //find last bit set to 1 (format len bit)
824 lo2=lo2 >> 1;
825 idx3++;
826 }
827 bitlen = idx3+19;
828 fc =0;
829 cardnum=0;
830 if(bitlen == 26){
831 cardnum = (lo>>1)&0xFFFF;
832 fc = (lo>>17)&0xFF;
833 }
834 if(bitlen == 37){
835 cardnum = (lo>>1)&0x7FFFF;
836 fc = ((hi&0xF)<<12)|(lo>>20);
837 }
838 if(bitlen == 34){
839 cardnum = (lo>>1)&0xFFFF;
840 fc= ((hi&1)<<15)|(lo>>17);
841 }
842 if(bitlen == 35){
843 cardnum = (lo>>1)&0xFFFFF;
844 fc = ((hi&1)<<11)|(lo>>21);
845 }
846 }
847 else { //if bit 38 is not set then 37 bit format is used
848 bitlen= 37;
849 fc =0;
850 cardnum=0;
851 if(bitlen==37){
852 cardnum = (lo>>1)&0x7FFFF;
853 fc = ((hi&0xF)<<12)|(lo>>20);
854 }
855 }
856 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
857 (unsigned int) hi,
858 (unsigned int) lo,
859 (unsigned int) (lo>>1) & 0xFFFF,
860 (unsigned int) bitlen,
861 (unsigned int) fc,
862 (unsigned int) cardnum);
863 }
864 if (findone){
865 if (ledcontrol) LED_A_OFF();
866 *high = hi;
867 *low = lo;
868 break;
869 }
870 // reset
871 }
872 hi2 = hi = lo = idx = 0;
873 WDT_HIT();
874 }
875 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
876 DbpString("Stopped");
877 if (ledcontrol) LED_A_OFF();
878 }
879
880 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
881 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
882 {
883 uint8_t *dest = BigBuf_get_addr();
884 size_t size;
885 int idx=0;
886 //clear read buffer
887 BigBuf_Clear_keep_EM();
888 // Configure to go in 125Khz listen mode
889 LFSetupFPGAForADC(95, true);
890
891 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
892
893 WDT_HIT();
894 if (ledcontrol) LED_A_ON();
895
896 DoAcquisition_default(-1,true);
897 // FSK demodulator
898 size = 50*128*2; //big enough to catch 2 sequences of largest format
899 idx = AWIDdemodFSK(dest, &size);
900
901 if (idx<=0 || size!=96) continue;
902 // Index map
903 // 0 10 20 30 40 50 60
904 // | | | | | | |
905 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
906 // -----------------------------------------------------------------------------
907 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
908 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
909 // |---26 bit---| |-----117----||-------------142-------------|
910 // b = format bit len, o = odd parity of last 3 bits
911 // f = facility code, c = card number
912 // w = wiegand parity
913 // (26 bit format shown)
914
915 //get raw ID before removing parities
916 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
917 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
918 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
919
920 size = removeParity(dest, idx+8, 4, 1, 88);
921 if (size != 66) continue;
922
923 // Index map
924 // 0 10 20 30 40 50 60
925 // | | | | | | |
926 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
927 // -----------------------------------------------------------------------------
928 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
929 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
930 // |26 bit| |-117--| |-----142------|
931 //
932 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
933 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
934 // |50 bit| |----4000------||-----------2248975-------------|
935 //
936 // b = format bit len, o = odd parity of last 3 bits
937 // f = facility code, c = card number
938 // w = wiegand parity
939
940 uint32_t fc = 0;
941 uint32_t cardnum = 0;
942 uint32_t code1 = 0;
943 uint32_t code2 = 0;
944 uint8_t fmtLen = bytebits_to_byte(dest,8);
945 switch(fmtLen) {
946 case 26:
947 fc = bytebits_to_byte(dest + 9, 8);
948 cardnum = bytebits_to_byte(dest + 17, 16);
949 code1 = bytebits_to_byte(dest + 8,fmtLen);
950 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
951 break;
952 case 50:
953 fc = bytebits_to_byte(dest + 9, 16);
954 cardnum = bytebits_to_byte(dest + 25, 32);
955 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
956 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
957 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
958 break;
959 default:
960 if (fmtLen > 32 ) {
961 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
962 code1 = bytebits_to_byte(dest+8,fmtLen-32);
963 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
964 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
965 } else {
966 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
967 code1 = bytebits_to_byte(dest+8,fmtLen);
968 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
969 }
970 break;
971 }
972 if (findone)
973 break;
974
975 idx = 0;
976 WDT_HIT();
977 }
978
979 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
980 DbpString("Stopped");
981 if (ledcontrol) LED_A_OFF();
982 }
983
984 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
985 {
986 uint8_t *dest = BigBuf_get_addr();
987
988 size_t size=0, idx=0;
989 int clk=0, invert=0, errCnt=0, maxErr=20;
990 uint32_t hi=0;
991 uint64_t lo=0;
992 //clear read buffer
993 BigBuf_Clear_keep_EM();
994 // Configure to go in 125Khz listen mode
995 LFSetupFPGAForADC(95, true);
996
997 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
998
999 WDT_HIT();
1000 if (ledcontrol) LED_A_ON();
1001
1002 DoAcquisition_default(-1,true);
1003 size = BigBuf_max_traceLen();
1004 //askdemod and manchester decode
1005 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
1006 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
1007 WDT_HIT();
1008
1009 if (errCnt<0) continue;
1010
1011 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
1012 if (errCnt){
1013 if (size>64){
1014 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
1015 hi,
1016 (uint32_t)(lo>>32),
1017 (uint32_t)lo,
1018 (uint32_t)(lo&0xFFFF),
1019 (uint32_t)((lo>>16LL) & 0xFF),
1020 (uint32_t)(lo & 0xFFFFFF));
1021 } else {
1022 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1023 (uint32_t)(lo>>32),
1024 (uint32_t)lo,
1025 (uint32_t)(lo&0xFFFF),
1026 (uint32_t)((lo>>16LL) & 0xFF),
1027 (uint32_t)(lo & 0xFFFFFF));
1028 }
1029
1030 if (findone){
1031 if (ledcontrol) LED_A_OFF();
1032 *high=lo>>32;
1033 *low=lo & 0xFFFFFFFF;
1034 break;
1035 }
1036 }
1037 WDT_HIT();
1038 hi = lo = size = idx = 0;
1039 clk = invert = errCnt = 0;
1040 }
1041 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1042 DbpString("Stopped");
1043 if (ledcontrol) LED_A_OFF();
1044 }
1045
1046 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1047 {
1048 uint8_t *dest = BigBuf_get_addr();
1049 int idx=0;
1050 uint32_t code=0, code2=0;
1051 uint8_t version=0;
1052 uint8_t facilitycode=0;
1053 uint16_t number=0;
1054 uint8_t crc = 0;
1055 uint16_t calccrc = 0;
1056
1057 //clear read buffer
1058 BigBuf_Clear_keep_EM();
1059
1060 // Configure to go in 125Khz listen mode
1061 LFSetupFPGAForADC(95, true);
1062
1063 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1064 WDT_HIT();
1065 if (ledcontrol) LED_A_ON();
1066 DoAcquisition_default(-1,true);
1067 //fskdemod and get start index
1068 WDT_HIT();
1069 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1070 if (idx<0) continue;
1071 //valid tag found
1072
1073 //Index map
1074 //0 10 20 30 40 50 60
1075 //| | | | | | |
1076 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1077 //-----------------------------------------------------------------------------
1078 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1079 //
1080 //Checksum:
1081 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1082 //preamble F0 E0 01 03 B6 75
1083 // How to calc checksum,
1084 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1085 // F0 + E0 + 01 + 03 + B6 = 28A
1086 // 28A & FF = 8A
1087 // FF - 8A = 75
1088 // Checksum: 0x75
1089 //XSF(version)facility:codeone+codetwo
1090 //Handle the data
1091 // if(findone){ //only print binary if we are doing one
1092 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1093 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1094 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1095 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1096 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1097 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1098 // Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1099 // }
1100 code = bytebits_to_byte(dest+idx,32);
1101 code2 = bytebits_to_byte(dest+idx+32,32);
1102 version = bytebits_to_byte(dest+idx+27,8); //14,4
1103 facilitycode = bytebits_to_byte(dest+idx+18,8);
1104 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1105
1106 crc = bytebits_to_byte(dest+idx+54,8);
1107 for (uint8_t i=1; i<6; ++i)
1108 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1109 calccrc &= 0xff;
1110 calccrc = 0xff - calccrc;
1111
1112 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1113
1114 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1115 // if we're only looking for one tag
1116 if (findone){
1117 if (ledcontrol) LED_A_OFF();
1118 *high=code;
1119 *low=code2;
1120 break;
1121 }
1122 code=code2=0;
1123 version=facilitycode=0;
1124 number=0;
1125 idx=0;
1126
1127 WDT_HIT();
1128 }
1129 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1130 DbpString("Stopped");
1131 if (ledcontrol) LED_A_OFF();
1132 }
1133
1134 /*------------------------------
1135 * T5555/T5557/T5567/T5577 routines
1136 *------------------------------
1137 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1138 *
1139 * Relevant communication times in microsecond
1140 * To compensate antenna falling times shorten the write times
1141 * and enlarge the gap ones.
1142 * Q5 tags seems to have issues when these values changes.
1143 */
1144
1145 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
1146 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
1147 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
1148 #define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
1149 #define READ_GAP 15*8
1150
1151 // VALUES TAKEN FROM EM4x function: SendForward
1152 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1153 // WRITE_GAP = 128; (16*8)
1154 // WRITE_1 = 256 32*8; (32*8)
1155
1156 // These timings work for 4469/4269/4305 (with the 55*8 above)
1157 // WRITE_0 = 23*8 , 9*8
1158
1159 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1160 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1161 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1162 // T0 = TIMER_CLOCK1 / 125000 = 192
1163 // 1 Cycle = 8 microseconds(us) == 1 field clock
1164
1165 // new timer:
1166 // = 1us = 1.5ticks
1167 // 1fc = 8us = 12ticks
1168 void TurnReadLFOn(uint32_t delay) {
1169 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1170
1171 // measure antenna strength.
1172 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1173
1174 // Give it a bit of time for the resonant antenna to settle.
1175 WaitUS(delay);
1176 }
1177
1178 // Write one bit to card
1179 void T55xxWriteBit(int bit) {
1180 if (!bit)
1181 TurnReadLFOn(WRITE_0);
1182 else
1183 TurnReadLFOn(WRITE_1);
1184 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1185 WaitUS(WRITE_GAP);
1186 }
1187
1188 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1189 void T55xxResetRead(void) {
1190 LED_A_ON();
1191 //clear buffer now so it does not interfere with timing later
1192 BigBuf_Clear_keep_EM();
1193
1194 // Set up FPGA, 125kHz
1195 LFSetupFPGAForADC(95, true);
1196
1197 // Trigger T55x7 in mode.
1198 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1199 WaitUS(START_GAP);
1200
1201 // reset tag - op code 00
1202 T55xxWriteBit(0);
1203 T55xxWriteBit(0);
1204
1205 // Turn field on to read the response
1206 TurnReadLFOn(READ_GAP);
1207
1208 // Acquisition
1209 doT55x7Acquisition(BigBuf_max_traceLen());
1210
1211 // Turn the field off
1212 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1213 cmd_send(CMD_ACK,0,0,0,0,0);
1214 LED_A_OFF();
1215 }
1216
1217 // Write one card block in page 0, no lock
1218 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1219 LED_A_ON();
1220 bool PwdMode = arg & 0x1;
1221 uint8_t Page = (arg & 0x2)>>1;
1222 uint32_t i = 0;
1223
1224 // Set up FPGA, 125kHz
1225 LFSetupFPGAForADC(95, true);
1226
1227 // Trigger T55x7 in mode.
1228 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1229 WaitUS(START_GAP);
1230
1231 // Opcode 10
1232 T55xxWriteBit(1);
1233 T55xxWriteBit(Page); //Page 0
1234 if (PwdMode){
1235 // Send Pwd
1236 for (i = 0x80000000; i != 0; i >>= 1)
1237 T55xxWriteBit(Pwd & i);
1238 }
1239 // Send Lock bit
1240 T55xxWriteBit(0);
1241
1242 // Send Data
1243 for (i = 0x80000000; i != 0; i >>= 1)
1244 T55xxWriteBit(Data & i);
1245
1246 // Send Block number
1247 for (i = 0x04; i != 0; i >>= 1)
1248 T55xxWriteBit(Block & i);
1249
1250 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1251 // so wait a little more)
1252 TurnReadLFOn(20 * 1000);
1253
1254 //could attempt to do a read to confirm write took
1255 // as the tag should repeat back the new block
1256 // until it is reset, but to confirm it we would
1257 // need to know the current block 0 config mode
1258
1259 // turn field off
1260 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1261 LED_A_OFF();
1262 }
1263
1264 // Write one card block in page 0, no lock
1265 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1266 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1267 cmd_send(CMD_ACK,0,0,0,0,0);
1268 }
1269
1270 // Read one card block in page [page]
1271 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1272 LED_A_ON();
1273 bool PwdMode = arg0 & 0x1;
1274 uint8_t Page = (arg0 & 0x2) >> 1;
1275 uint32_t i = 0;
1276 bool RegReadMode = (Block == 0xFF);
1277
1278 //clear buffer now so it does not interfere with timing later
1279 BigBuf_Clear_keep_EM();
1280
1281 //make sure block is at max 7
1282 Block &= 0x7;
1283
1284 // Set up FPGA, 125kHz to power up the tag
1285 LFSetupFPGAForADC(95, true);
1286 //SpinDelay(3);
1287
1288 // Trigger T55x7 Direct Access Mode with start gap
1289 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1290 WaitUS(START_GAP);
1291
1292 // Opcode 1[page]
1293 T55xxWriteBit(1);
1294 T55xxWriteBit(Page); //Page 0
1295
1296 if (PwdMode){
1297 // Send Pwd
1298 for (i = 0x80000000; i != 0; i >>= 1)
1299 T55xxWriteBit(Pwd & i);
1300 }
1301 // Send a zero bit separation
1302 T55xxWriteBit(0);
1303
1304 // Send Block number (if direct access mode)
1305 if (!RegReadMode)
1306 for (i = 0x04; i != 0; i >>= 1)
1307 T55xxWriteBit(Block & i);
1308
1309 // Turn field on to read the response
1310 TurnReadLFOn(READ_GAP);
1311
1312 // Acquisition
1313 doT55x7Acquisition(7679);
1314
1315 // Turn the field off
1316 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1317 cmd_send(CMD_ACK,0,0,0,0,0);
1318 LED_A_OFF();
1319 }
1320
1321 void T55xxWakeUp(uint32_t Pwd){
1322 LED_B_ON();
1323 uint32_t i = 0;
1324
1325 // Set up FPGA, 125kHz
1326 LFSetupFPGAForADC(95, true);
1327
1328 // Trigger T55x7 Direct Access Mode
1329 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1330 WaitUS(START_GAP);
1331
1332 // Opcode 10
1333 T55xxWriteBit(1);
1334 T55xxWriteBit(0); //Page 0
1335
1336 // Send Pwd
1337 for (i = 0x80000000; i != 0; i >>= 1)
1338 T55xxWriteBit(Pwd & i);
1339
1340 // Turn and leave field on to let the begin repeating transmission
1341 TurnReadLFOn(20*1000);
1342 }
1343
1344 /*-------------- Cloning routines -----------*/
1345 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1346 // write last block first and config block last (if included)
1347 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1348 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1349 }
1350
1351 // Copy HID id to card and setup block 0 config
1352 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1353 uint32_t data[] = {0,0,0,0,0,0,0};
1354 uint8_t last_block = 0;
1355
1356 if (longFMT){
1357 // Ensure no more than 84 bits supplied
1358 if (hi2 > 0xFFFFF) {
1359 DbpString("Tags can only have 84 bits.");
1360 return;
1361 }
1362 // Build the 6 data blocks for supplied 84bit ID
1363 last_block = 6;
1364 // load preamble (1D) & long format identifier (9E manchester encoded)
1365 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1366 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1367 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1368 data[3] = manchesterEncode2Bytes(hi >> 16);
1369 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1370 data[5] = manchesterEncode2Bytes(lo >> 16);
1371 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1372 } else {
1373 // Ensure no more than 44 bits supplied
1374 if (hi > 0xFFF) {
1375 DbpString("Tags can only have 44 bits.");
1376 return;
1377 }
1378 // Build the 3 data blocks for supplied 44bit ID
1379 last_block = 3;
1380 // load preamble
1381 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1382 data[2] = manchesterEncode2Bytes(lo >> 16);
1383 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1384 }
1385 // load chip config block
1386 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1387
1388 //TODO add selection of chip for Q5 or T55x7
1389 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1390
1391 LED_D_ON();
1392 WriteT55xx(data, 0, last_block+1);
1393 LED_D_OFF();
1394 }
1395
1396 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1397 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1398 //TODO add selection of chip for Q5 or T55x7
1399 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1400 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1401
1402 LED_D_ON();
1403 // Program the data blocks for supplied ID
1404 // and the block 0 config
1405 WriteT55xx(data, 0, 3);
1406 LED_D_OFF();
1407 }
1408
1409 // Clone Indala 64-bit tag by UID to T55x7
1410 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1411 //Program the 2 data blocks for supplied 64bit UID
1412 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1413 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1414 //TODO add selection of chip for Q5 or T55x7
1415 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1416
1417 WriteT55xx(data, 0, 3);
1418 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1419 // T5567WriteBlock(0x603E1042,0);
1420 }
1421 // Clone Indala 224-bit tag by UID to T55x7
1422 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1423 //Program the 7 data blocks for supplied 224bit UID
1424 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1425 // and the block 0 for Indala224 format
1426 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1427 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1428 //TODO add selection of chip for Q5 or T55x7
1429 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1430 WriteT55xx(data, 0, 8);
1431 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1432 // T5567WriteBlock(0x603E10E2,0);
1433 }
1434 // clone viking tag to T55xx
1435 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1436 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1437 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1438 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1439 // Program the data blocks for supplied ID and the block 0 config
1440 WriteT55xx(data, 0, 3);
1441 LED_D_OFF();
1442 cmd_send(CMD_ACK,0,0,0,0,0);
1443 }
1444
1445 // Define 9bit header for EM410x tags
1446 #define EM410X_HEADER 0x1FF
1447 #define EM410X_ID_LENGTH 40
1448
1449 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1450 int i, id_bit;
1451 uint64_t id = EM410X_HEADER;
1452 uint64_t rev_id = 0; // reversed ID
1453 int c_parity[4]; // column parity
1454 int r_parity = 0; // row parity
1455 uint32_t clock = 0;
1456
1457 // Reverse ID bits given as parameter (for simpler operations)
1458 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1459 if (i < 32) {
1460 rev_id = (rev_id << 1) | (id_lo & 1);
1461 id_lo >>= 1;
1462 } else {
1463 rev_id = (rev_id << 1) | (id_hi & 1);
1464 id_hi >>= 1;
1465 }
1466 }
1467
1468 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1469 id_bit = rev_id & 1;
1470
1471 if (i % 4 == 0) {
1472 // Don't write row parity bit at start of parsing
1473 if (i)
1474 id = (id << 1) | r_parity;
1475 // Start counting parity for new row
1476 r_parity = id_bit;
1477 } else {
1478 // Count row parity
1479 r_parity ^= id_bit;
1480 }
1481
1482 // First elements in column?
1483 if (i < 4)
1484 // Fill out first elements
1485 c_parity[i] = id_bit;
1486 else
1487 // Count column parity
1488 c_parity[i % 4] ^= id_bit;
1489
1490 // Insert ID bit
1491 id = (id << 1) | id_bit;
1492 rev_id >>= 1;
1493 }
1494
1495 // Insert parity bit of last row
1496 id = (id << 1) | r_parity;
1497
1498 // Fill out column parity at the end of tag
1499 for (i = 0; i < 4; ++i)
1500 id = (id << 1) | c_parity[i];
1501
1502 // Add stop bit
1503 id <<= 1;
1504
1505 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1506 LED_D_ON();
1507
1508 // Write EM410x ID
1509 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1510
1511 clock = (card & 0xFF00) >> 8;
1512 clock = (clock == 0) ? 64 : clock;
1513 Dbprintf("Clock rate: %d", clock);
1514 if (card & 0xFF) { //t55x7
1515 clock = GetT55xxClockBit(clock);
1516 if (clock == 0) {
1517 Dbprintf("Invalid clock rate: %d", clock);
1518 return;
1519 }
1520 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1521 } else { //t5555 (Q5)
1522 clock = (clock-2)>>1; //n = (RF-2)/2
1523 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1524 }
1525
1526 WriteT55xx(data, 0, 3);
1527
1528 LED_D_OFF();
1529 Dbprintf("Tag %s written with 0x%08x%08x\n",
1530 card ? "T55x7":"T5555",
1531 (uint32_t)(id >> 32),
1532 (uint32_t)id);
1533 }
1534
1535 //-----------------------------------
1536 // EM4469 / EM4305 routines
1537 //-----------------------------------
1538 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1539 #define FWD_CMD_WRITE 0xA
1540 #define FWD_CMD_READ 0x9
1541 #define FWD_CMD_DISABLE 0x5
1542
1543 uint8_t forwardLink_data[64]; //array of forwarded bits
1544 uint8_t * forward_ptr; //ptr for forward message preparation
1545 uint8_t fwd_bit_sz; //forwardlink bit counter
1546 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1547
1548 //====================================================================
1549 // prepares command bits
1550 // see EM4469 spec
1551 //====================================================================
1552 //--------------------------------------------------------------------
1553 // VALUES TAKEN FROM EM4x function: SendForward
1554 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1555 // WRITE_GAP = 128; (16*8)
1556 // WRITE_1 = 256 32*8; (32*8)
1557
1558 // These timings work for 4469/4269/4305 (with the 55*8 above)
1559 // WRITE_0 = 23*8 , 9*8
1560
1561 uint8_t Prepare_Cmd( uint8_t cmd ) {
1562
1563 *forward_ptr++ = 0; //start bit
1564 *forward_ptr++ = 0; //second pause for 4050 code
1565
1566 *forward_ptr++ = cmd;
1567 cmd >>= 1;
1568 *forward_ptr++ = cmd;
1569 cmd >>= 1;
1570 *forward_ptr++ = cmd;
1571 cmd >>= 1;
1572 *forward_ptr++ = cmd;
1573
1574 return 6; //return number of emited bits
1575 }
1576
1577 //====================================================================
1578 // prepares address bits
1579 // see EM4469 spec
1580 //====================================================================
1581 uint8_t Prepare_Addr( uint8_t addr ) {
1582
1583 register uint8_t line_parity;
1584
1585 uint8_t i;
1586 line_parity = 0;
1587 for(i=0;i<6;i++) {
1588 *forward_ptr++ = addr;
1589 line_parity ^= addr;
1590 addr >>= 1;
1591 }
1592
1593 *forward_ptr++ = (line_parity & 1);
1594
1595 return 7; //return number of emited bits
1596 }
1597
1598 //====================================================================
1599 // prepares data bits intreleaved with parity bits
1600 // see EM4469 spec
1601 //====================================================================
1602 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1603
1604 register uint8_t line_parity;
1605 register uint8_t column_parity;
1606 register uint8_t i, j;
1607 register uint16_t data;
1608
1609 data = data_low;
1610 column_parity = 0;
1611
1612 for(i=0; i<4; i++) {
1613 line_parity = 0;
1614 for(j=0; j<8; j++) {
1615 line_parity ^= data;
1616 column_parity ^= (data & 1) << j;
1617 *forward_ptr++ = data;
1618 data >>= 1;
1619 }
1620 *forward_ptr++ = line_parity;
1621 if(i == 1)
1622 data = data_hi;
1623 }
1624
1625 for(j=0; j<8; j++) {
1626 *forward_ptr++ = column_parity;
1627 column_parity >>= 1;
1628 }
1629 *forward_ptr = 0;
1630
1631 return 45; //return number of emited bits
1632 }
1633
1634 //====================================================================
1635 // Forward Link send function
1636 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1637 // fwd_bit_count set with number of bits to be sent
1638 //====================================================================
1639 void SendForward(uint8_t fwd_bit_count) {
1640
1641 fwd_write_ptr = forwardLink_data;
1642 fwd_bit_sz = fwd_bit_count;
1643
1644 LED_D_ON();
1645
1646 // Set up FPGA, 125kHz
1647 LFSetupFPGAForADC(95, true);
1648
1649 // force 1st mod pulse (start gap must be longer for 4305)
1650 fwd_bit_sz--; //prepare next bit modulation
1651 fwd_write_ptr++;
1652 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1653 WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
1654 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1655 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1656
1657 // now start writting
1658 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1659 if(((*fwd_write_ptr++) & 1) == 1)
1660 WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1661 else {
1662 //These timings work for 4469/4269/4305 (with the 55*8 above)
1663 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1664 WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1665 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1666 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1667 }
1668 }
1669 }
1670
1671 void EM4xLogin(uint32_t Password) {
1672
1673 uint8_t fwd_bit_count;
1674 forward_ptr = forwardLink_data;
1675 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1676 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1677 SendForward(fwd_bit_count);
1678
1679 //Wait for command to complete
1680 WaitMS(20);
1681 }
1682
1683 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1684
1685 uint8_t fwd_bit_count;
1686 uint8_t *dest = BigBuf_get_addr();
1687 uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
1688 uint32_t i = 0;
1689
1690 // Clear destination buffer before sending the command
1691 BigBuf_Clear_ext(false);
1692
1693 //If password mode do login
1694 if (PwdMode == 1) EM4xLogin(Pwd);
1695
1696 forward_ptr = forwardLink_data;
1697 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1698 fwd_bit_count += Prepare_Addr( Address );
1699
1700 SendForward(fwd_bit_count);
1701
1702 // Now do the acquisition
1703 // ICEMAN, change to the one in lfsampling.c
1704 i = 0;
1705 for(;;) {
1706 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1707 AT91C_BASE_SSC->SSC_THR = 0x43;
1708 }
1709 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1710 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1711 ++i;
1712 if (i >= bufsize) break;
1713 }
1714 }
1715
1716 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1717 cmd_send(CMD_ACK,0,0,0,0,0);
1718 LED_D_OFF();
1719 }
1720
1721 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1722
1723 uint8_t fwd_bit_count;
1724
1725 //If password mode do login
1726 if (PwdMode == 1) EM4xLogin(Pwd);
1727
1728 forward_ptr = forwardLink_data;
1729 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1730 fwd_bit_count += Prepare_Addr( Address );
1731 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1732
1733 SendForward(fwd_bit_count);
1734
1735 //Wait for write to complete
1736 WaitMS(20);
1737 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1738 LED_D_OFF();
1739 }
Proxmark3 GIT tracking
Impressum, Datenschutz