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ADD: Marshmellows fixes for "lf t55xx" and "lf cmdread" ref: https://github.com...
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40 //clear read buffer
41 BigBuf_Clear_keep_EM();
42
43 /* Make sure the tag is reset */
44 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
45 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
46 SpinDelay(2500);
47
48 LFSetupFPGAForADC(sc.divisor, 1);
49
50 // And a little more time for the tag to fully power up
51 SpinDelay(2000);
52
53 // now modulate the reader field
54 while(*command != '\0' && *command != ' ') {
55 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
56 LED_D_OFF();
57 SpinDelayUs(delay_off);
58 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
59
60 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
61 LED_D_ON();
62 if(*(command++) == '0')
63 SpinDelayUs(period_0);
64 else
65 SpinDelayUs(period_1);
66 }
67 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
68 LED_D_OFF();
69 SpinDelayUs(delay_off);
70 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
71
72 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
73
74 // now do the read
75 DoAcquisition_config(false);
76 }
77
78 /* blank r/w tag data stream
79 ...0000000000000000 01111111
80 1010101010101010101010101010101010101010101010101010101010101010
81 0011010010100001
82 01111111
83 101010101010101[0]000...
84
85 [5555fe852c5555555555555555fe0000]
86 */
87 void ReadTItag(void)
88 {
89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
180 if (shift3 & (1<<15) ) {
181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
208 if (crc != (shift2&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
210 } else {
211 DbpString("Info: CRC is good");
212 }
213 }
214 }
215
216 void WriteTIbyte(uint8_t b)
217 {
218 int i = 0;
219
220 // modulate 8 bits out to the antenna
221 for (i=0; i<8; i++)
222 {
223 if (b&(1<<i)) {
224 // stop modulating antenna
225 LOW(GPIO_SSC_DOUT);
226 SpinDelayUs(1000);
227 // modulate antenna
228 HIGH(GPIO_SSC_DOUT);
229 SpinDelayUs(1000);
230 } else {
231 // stop modulating antenna
232 LOW(GPIO_SSC_DOUT);
233 SpinDelayUs(300);
234 // modulate antenna
235 HIGH(GPIO_SSC_DOUT);
236 SpinDelayUs(1700);
237 }
238 }
239 }
240
241 void AcquireTiType(void)
242 {
243 int i, j, n;
244 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
245 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
246 #define TIBUFLEN 1250
247
248 // clear buffer
249 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
250
251 //clear buffer now so it does not interfere with timing later
252 BigBuf_Clear_ext(false);
253
254 // Set up the synchronous serial port
255 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
256 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
257
258 // steal this pin from the SSP and use it to control the modulation
259 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
260 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
261
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
263 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
264
265 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
266 // 48/2 = 24 MHz clock must be divided by 12
267 AT91C_BASE_SSC->SSC_CMR = 12;
268
269 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
270 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
271 AT91C_BASE_SSC->SSC_TCMR = 0;
272 AT91C_BASE_SSC->SSC_TFMR = 0;
273
274 LED_D_ON();
275
276 // modulate antenna
277 HIGH(GPIO_SSC_DOUT);
278
279 // Charge TI tag for 50ms.
280 SpinDelay(50);
281
282 // stop modulating antenna and listen
283 LOW(GPIO_SSC_DOUT);
284
285 LED_D_OFF();
286
287 i = 0;
288 for(;;) {
289 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
290 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
291 i++; if(i >= TIBUFLEN) break;
292 }
293 WDT_HIT();
294 }
295
296 // return stolen pin to SSP
297 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
298 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
299
300 char *dest = (char *)BigBuf_get_addr();
301 n = TIBUFLEN * 32;
302
303 // unpack buffer
304 for (i = TIBUFLEN-1; i >= 0; i--) {
305 for (j = 0; j < 32; j++) {
306 if(buf[i] & (1 << j)) {
307 dest[--n] = 1;
308 } else {
309 dest[--n] = -1;
310 }
311 }
312 }
313 }
314
315 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
316 // if crc provided, it will be written with the data verbatim (even if bogus)
317 // if not provided a valid crc will be computed from the data and written.
318 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
319 {
320 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
321 if(crc == 0) {
322 crc = update_crc16(crc, (idlo)&0xff);
323 crc = update_crc16(crc, (idlo>>8)&0xff);
324 crc = update_crc16(crc, (idlo>>16)&0xff);
325 crc = update_crc16(crc, (idlo>>24)&0xff);
326 crc = update_crc16(crc, (idhi)&0xff);
327 crc = update_crc16(crc, (idhi>>8)&0xff);
328 crc = update_crc16(crc, (idhi>>16)&0xff);
329 crc = update_crc16(crc, (idhi>>24)&0xff);
330 }
331 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
332
333 // TI tags charge at 134.2Khz
334 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
335 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
336 // connects to SSP_DIN and the SSP_DOUT logic level controls
337 // whether we're modulating the antenna (high)
338 // or listening to the antenna (low)
339 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
340 LED_A_ON();
341
342 // steal this pin from the SSP and use it to control the modulation
343 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
344 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
345
346 // writing algorithm:
347 // a high bit consists of a field off for 1ms and field on for 1ms
348 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
349 // initiate a charge time of 50ms (field on) then immediately start writing bits
350 // start by writing 0xBB (keyword) and 0xEB (password)
351 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
352 // finally end with 0x0300 (write frame)
353 // all data is sent lsb first
354 // finish with 15ms programming time
355
356 // modulate antenna
357 HIGH(GPIO_SSC_DOUT);
358 SpinDelay(50); // charge time
359
360 WriteTIbyte(0xbb); // keyword
361 WriteTIbyte(0xeb); // password
362 WriteTIbyte( (idlo )&0xff );
363 WriteTIbyte( (idlo>>8 )&0xff );
364 WriteTIbyte( (idlo>>16)&0xff );
365 WriteTIbyte( (idlo>>24)&0xff );
366 WriteTIbyte( (idhi )&0xff );
367 WriteTIbyte( (idhi>>8 )&0xff );
368 WriteTIbyte( (idhi>>16)&0xff );
369 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
370 WriteTIbyte( (crc )&0xff ); // crc lo
371 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
372 WriteTIbyte(0x00); // write frame lo
373 WriteTIbyte(0x03); // write frame hi
374 HIGH(GPIO_SSC_DOUT);
375 SpinDelay(50); // programming time
376
377 LED_A_OFF();
378
379 // get TI tag data into the buffer
380 AcquireTiType();
381
382 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
383 DbpString("Now use 'lf ti read' to check");
384 }
385
386 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
387 {
388 int i;
389 uint8_t *tab = BigBuf_get_addr();
390
391 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
392 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
393
394 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
405 if(BUTTON_PRESS() || usb_poll_validate_length() ) {
406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol) LED_D_ON();
412
413 if(tab[i])
414 OPEN_COIL();
415 else
416 SHORT_COIL();
417
418 if (ledcontrol) LED_D_OFF();
419
420 //wait until SSC_CLK goes LOW
421 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
422 if( BUTTON_PRESS() || usb_poll_validate_length() ) {
423 DbpString("Stopped");
424 return;
425 }
426 WDT_HIT();
427 }
428
429 i++;
430 if(i == period) {
431
432 i = 0;
433 if (gap) {
434 SHORT_COIL();
435 SpinDelayUs(gap);
436 }
437 }
438 }
439 }
440
441 #define DEBUG_FRAME_CONTENTS 1
442 void SimulateTagLowFrequencyBidir(int divisor, int t0)
443 {
444 }
445
446 // compose fc/8 fc/10 waveform (FSK2)
447 static void fc(int c, int *n)
448 {
449 uint8_t *dest = BigBuf_get_addr();
450 int idx;
451
452 // for when we want an fc8 pattern every 4 logical bits
453 if(c==0) {
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 }
463
464 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
465 if(c==8) {
466 for (idx=0; idx<6; idx++) {
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 }
476 }
477
478 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
479 if(c==10) {
480 for (idx=0; idx<5; idx++) {
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 }
492 }
493 }
494 // compose fc/X fc/Y waveform (FSKx)
495 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
496 {
497 uint8_t *dest = BigBuf_get_addr();
498 uint8_t halfFC = fc/2;
499 uint8_t wavesPerClock = clock/fc;
500 uint8_t mod = clock % fc; //modifier
501 uint8_t modAdj = fc/mod; //how often to apply modifier
502 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
503 // loop through clock - step field clock
504 for (uint8_t idx=0; idx < wavesPerClock; idx++){
505 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
506 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
507 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
508 *n += fc;
509 }
510 if (mod>0) (*modCnt)++;
511 if ((mod>0) && modAdjOk){ //fsk2
512 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
513 memset(dest+(*n), 0, fc-halfFC);
514 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
515 *n += fc;
516 }
517 }
518 if (mod>0 && !modAdjOk){ //fsk1
519 memset(dest+(*n), 0, mod-(mod/2));
520 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
521 *n += mod;
522 }
523 }
524
525 // prepare a waveform pattern in the buffer based on the ID given then
526 // simulate a HID tag until the button is pressed
527 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
528 {
529 int n=0, i=0;
530 /*
531 HID tag bitstream format
532 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
533 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
534 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
535 A fc8 is inserted before every 4 bits
536 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
537 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
538 */
539
540 if (hi>0xFFF) {
541 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
542 return;
543 }
544 fc(0,&n);
545 // special start of frame marker containing invalid bit sequences
546 fc(8, &n); fc(8, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548 fc(10, &n); fc(10, &n); // invalid
549 fc(8, &n); fc(10, &n); // logical 0
550
551 WDT_HIT();
552 // manchester encode bits 43 to 32
553 for (i=11; i>=0; i--) {
554 if ((i%4)==3) fc(0,&n);
555 if ((hi>>i)&1) {
556 fc(10, &n); fc(8, &n); // low-high transition
557 } else {
558 fc(8, &n); fc(10, &n); // high-low transition
559 }
560 }
561
562 WDT_HIT();
563 // manchester encode bits 31 to 0
564 for (i=31; i>=0; i--) {
565 if ((i%4)==3) fc(0,&n);
566 if ((lo>>i)&1) {
567 fc(10, &n); fc(8, &n); // low-high transition
568 } else {
569 fc(8, &n); fc(10, &n); // high-low transition
570 }
571 }
572
573 if (ledcontrol) LED_A_ON();
574 SimulateTagLowFrequency(n, 0, ledcontrol);
575 if (ledcontrol) LED_A_OFF();
576 }
577
578 // prepare a waveform pattern in the buffer based on the ID given then
579 // simulate a FSK tag until the button is pressed
580 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
581 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
582 {
583 int ledcontrol=1;
584 int n=0, i=0;
585 uint8_t fcHigh = arg1 >> 8;
586 uint8_t fcLow = arg1 & 0xFF;
587 uint16_t modCnt = 0;
588 uint8_t clk = arg2 & 0xFF;
589 uint8_t invert = (arg2 >> 8) & 1;
590
591 for (i=0; i<size; i++){
592 if (BitStream[i] == invert){
593 fcAll(fcLow, &n, clk, &modCnt);
594 } else {
595 fcAll(fcHigh, &n, clk, &modCnt);
596 }
597 }
598 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
599
600 if (ledcontrol) LED_A_ON();
601 SimulateTagLowFrequency(n, 0, ledcontrol);
602 if (ledcontrol) LED_A_OFF();
603 }
604
605 // compose ask waveform for one bit(ASK)
606 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
607 {
608 uint8_t *dest = BigBuf_get_addr();
609 uint8_t halfClk = clock/2;
610 // c = current bit 1 or 0
611 if (manchester==1){
612 memset(dest+(*n), c, halfClk);
613 memset(dest+(*n) + halfClk, c^1, halfClk);
614 } else {
615 memset(dest+(*n), c, clock);
616 }
617 *n += clock;
618 }
619
620 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
621 {
622 uint8_t *dest = BigBuf_get_addr();
623 uint8_t halfClk = clock/2;
624 if (c){
625 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
626 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
627 } else {
628 memset(dest+(*n), c ^ *phase, clock);
629 *phase ^= 1;
630 }
631
632 }
633
634 // args clock, ask/man or askraw, invert, transmission separator
635 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
636 {
637 int ledcontrol = 1;
638 int n=0, i=0;
639 uint8_t clk = (arg1 >> 8) & 0xFF;
640 uint8_t encoding = arg1 & 0xFF;
641 uint8_t separator = arg2 & 1;
642 uint8_t invert = (arg2 >> 8) & 1;
643
644 if (encoding==2){ //biphase
645 uint8_t phase=0;
646 for (i=0; i<size; i++){
647 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
648 }
649 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
650 for (i=0; i<size; i++){
651 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
652 }
653 }
654 } else { // ask/manchester || ask/raw
655 for (i=0; i<size; i++){
656 askSimBit(BitStream[i]^invert, &n, clk, encoding);
657 }
658 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
659 for (i=0; i<size; i++){
660 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
661 }
662 }
663 }
664
665 if (separator==1) Dbprintf("sorry but separator option not yet available");
666
667 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
668
669 if (ledcontrol) LED_A_ON();
670 SimulateTagLowFrequency(n, 0, ledcontrol);
671 if (ledcontrol) LED_A_OFF();
672 }
673
674 //carrier can be 2,4 or 8
675 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
676 {
677 uint8_t *dest = BigBuf_get_addr();
678 uint8_t halfWave = waveLen/2;
679 //uint8_t idx;
680 int i = 0;
681 if (phaseChg){
682 // write phase change
683 memset(dest+(*n), *curPhase^1, halfWave);
684 memset(dest+(*n) + halfWave, *curPhase, halfWave);
685 *n += waveLen;
686 *curPhase ^= 1;
687 i += waveLen;
688 }
689 //write each normal clock wave for the clock duration
690 for (; i < clk; i+=waveLen){
691 memset(dest+(*n), *curPhase, halfWave);
692 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
693 *n += waveLen;
694 }
695 }
696
697 // args clock, carrier, invert,
698 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
699 {
700 int ledcontrol = 1;
701 int n=0, i=0;
702 uint8_t clk = arg1 >> 8;
703 uint8_t carrier = arg1 & 0xFF;
704 uint8_t invert = arg2 & 0xFF;
705 uint8_t curPhase = 0;
706 for (i=0; i<size; i++){
707 if (BitStream[i] == curPhase){
708 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
709 } else {
710 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
711 }
712 }
713 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
714
715 if (ledcontrol) LED_A_ON();
716 SimulateTagLowFrequency(n, 0, ledcontrol);
717 if (ledcontrol) LED_A_OFF();
718 }
719
720 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
721 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
722 {
723 uint8_t *dest = BigBuf_get_addr();
724 size_t size = 0;
725 uint32_t hi2=0, hi=0, lo=0;
726 int idx=0;
727 // Configure to go in 125Khz listen mode
728 LFSetupFPGAForADC(95, true);
729
730 //clear read buffer
731 BigBuf_Clear_keep_EM();
732
733 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
734
735 WDT_HIT();
736 if (ledcontrol) LED_A_ON();
737
738 DoAcquisition_default(-1,true);
739 // FSK demodulator
740 size = 50*128*2; //big enough to catch 2 sequences of largest format
741 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
742
743 if (idx>0 && lo>0 && (size==96 || size==192)){
744 // go over previously decoded manchester data and decode into usable tag ID
745 if (hi2 != 0){ //extra large HID tags 88/192 bits
746 Dbprintf("TAG ID: %x%08x%08x (%d)",
747 (unsigned int) hi2,
748 (unsigned int) hi,
749 (unsigned int) lo,
750 (unsigned int) (lo>>1) & 0xFFFF
751 );
752 } else { //standard HID tags 44/96 bits
753 uint8_t bitlen = 0;
754 uint32_t fc = 0;
755 uint32_t cardnum = 0;
756
757 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
758 uint32_t lo2=0;
759 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
760 uint8_t idx3 = 1;
761 while(lo2 > 1){ //find last bit set to 1 (format len bit)
762 lo2=lo2 >> 1;
763 idx3++;
764 }
765 bitlen = idx3+19;
766 fc =0;
767 cardnum=0;
768 if(bitlen == 26){
769 cardnum = (lo>>1)&0xFFFF;
770 fc = (lo>>17)&0xFF;
771 }
772 if(bitlen == 37){
773 cardnum = (lo>>1)&0x7FFFF;
774 fc = ((hi&0xF)<<12)|(lo>>20);
775 }
776 if(bitlen == 34){
777 cardnum = (lo>>1)&0xFFFF;
778 fc= ((hi&1)<<15)|(lo>>17);
779 }
780 if(bitlen == 35){
781 cardnum = (lo>>1)&0xFFFFF;
782 fc = ((hi&1)<<11)|(lo>>21);
783 }
784 }
785 else { //if bit 38 is not set then 37 bit format is used
786 bitlen= 37;
787 fc =0;
788 cardnum=0;
789 if(bitlen==37){
790 cardnum = (lo>>1)&0x7FFFF;
791 fc = ((hi&0xF)<<12)|(lo>>20);
792 }
793 }
794 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
795 (unsigned int) hi,
796 (unsigned int) lo,
797 (unsigned int) (lo>>1) & 0xFFFF,
798 (unsigned int) bitlen,
799 (unsigned int) fc,
800 (unsigned int) cardnum);
801 }
802 if (findone){
803 if (ledcontrol) LED_A_OFF();
804 *high = hi;
805 *low = lo;
806 return;
807 }
808 // reset
809 }
810 hi2 = hi = lo = idx = 0;
811 WDT_HIT();
812 }
813 DbpString("Stopped");
814 if (ledcontrol) LED_A_OFF();
815 }
816
817 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
818 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
819 {
820 uint8_t *dest = BigBuf_get_addr();
821 size_t size;
822 int idx=0;
823 //clear read buffer
824 BigBuf_Clear_keep_EM();
825 // Configure to go in 125Khz listen mode
826 LFSetupFPGAForADC(95, true);
827
828 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
829
830 WDT_HIT();
831 if (ledcontrol) LED_A_ON();
832
833 DoAcquisition_default(-1,true);
834 // FSK demodulator
835 size = 50*128*2; //big enough to catch 2 sequences of largest format
836 idx = AWIDdemodFSK(dest, &size);
837
838 if (idx<=0 || size!=96) continue;
839 // Index map
840 // 0 10 20 30 40 50 60
841 // | | | | | | |
842 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
843 // -----------------------------------------------------------------------------
844 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
845 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
846 // |---26 bit---| |-----117----||-------------142-------------|
847 // b = format bit len, o = odd parity of last 3 bits
848 // f = facility code, c = card number
849 // w = wiegand parity
850 // (26 bit format shown)
851
852 //get raw ID before removing parities
853 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
854 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
855 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
856
857 size = removeParity(dest, idx+8, 4, 1, 88);
858 if (size != 66) continue;
859 // ok valid card found!
860
861 // Index map
862 // 0 10 20 30 40 50 60
863 // | | | | | | |
864 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
865 // -----------------------------------------------------------------------------
866 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
867 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
868 // |26 bit| |-117--| |-----142------|
869 // b = format bit len, o = odd parity of last 3 bits
870 // f = facility code, c = card number
871 // w = wiegand parity
872 // (26 bit format shown)
873
874 uint32_t fc = 0;
875 uint32_t cardnum = 0;
876 uint32_t code1 = 0;
877 uint32_t code2 = 0;
878 uint8_t fmtLen = bytebits_to_byte(dest,8);
879 if (fmtLen==26){
880 fc = bytebits_to_byte(dest+9, 8);
881 cardnum = bytebits_to_byte(dest+17, 16);
882 code1 = bytebits_to_byte(dest+8,fmtLen);
883 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
884 } else {
885 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
886 if (fmtLen>32){
887 code1 = bytebits_to_byte(dest+8,fmtLen-32);
888 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
889 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
890 } else{
891 code1 = bytebits_to_byte(dest+8,fmtLen);
892 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
893 }
894 }
895 if (findone){
896 if (ledcontrol) LED_A_OFF();
897 return;
898 }
899 // reset
900 idx = 0;
901 WDT_HIT();
902 }
903 DbpString("Stopped");
904 if (ledcontrol) LED_A_OFF();
905 }
906
907 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
908 {
909 uint8_t *dest = BigBuf_get_addr();
910
911 size_t size=0, idx=0;
912 int clk=0, invert=0, errCnt=0, maxErr=20;
913 uint32_t hi=0;
914 uint64_t lo=0;
915 //clear read buffer
916 BigBuf_Clear_keep_EM();
917 // Configure to go in 125Khz listen mode
918 LFSetupFPGAForADC(95, true);
919
920 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
921
922 WDT_HIT();
923 if (ledcontrol) LED_A_ON();
924
925 DoAcquisition_default(-1,true);
926 size = BigBuf_max_traceLen();
927 //askdemod and manchester decode
928 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
929 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
930 WDT_HIT();
931
932 if (errCnt<0) continue;
933
934 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
935 if (errCnt){
936 if (size>64){
937 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
938 hi,
939 (uint32_t)(lo>>32),
940 (uint32_t)lo,
941 (uint32_t)(lo&0xFFFF),
942 (uint32_t)((lo>>16LL) & 0xFF),
943 (uint32_t)(lo & 0xFFFFFF));
944 } else {
945 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
946 (uint32_t)(lo>>32),
947 (uint32_t)lo,
948 (uint32_t)(lo&0xFFFF),
949 (uint32_t)((lo>>16LL) & 0xFF),
950 (uint32_t)(lo & 0xFFFFFF));
951 }
952
953 if (findone){
954 if (ledcontrol) LED_A_OFF();
955 *high=lo>>32;
956 *low=lo & 0xFFFFFFFF;
957 return;
958 }
959 }
960 WDT_HIT();
961 hi = lo = size = idx = 0;
962 clk = invert = errCnt = 0;
963 }
964 DbpString("Stopped");
965 if (ledcontrol) LED_A_OFF();
966 }
967
968 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
969 {
970 uint8_t *dest = BigBuf_get_addr();
971 int idx=0;
972 uint32_t code=0, code2=0;
973 uint8_t version=0;
974 uint8_t facilitycode=0;
975 uint16_t number=0;
976 uint8_t crc = 0;
977 uint16_t calccrc = 0;
978
979 //clear read buffer
980 BigBuf_Clear_keep_EM();
981
982 // Configure to go in 125Khz listen mode
983 LFSetupFPGAForADC(95, true);
984
985 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
986 WDT_HIT();
987 if (ledcontrol) LED_A_ON();
988 DoAcquisition_default(-1,true);
989 //fskdemod and get start index
990 WDT_HIT();
991 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
992 if (idx<0) continue;
993 //valid tag found
994
995 //Index map
996 //0 10 20 30 40 50 60
997 //| | | | | | |
998 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
999 //-----------------------------------------------------------------------------
1000 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1001 //
1002 //Checksum:
1003 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1004 //preamble F0 E0 01 03 B6 75
1005 // How to calc checksum,
1006 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1007 // F0 + E0 + 01 + 03 + B6 = 28A
1008 // 28A & FF = 8A
1009 // FF - 8A = 75
1010 // Checksum: 0x75
1011 //XSF(version)facility:codeone+codetwo
1012 //Handle the data
1013 if(findone){ //only print binary if we are doing one
1014 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1015 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1016 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1017 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1018 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1019 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1020 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1021 }
1022 code = bytebits_to_byte(dest+idx,32);
1023 code2 = bytebits_to_byte(dest+idx+32,32);
1024 version = bytebits_to_byte(dest+idx+27,8); //14,4
1025 facilitycode = bytebits_to_byte(dest+idx+18,8);
1026 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1027
1028 crc = bytebits_to_byte(dest+idx+54,8);
1029 for (uint8_t i=1; i<6; ++i)
1030 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1031 calccrc &= 0xff;
1032 calccrc = 0xff - calccrc;
1033
1034 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1035
1036 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1037 // if we're only looking for one tag
1038 if (findone){
1039 if (ledcontrol) LED_A_OFF();
1040 *high=code;
1041 *low=code2;
1042 return;
1043 }
1044 code=code2=0;
1045 version=facilitycode=0;
1046 number=0;
1047 idx=0;
1048
1049 WDT_HIT();
1050 }
1051 DbpString("Stopped");
1052 if (ledcontrol) LED_A_OFF();
1053 }
1054
1055 /*------------------------------
1056 * T5555/T5557/T5567/T5577 routines
1057 *------------------------------
1058 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1059 *
1060 * Relevant communication times in microsecond
1061 * To compensate antenna falling times shorten the write times
1062 * and enlarge the gap ones.
1063 * Q5 tags seems to have issues when these values changes.
1064 */
1065
1066 #define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1067 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1068 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1069 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1070 #define READ_GAP 15*8
1071
1072 // VALUES TAKEN FROM EM4x function: SendForward
1073 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1074 // WRITE_GAP = 128; (16*8)
1075 // WRITE_1 = 256 32*8; (32*8)
1076
1077 // These timings work for 4469/4269/4305 (with the 55*8 above)
1078 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1079
1080 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1081 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1082 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1083 // T0 = TIMER_CLOCK1 / 125000 = 192
1084 // 1 Cycle = 8 microseconds(us) == 1 field clock
1085
1086 void TurnReadLFOn(int delay) {
1087 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1088 // Give it a bit of time for the resonant antenna to settle.
1089
1090 // measure antenna strength.
1091 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1092 // where to save it
1093
1094 SpinDelayUs(delay);
1095 }
1096
1097 // Write one bit to card
1098 void T55xxWriteBit(int bit) {
1099 if (!bit)
1100 TurnReadLFOn(WRITE_0);
1101 else
1102 TurnReadLFOn(WRITE_1);
1103 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1104 SpinDelayUs(WRITE_GAP);
1105 }
1106
1107 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1108 void T55xxResetRead(void) {
1109 LED_A_ON();
1110 //clear buffer now so it does not interfere with timing later
1111 BigBuf_Clear_keep_EM();
1112
1113 // Set up FPGA, 125kHz
1114 LFSetupFPGAForADC(95, true);
1115
1116 // Trigger T55x7 in mode.
1117 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1118 SpinDelayUs(START_GAP);
1119
1120 // reset tag - op code 00
1121 T55xxWriteBit(0);
1122 T55xxWriteBit(0);
1123
1124 // Turn field on to read the response
1125 TurnReadLFOn(READ_GAP);
1126
1127 // Acquisition
1128 doT55x7Acquisition(BigBuf_max_traceLen());
1129
1130 // Turn the field off
1131 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1132 cmd_send(CMD_ACK,0,0,0,0,0);
1133 LED_A_OFF();
1134 }
1135
1136 // Write one card block in page 0, no lock
1137 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1138 LED_A_ON();
1139 bool PwdMode = arg & 0x1;
1140 uint8_t Page = (arg & 0x2)>>1;
1141 uint32_t i = 0;
1142
1143 // Set up FPGA, 125kHz
1144 LFSetupFPGAForADC(95, true);
1145
1146 // Trigger T55x7 in mode.
1147 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1148 SpinDelayUs(START_GAP);
1149
1150 // Opcode 10
1151 T55xxWriteBit(1);
1152 T55xxWriteBit(Page); //Page 0
1153 if (PwdMode){
1154 // Send Pwd
1155 for (i = 0x80000000; i != 0; i >>= 1)
1156 T55xxWriteBit(Pwd & i);
1157 }
1158 // Send Lock bit
1159 T55xxWriteBit(0);
1160
1161 // Send Data
1162 for (i = 0x80000000; i != 0; i >>= 1)
1163 T55xxWriteBit(Data & i);
1164
1165 // Send Block number
1166 for (i = 0x04; i != 0; i >>= 1)
1167 T55xxWriteBit(Block & i);
1168
1169 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1170 // so wait a little more)
1171 TurnReadLFOn(20 * 1000);
1172 //could attempt to do a read to confirm write took
1173 // as the tag should repeat back the new block
1174 // until it is reset, but to confirm it we would
1175 // need to know the current block 0 config mode
1176
1177 // turn field off
1178 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1179 LED_A_OFF();
1180 }
1181
1182 // Write one card block in page 0, no lock
1183 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1184 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1185 cmd_send(CMD_ACK,0,0,0,0,0);
1186 }
1187
1188 // Read one card block in page [page]
1189 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1190 LED_A_ON();
1191 bool PwdMode = arg0 & 0x1;
1192 uint8_t Page = (arg0 & 0x2) >> 1;
1193 uint32_t i = 0;
1194 bool RegReadMode = (Block == 0xFF);
1195
1196 //clear buffer now so it does not interfere with timing later
1197 BigBuf_Clear_ext(false);
1198
1199 //make sure block is at max 7
1200 Block &= 0x7;
1201
1202 // Set up FPGA, 125kHz to power up the tag
1203 LFSetupFPGAForADC(95, true);
1204
1205 // Trigger T55x7 Direct Access Mode with start gap
1206 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1207 SpinDelayUs(START_GAP);
1208
1209 // Opcode 1[page]
1210 T55xxWriteBit(1);
1211 T55xxWriteBit(Page); //Page 0
1212
1213 if (PwdMode){
1214 // Send Pwd
1215 for (i = 0x80000000; i != 0; i >>= 1)
1216 T55xxWriteBit(Pwd & i);
1217 }
1218 // Send a zero bit separation
1219 T55xxWriteBit(0);
1220
1221 // Send Block number (if direct access mode)
1222 if (!RegReadMode)
1223 for (i = 0x04; i != 0; i >>= 1)
1224 T55xxWriteBit(Block & i);
1225
1226 // Turn field on to read the response
1227 TurnReadLFOn(READ_GAP);
1228
1229 // Acquisition
1230 doT55x7Acquisition(12000);
1231
1232 // Turn the field off
1233 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1234 cmd_send(CMD_ACK,0,0,0,0,0);
1235 LED_A_OFF();
1236 }
1237
1238 void T55xxWakeUp(uint32_t Pwd){
1239 LED_B_ON();
1240 uint32_t i = 0;
1241
1242 // Set up FPGA, 125kHz
1243 LFSetupFPGAForADC(95, true);
1244
1245 // Trigger T55x7 Direct Access Mode
1246 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1247 SpinDelayUs(START_GAP);
1248
1249 // Opcode 10
1250 T55xxWriteBit(1);
1251 T55xxWriteBit(0); //Page 0
1252
1253 // Send Pwd
1254 for (i = 0x80000000; i != 0; i >>= 1)
1255 T55xxWriteBit(Pwd & i);
1256
1257 // Turn and leave field on to let the begin repeating transmission
1258 TurnReadLFOn(20*1000);
1259 }
1260
1261 /*-------------- Cloning routines -----------*/
1262
1263 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1264 // write last block first and config block last (if included)
1265 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1266 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1267 }
1268
1269 // Copy HID id to card and setup block 0 config
1270 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1271 uint32_t data[] = {0,0,0,0,0,0,0};
1272 uint8_t last_block = 0;
1273
1274 if (longFMT){
1275 // Ensure no more than 84 bits supplied
1276 if (hi2 > 0xFFFFF) {
1277 DbpString("Tags can only have 84 bits.");
1278 return;
1279 }
1280 // Build the 6 data blocks for supplied 84bit ID
1281 last_block = 6;
1282 // load preamble (1D) & long format identifier (9E manchester encoded)
1283 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1284 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1285 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1286 data[3] = manchesterEncode2Bytes(hi >> 16);
1287 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1288 data[5] = manchesterEncode2Bytes(lo >> 16);
1289 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1290 } else {
1291 // Ensure no more than 44 bits supplied
1292 if (hi > 0xFFF) {
1293 DbpString("Tags can only have 44 bits.");
1294 return;
1295 }
1296 // Build the 3 data blocks for supplied 44bit ID
1297 last_block = 3;
1298 // load preamble
1299 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1300 data[2] = manchesterEncode2Bytes(lo >> 16);
1301 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1302 }
1303 // load chip config block
1304 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1305
1306 //TODO add selection of chip for Q5 or T55x7
1307 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1308
1309 LED_D_ON();
1310 // Program the data blocks for supplied ID
1311 // and the block 0 for HID format
1312 WriteT55xx(data, 0, last_block+1);
1313
1314 LED_D_OFF();
1315
1316 DbpString("DONE!");
1317 }
1318
1319 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1320 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1321 //TODO add selection of chip for Q5 or T55x7
1322 // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1323
1324 LED_D_ON();
1325 // Program the data blocks for supplied ID
1326 // and the block 0 config
1327 WriteT55xx(data, 0, 3);
1328
1329 LED_D_OFF();
1330
1331 DbpString("DONE!");
1332 }
1333
1334 // Clone Indala 64-bit tag by UID to T55x7
1335 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1336 //Program the 2 data blocks for supplied 64bit UID
1337 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1338 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1339 //TODO add selection of chip for Q5 or T55x7
1340 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1341
1342 WriteT55xx(data, 0, 3);
1343 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1344 // T5567WriteBlock(0x603E1042,0);
1345 DbpString("DONE!");
1346 }
1347 // Clone Indala 224-bit tag by UID to T55x7
1348 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1349 //Program the 7 data blocks for supplied 224bit UID
1350 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1351 // and the block 0 for Indala224 format
1352 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1353 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1354 //TODO add selection of chip for Q5 or T55x7
1355 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1356 WriteT55xx(data, 0, 8);
1357 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1358 // T5567WriteBlock(0x603E10E2,0);
1359 DbpString("DONE!");
1360 }
1361 // clone viking tag to T55xx
1362 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1363 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1364 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1365 // Program the data blocks for supplied ID and the block 0 config
1366 WriteT55xx(data, 0, 3);
1367 LED_D_OFF();
1368 cmd_send(CMD_ACK,0,0,0,0,0);
1369 }
1370
1371 // Define 9bit header for EM410x tags
1372 #define EM410X_HEADER 0x1FF
1373 #define EM410X_ID_LENGTH 40
1374
1375 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1376 int i, id_bit;
1377 uint64_t id = EM410X_HEADER;
1378 uint64_t rev_id = 0; // reversed ID
1379 int c_parity[4]; // column parity
1380 int r_parity = 0; // row parity
1381 uint32_t clock = 0;
1382
1383 // Reverse ID bits given as parameter (for simpler operations)
1384 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1385 if (i < 32) {
1386 rev_id = (rev_id << 1) | (id_lo & 1);
1387 id_lo >>= 1;
1388 } else {
1389 rev_id = (rev_id << 1) | (id_hi & 1);
1390 id_hi >>= 1;
1391 }
1392 }
1393
1394 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1395 id_bit = rev_id & 1;
1396
1397 if (i % 4 == 0) {
1398 // Don't write row parity bit at start of parsing
1399 if (i)
1400 id = (id << 1) | r_parity;
1401 // Start counting parity for new row
1402 r_parity = id_bit;
1403 } else {
1404 // Count row parity
1405 r_parity ^= id_bit;
1406 }
1407
1408 // First elements in column?
1409 if (i < 4)
1410 // Fill out first elements
1411 c_parity[i] = id_bit;
1412 else
1413 // Count column parity
1414 c_parity[i % 4] ^= id_bit;
1415
1416 // Insert ID bit
1417 id = (id << 1) | id_bit;
1418 rev_id >>= 1;
1419 }
1420
1421 // Insert parity bit of last row
1422 id = (id << 1) | r_parity;
1423
1424 // Fill out column parity at the end of tag
1425 for (i = 0; i < 4; ++i)
1426 id = (id << 1) | c_parity[i];
1427
1428 // Add stop bit
1429 id <<= 1;
1430
1431 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1432 LED_D_ON();
1433
1434 // Write EM410x ID
1435 uint32_t data[] = {0, (uint32_t)(id>>32), id & 0xFFFFFFFF};
1436
1437 clock = (card & 0xFF00) >> 8;
1438 clock = (clock == 0) ? 64 : clock;
1439 Dbprintf("Clock rate: %d", clock);
1440 if (card & 0xFF) { //t55x7
1441 clock = GetT55xxClockBit(clock);
1442 if (clock == 0) {
1443 Dbprintf("Invalid clock rate: %d", clock);
1444 return;
1445 }
1446 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1447 } else { //t5555 (Q5)
1448 clock = (clock-2)>>1; //n = (RF-2)/2
1449 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1450 }
1451
1452 WriteT55xx(data, 0, 3);
1453
1454 LED_D_OFF();
1455 Dbprintf("Tag %s written with 0x%08x%08x\n",
1456 card ? "T55x7":"T5555",
1457 (uint32_t)(id >> 32),
1458 (uint32_t)id);
1459 }
1460
1461 //-----------------------------------
1462 // EM4469 / EM4305 routines
1463 //-----------------------------------
1464 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1465 #define FWD_CMD_WRITE 0xA
1466 #define FWD_CMD_READ 0x9
1467 #define FWD_CMD_DISABLE 0x5
1468
1469 uint8_t forwardLink_data[64]; //array of forwarded bits
1470 uint8_t * forward_ptr; //ptr for forward message preparation
1471 uint8_t fwd_bit_sz; //forwardlink bit counter
1472 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1473
1474 //====================================================================
1475 // prepares command bits
1476 // see EM4469 spec
1477 //====================================================================
1478 //--------------------------------------------------------------------
1479 // VALUES TAKEN FROM EM4x function: SendForward
1480 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1481 // WRITE_GAP = 128; (16*8)
1482 // WRITE_1 = 256 32*8; (32*8)
1483
1484 // These timings work for 4469/4269/4305 (with the 55*8 above)
1485 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1486
1487 uint8_t Prepare_Cmd( uint8_t cmd ) {
1488
1489 *forward_ptr++ = 0; //start bit
1490 *forward_ptr++ = 0; //second pause for 4050 code
1491
1492 *forward_ptr++ = cmd;
1493 cmd >>= 1;
1494 *forward_ptr++ = cmd;
1495 cmd >>= 1;
1496 *forward_ptr++ = cmd;
1497 cmd >>= 1;
1498 *forward_ptr++ = cmd;
1499
1500 return 6; //return number of emited bits
1501 }
1502
1503 //====================================================================
1504 // prepares address bits
1505 // see EM4469 spec
1506 //====================================================================
1507 uint8_t Prepare_Addr( uint8_t addr ) {
1508
1509 register uint8_t line_parity;
1510
1511 uint8_t i;
1512 line_parity = 0;
1513 for(i=0;i<6;i++) {
1514 *forward_ptr++ = addr;
1515 line_parity ^= addr;
1516 addr >>= 1;
1517 }
1518
1519 *forward_ptr++ = (line_parity & 1);
1520
1521 return 7; //return number of emited bits
1522 }
1523
1524 //====================================================================
1525 // prepares data bits intreleaved with parity bits
1526 // see EM4469 spec
1527 //====================================================================
1528 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1529
1530 register uint8_t line_parity;
1531 register uint8_t column_parity;
1532 register uint8_t i, j;
1533 register uint16_t data;
1534
1535 data = data_low;
1536 column_parity = 0;
1537
1538 for(i=0; i<4; i++) {
1539 line_parity = 0;
1540 for(j=0; j<8; j++) {
1541 line_parity ^= data;
1542 column_parity ^= (data & 1) << j;
1543 *forward_ptr++ = data;
1544 data >>= 1;
1545 }
1546 *forward_ptr++ = line_parity;
1547 if(i == 1)
1548 data = data_hi;
1549 }
1550
1551 for(j=0; j<8; j++) {
1552 *forward_ptr++ = column_parity;
1553 column_parity >>= 1;
1554 }
1555 *forward_ptr = 0;
1556
1557 return 45; //return number of emited bits
1558 }
1559
1560 //====================================================================
1561 // Forward Link send function
1562 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1563 // fwd_bit_count set with number of bits to be sent
1564 //====================================================================
1565 void SendForward(uint8_t fwd_bit_count) {
1566
1567 fwd_write_ptr = forwardLink_data;
1568 fwd_bit_sz = fwd_bit_count;
1569
1570 LED_D_ON();
1571
1572 // Set up FPGA, 125kHz
1573 LFSetupFPGAForADC(95, true);
1574
1575 // force 1st mod pulse (start gap must be longer for 4305)
1576 fwd_bit_sz--; //prepare next bit modulation
1577 fwd_write_ptr++;
1578 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1579 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1580 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1581 SpinDelayUs(16*8); //16 cycles on (8us each)
1582
1583 // now start writting
1584 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1585 if(((*fwd_write_ptr++) & 1) == 1)
1586 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1587 else {
1588 //These timings work for 4469/4269/4305 (with the 55*8 above)
1589 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1590 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1591 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1592 SpinDelayUs(9*8); //16 cycles on (8us each)
1593 }
1594 }
1595 }
1596
1597 void EM4xLogin(uint32_t Password) {
1598
1599 uint8_t fwd_bit_count;
1600
1601 forward_ptr = forwardLink_data;
1602 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1603 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1604
1605 SendForward(fwd_bit_count);
1606
1607 //Wait for command to complete
1608 SpinDelay(20);
1609 }
1610
1611 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1612
1613 uint8_t fwd_bit_count;
1614 uint8_t *dest = BigBuf_get_addr();
1615 uint16_t bufsize = BigBuf_max_traceLen();
1616 uint32_t i = 0;
1617
1618 // Clear destination buffer before sending the command
1619 BigBuf_Clear_ext(false);
1620
1621 //If password mode do login
1622 if (PwdMode == 1) EM4xLogin(Pwd);
1623
1624 forward_ptr = forwardLink_data;
1625 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1626 fwd_bit_count += Prepare_Addr( Address );
1627
1628 // Connect the A/D to the peak-detected low-frequency path.
1629 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1630 // Now set up the SSC to get the ADC samples that are now streaming at us.
1631 FpgaSetupSsc();
1632
1633 SendForward(fwd_bit_count);
1634
1635 // Now do the acquisition
1636 i = 0;
1637 for(;;) {
1638 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1639 AT91C_BASE_SSC->SSC_THR = 0x43;
1640 }
1641 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1642 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1643 ++i;
1644 if (i >= bufsize) break;
1645 }
1646 }
1647
1648 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1649 cmd_send(CMD_ACK,0,0,0,0,0);
1650 LED_D_OFF();
1651 }
1652
1653 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1654
1655 uint8_t fwd_bit_count;
1656
1657 //If password mode do login
1658 if (PwdMode == 1) EM4xLogin(Pwd);
1659
1660 forward_ptr = forwardLink_data;
1661 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1662 fwd_bit_count += Prepare_Addr( Address );
1663 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1664
1665 SendForward(fwd_bit_count);
1666
1667 //Wait for write to complete
1668 SpinDelay(20);
1669 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1670 LED_D_OFF();
1671 }
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