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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, April 2006
3 // iZsh <izsh at fail0verflow.com>, 2014
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // Routines to load the FPGA image, and then to configure the FPGA's major
10 // mode once it is configured.
11 //-----------------------------------------------------------------------------
12
13 #include <stdint.h>
14 #include <stddef.h>
15 #include <stdbool.h>
16 #include "fpgaloader.h"
17 #include "proxmark3.h"
18 #include "util.h"
19 #include "string.h"
20 #include "BigBuf.h"
21 #include "zlib.h"
22
23 extern void Dbprintf(const char *fmt, ...);
24
25 // remember which version of the bitstream we have already downloaded to the FPGA
26 static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
27
28 // this is where the bitstreams are located in memory:
29 extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
30
31 static uint8_t *fpga_image_ptr = NULL;
32 static uint32_t uncompressed_bytes_cnt;
33
34 static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
35 #define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
36 #define OUTPUT_BUFFER_LEN 80
37 #define FPGA_INTERLEAVE_SIZE 288
38
39 //-----------------------------------------------------------------------------
40 // Set up the Serial Peripheral Interface as master
41 // Used to write the FPGA config word
42 // May also be used to write to other SPI attached devices like an LCD
43 //-----------------------------------------------------------------------------
44 void SetupSpi(int mode)
45 {
46 // PA10 -> SPI_NCS2 chip select (LCD)
47 // PA11 -> SPI_NCS0 chip select (FPGA)
48 // PA12 -> SPI_MISO Master-In Slave-Out
49 // PA13 -> SPI_MOSI Master-Out Slave-In
50 // PA14 -> SPI_SPCK Serial Clock
51
52 // Disable PIO control of the following pins, allows use by the SPI peripheral
53 AT91C_BASE_PIOA->PIO_PDR =
54 GPIO_NCS0 |
55 GPIO_NCS2 |
56 GPIO_MISO |
57 GPIO_MOSI |
58 GPIO_SPCK;
59
60 AT91C_BASE_PIOA->PIO_ASR =
61 GPIO_NCS0 |
62 GPIO_MISO |
63 GPIO_MOSI |
64 GPIO_SPCK;
65
66 AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
67
68 //enable the SPI Peripheral clock
69 AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
70 // Enable SPI
71 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
72
73 switch (mode) {
74 case SPI_FPGA_MODE:
75 AT91C_BASE_SPI->SPI_MR =
76 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
77 (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
78 ( 0 << 7) | // Local Loopback Disabled
79 ( 1 << 4) | // Mode Fault Detection disabled
80 ( 0 << 2) | // Chip selects connected directly to peripheral
81 ( 0 << 1) | // Fixed Peripheral Select
82 ( 1 << 0); // Master Mode
83 AT91C_BASE_SPI->SPI_CSR[0] =
84 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
85 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
86 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
87 ( 8 << 4) | // Bits per Transfer (16 bits)
88 ( 0 << 3) | // Chip Select inactive after transfer
89 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
90 ( 0 << 0); // Clock Polarity inactive state is logic 0
91 break;
92 case SPI_LCD_MODE:
93 AT91C_BASE_SPI->SPI_MR =
94 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
95 (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
96 ( 0 << 7) | // Local Loopback Disabled
97 ( 1 << 4) | // Mode Fault Detection disabled
98 ( 0 << 2) | // Chip selects connected directly to peripheral
99 ( 0 << 1) | // Fixed Peripheral Select
100 ( 1 << 0); // Master Mode
101 AT91C_BASE_SPI->SPI_CSR[2] =
102 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
103 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
104 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
105 ( 1 << 4) | // Bits per Transfer (9 bits)
106 ( 0 << 3) | // Chip Select inactive after transfer
107 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
108 ( 0 << 0); // Clock Polarity inactive state is logic 0
109 break;
110 default: // Disable SPI
111 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
112 break;
113 }
114 }
115
116 //-----------------------------------------------------------------------------
117 // Set up the synchronous serial port, with the one set of options that we
118 // always use when we are talking to the FPGA. Both RX and TX are enabled.
119 //-----------------------------------------------------------------------------
120 void FpgaSetupSsc(void) {
121 // First configure the GPIOs, and get ourselves a clock.
122 AT91C_BASE_PIOA->PIO_ASR =
123 GPIO_SSC_FRAME |
124 GPIO_SSC_DIN |
125 GPIO_SSC_DOUT |
126 GPIO_SSC_CLK;
127 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
128
129 AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_SSC);
130
131 // Now set up the SSC proper, starting from a known state.
132 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
133
134 // RX clock comes from TX clock, RX starts when TX starts, data changes
135 // on RX clock rising edge, sampled on falling edge
136 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
137
138 // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
139 // pulse, no output sync
140 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
141
142 // clock comes from TK pin, no clock output, outputs change on falling
143 // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
144 AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
145
146 // tx framing is the same as the rx framing
147 AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
148
149 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
150 }
151
152 //-----------------------------------------------------------------------------
153 // Set up DMA to receive samples from the FPGA. We will use the PDC, with
154 // a single buffer as a circular buffer (so that we just chain back to
155 // ourselves, not to another buffer). The stuff to manipulate those buffers
156 // is in apps.h, because it should be inlined, for speed.
157 //-----------------------------------------------------------------------------
158 bool FpgaSetupSscDma(uint8_t *buf, int len) {
159 if (buf == NULL) return false;
160
161 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
162 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
163 AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
164 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
165 AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
166 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
167 return true;
168 }
169
170
171 //----------------------------------------------------------------------------
172 // Uncompress (inflate) the FPGA data. Returns one decompressed byte with
173 // each call.
174 //----------------------------------------------------------------------------
175 static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
176 {
177 if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
178 compressed_fpga_stream->next_out = output_buffer;
179 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
180 fpga_image_ptr = output_buffer;
181 int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
182
183 if (res != Z_OK)
184 Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
185
186 if (res < 0)
187 return res;
188 }
189
190 ++uncompressed_bytes_cnt;
191
192 return *fpga_image_ptr++;
193 }
194
195 //----------------------------------------------------------------------------
196 // Undo the interleaving of several FPGA config files. FPGA config files
197 // are combined into one big file:
198 // 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
199 //----------------------------------------------------------------------------
200 static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
201 {
202 while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
203 // skip undesired data belonging to other bitstream_versions
204 get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
205 }
206
207 return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
208 }
209
210
211 static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
212 {
213 return BigBuf_malloc(items*size);
214 }
215
216
217 static void fpga_inflate_free(voidpf opaque, voidpf address)
218 {
219 // free eventually allocated BigBuf memory
220 BigBuf_free(); BigBuf_Clear_ext(false);
221 }
222
223
224 //----------------------------------------------------------------------------
225 // Initialize decompression of the respective (HF or LF) FPGA stream
226 //----------------------------------------------------------------------------
227 static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
228 {
229 uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
230
231 uncompressed_bytes_cnt = 0;
232
233 // initialize z_stream structure for inflate:
234 compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
235 compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
236 compressed_fpga_stream->next_out = output_buffer;
237 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
238 compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
239 compressed_fpga_stream->zfree = &fpga_inflate_free;
240
241 inflateInit2(compressed_fpga_stream, 0);
242
243 fpga_image_ptr = output_buffer;
244
245 for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
246 header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
247
248 // Check for a valid .bit file (starts with _bitparse_fixed_header)
249 if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
250 return true;
251
252 return false;
253 }
254
255
256 static void DownloadFPGA_byte(unsigned char w)
257 {
258 #define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
259 SEND_BIT(7);
260 SEND_BIT(6);
261 SEND_BIT(5);
262 SEND_BIT(4);
263 SEND_BIT(3);
264 SEND_BIT(2);
265 SEND_BIT(1);
266 SEND_BIT(0);
267 }
268
269 // Download the fpga image starting at current stream position with length FpgaImageLen bytes
270 static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
271 {
272 int i=0;
273
274 AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
275 AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
276 HIGH(GPIO_FPGA_ON); // ensure everything is powered on
277
278 SpinDelay(50);
279
280 LED_D_ON();
281
282 // These pins are inputs
283 AT91C_BASE_PIOA->PIO_ODR =
284 GPIO_FPGA_NINIT |
285 GPIO_FPGA_DONE;
286 // PIO controls the following pins
287 AT91C_BASE_PIOA->PIO_PER =
288 GPIO_FPGA_NINIT |
289 GPIO_FPGA_DONE;
290 // Enable pull-ups
291 AT91C_BASE_PIOA->PIO_PPUER =
292 GPIO_FPGA_NINIT |
293 GPIO_FPGA_DONE;
294
295 // setup initial logic state
296 HIGH(GPIO_FPGA_NPROGRAM);
297 LOW(GPIO_FPGA_CCLK);
298 LOW(GPIO_FPGA_DIN);
299 // These pins are outputs
300 AT91C_BASE_PIOA->PIO_OER =
301 GPIO_FPGA_NPROGRAM |
302 GPIO_FPGA_CCLK |
303 GPIO_FPGA_DIN;
304
305 // enter FPGA configuration mode
306 LOW(GPIO_FPGA_NPROGRAM);
307 SpinDelay(50);
308 HIGH(GPIO_FPGA_NPROGRAM);
309
310 i=100000;
311 // wait for FPGA ready to accept data signal
312 while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
313 i--;
314 }
315
316 // crude error indicator, leave both red LEDs on and return
317 if (i==0){
318 LED_C_ON();
319 LED_D_ON();
320 return;
321 }
322
323 for(i = 0; i < FpgaImageLen; i++) {
324 int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
325 if (b < 0) {
326 Dbprintf("Error %d during FpgaDownload", b);
327 break;
328 }
329 DownloadFPGA_byte(b);
330 }
331
332 // continue to clock FPGA until ready signal goes high
333 i=100000;
334 while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
335 HIGH(GPIO_FPGA_CCLK);
336 LOW(GPIO_FPGA_CCLK);
337 }
338 // crude error indicator, leave both red LEDs on and return
339 if (i==0){
340 LED_C_ON();
341 LED_D_ON();
342 return;
343 }
344 LED_D_OFF();
345 }
346
347
348 /* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
349 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
350 * After that the format is 1 byte section type (ASCII character), 2 byte length
351 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
352 * length.
353 */
354 static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
355 {
356 int result = 0;
357 #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
358 uint16_t numbytes = 0;
359 while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
360 char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
361 numbytes++;
362 unsigned int current_length = 0;
363 if(current_name < 'a' || current_name > 'e') {
364 /* Strange section name, abort */
365 break;
366 }
367 current_length = 0;
368 switch(current_name) {
369 case 'e':
370 /* Four byte length field */
371 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
372 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
373 numbytes += 2;
374 default: /* Fall through, two byte length field */
375 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
376 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
377 numbytes += 2;
378 }
379
380 if(current_name != 'e' && current_length > 255) {
381 /* Maybe a parse error */
382 break;
383 }
384
385 if(current_name == section_name) {
386 /* Found it */
387 *section_length = current_length;
388 result = 1;
389 break;
390 }
391
392 for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
393 get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
394 numbytes++;
395 }
396 }
397
398 return result;
399 }
400
401
402 //----------------------------------------------------------------------------
403 // Check which FPGA image is currently loaded (if any). If necessary
404 // decompress and load the correct (HF or LF) image to the FPGA
405 //----------------------------------------------------------------------------
406 void FpgaDownloadAndGo(int bitstream_version)
407 {
408 z_stream compressed_fpga_stream;
409 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
410
411 // check whether or not the bitstream is already loaded
412 if (downloaded_bitstream == bitstream_version)
413 return;
414
415 // make sure that we have enough memory to decompress
416 BigBuf_free(); BigBuf_Clear_ext(false);
417
418 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
419 return;
420 }
421
422 unsigned int bitstream_length;
423 if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
424 DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
425 downloaded_bitstream = bitstream_version;
426 }
427
428 inflateEnd(&compressed_fpga_stream);
429
430 // free eventually allocated BigBuf memory
431 BigBuf_free(); BigBuf_Clear_ext(false);
432 }
433
434
435 //-----------------------------------------------------------------------------
436 // Gather version information from FPGA image. Needs to decompress the begin
437 // of the respective (HF or LF) image.
438 // Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
439 // advisable to call this only once and store the results for later use.
440 //-----------------------------------------------------------------------------
441 void FpgaGatherVersion(int bitstream_version, char *dst, int len)
442 {
443 unsigned int fpga_info_len;
444 char tempstr[40] = {0x00};
445 z_stream compressed_fpga_stream;
446 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
447
448 dst[0] = '\0';
449
450 // ensure that we can allocate enough memory for decompression:
451 BigBuf_free(); BigBuf_Clear_ext(false);
452
453 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
454 return;
455
456 if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
457 for (uint16_t i = 0; i < fpga_info_len; i++) {
458 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
459 if (i < sizeof(tempstr)) {
460 tempstr[i] = c;
461 }
462 }
463 if (!memcmp("fpga_lf", tempstr, 7))
464 strncat(dst, "LF ", len-1);
465 else if (!memcmp("fpga_hf", tempstr, 7))
466 strncat(dst, "HF ", len-1);
467 }
468 strncat(dst, "FPGA image built", len-1);
469 if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
470 strncat(dst, " for ", len-1);
471 for (uint16_t i = 0; i < fpga_info_len; i++) {
472 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
473 if (i < sizeof(tempstr)) {
474 tempstr[i] = c;
475 }
476 }
477 strncat(dst, tempstr, len-1);
478 }
479 if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
480 strncat(dst, " on ", len-1);
481 for (uint16_t i = 0; i < fpga_info_len; i++) {
482 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
483 if (i < sizeof(tempstr)) {
484 tempstr[i] = c;
485 }
486 }
487 strncat(dst, tempstr, len-1);
488 }
489 if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
490 strncat(dst, " at ", len-1);
491 for (uint16_t i = 0; i < fpga_info_len; i++) {
492 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
493 if (i < sizeof(tempstr)) {
494 tempstr[i] = c;
495 }
496 }
497 strncat(dst, tempstr, len-1);
498 }
499
500 strncat(dst, "\n", len-1);
501
502 inflateEnd(&compressed_fpga_stream);
503 }
504
505
506 //-----------------------------------------------------------------------------
507 // Send a 16 bit command/data pair to the FPGA.
508 // The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
509 // where C is the 4 bit command and D is the 12 bit data
510 //-----------------------------------------------------------------------------
511 void FpgaSendCommand(uint16_t cmd, uint16_t v)
512 {
513 SetupSpi(SPI_FPGA_MODE);
514 while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
515 AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
516 }
517 //-----------------------------------------------------------------------------
518 // Write the FPGA setup word (that determines what mode the logic is in, read
519 // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
520 // avoid changing this function's occurence everywhere in the source code.
521 //-----------------------------------------------------------------------------
522 void FpgaWriteConfWord(uint8_t v)
523 {
524 FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
525 }
526
527 //-----------------------------------------------------------------------------
528 // Set up the CMOS switches that mux the ADC: four switches, independently
529 // closable, but should only close one at a time. Not an FPGA thing, but
530 // the samples from the ADC always flow through the FPGA.
531 //-----------------------------------------------------------------------------
532 void SetAdcMuxFor(uint32_t whichGpio)
533 {
534 AT91C_BASE_PIOA->PIO_OER =
535 GPIO_MUXSEL_HIPKD |
536 GPIO_MUXSEL_LOPKD |
537 GPIO_MUXSEL_LORAW |
538 GPIO_MUXSEL_HIRAW;
539
540 AT91C_BASE_PIOA->PIO_PER =
541 GPIO_MUXSEL_HIPKD |
542 GPIO_MUXSEL_LOPKD |
543 GPIO_MUXSEL_LORAW |
544 GPIO_MUXSEL_HIRAW;
545
546 LOW(GPIO_MUXSEL_HIPKD);
547 LOW(GPIO_MUXSEL_HIRAW);
548 LOW(GPIO_MUXSEL_LORAW);
549 LOW(GPIO_MUXSEL_LOPKD);
550
551 HIGH(whichGpio);
552 }
553
554 void Fpga_print_status(void)
555 {
556 Dbprintf("Fgpa");
557 if(downloaded_bitstream == FPGA_BITSTREAM_HF) Dbprintf(" mode.............HF");
558 else if(downloaded_bitstream == FPGA_BITSTREAM_LF) Dbprintf(" mode.............LF");
559 else Dbprintf(" mode.............%d", downloaded_bitstream);
560 }
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