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[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 #ifndef SHORT_COIL
23 # define SHORT_COIL() LOW(GPIO_SSC_DOUT)
24 #endif
25 #ifndef OPEN_COIL
26 # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
27 #endif
28
29 /**
30 * Function to do a modulation and then get samples.
31 * @param delay_off
32 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
33 * @param useHighFreg
34 * @param command
35 */
36 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
37 {
38 /* Make sure the tag is reset */
39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
41 SpinDelay(200);
42
43 uint16_t period_0 = periods >> 16;
44 uint16_t period_1 = periods & 0xFFFF;
45
46 // 95 == 125 KHz 88 == 124.8 KHz
47 int divisor_used = (useHighFreq) ? 88 : 95;
48 sample_config sc = { 0,0,1, divisor_used, 0};
49 setSamplingConfig(&sc);
50
51 //clear read buffer
52 BigBuf_Clear_keep_EM();
53
54 LFSetupFPGAForADC(sc.divisor, 1);
55
56 // And a little more time for the tag to fully power up
57 SpinDelay(50);
58
59 // now modulate the reader field
60 while(*command != '\0' && *command != ' ') {
61 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
62 LED_D_OFF();
63 WaitUS(delay_off);
64 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
65
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
67 LED_D_ON();
68 if(*(command++) == '0')
69 WaitUS(period_0);
70 else
71 WaitUS(period_1);
72 }
73 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
74 LED_D_OFF();
75 WaitUS(delay_off);
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
78
79 // now do the read
80 DoAcquisition_config(false);
81 }
82
83 /* blank r/w tag data stream
84 ...0000000000000000 01111111
85 1010101010101010101010101010101010101010101010101010101010101010
86 0011010010100001
87 01111111
88 101010101010101[0]000...
89
90 [5555fe852c5555555555555555fe0000]
91 */
92 void ReadTItag(void)
93 {
94 StartTicks();
95 // some hardcoded initial params
96 // when we read a TI tag we sample the zerocross line at 2Mhz
97 // TI tags modulate a 1 as 16 cycles of 123.2Khz
98 // TI tags modulate a 0 as 16 cycles of 134.2Khz
99 #define FSAMPLE 2000000
100 #define FREQLO 123200
101 #define FREQHI 134200
102
103 signed char *dest = (signed char *)BigBuf_get_addr();
104 uint16_t n = BigBuf_max_traceLen();
105 // 128 bit shift register [shift3:shift2:shift1:shift0]
106 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
107
108 int i, cycles=0, samples=0;
109 // how many sample points fit in 16 cycles of each frequency
110 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
111 // when to tell if we're close enough to one freq or another
112 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
113
114 // TI tags charge at 134.2Khz
115 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
117
118 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
119 // connects to SSP_DIN and the SSP_DOUT logic level controls
120 // whether we're modulating the antenna (high)
121 // or listening to the antenna (low)
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
123
124 // get TI tag data into the buffer
125 AcquireTiType();
126
127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
128
129 for (i=0; i<n-1; i++) {
130 // count cycles by looking for lo to hi zero crossings
131 if ( (dest[i]<0) && (dest[i+1]>0) ) {
132 cycles++;
133 // after 16 cycles, measure the frequency
134 if (cycles>15) {
135 cycles=0;
136 samples=i-samples; // number of samples in these 16 cycles
137
138 // TI bits are coming to us lsb first so shift them
139 // right through our 128 bit right shift register
140 shift0 = (shift0>>1) | (shift1 << 31);
141 shift1 = (shift1>>1) | (shift2 << 31);
142 shift2 = (shift2>>1) | (shift3 << 31);
143 shift3 >>= 1;
144
145 // check if the cycles fall close to the number
146 // expected for either the low or high frequency
147 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
148 // low frequency represents a 1
149 shift3 |= (1<<31);
150 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
151 // high frequency represents a 0
152 } else {
153 // probably detected a gay waveform or noise
154 // use this as gaydar or discard shift register and start again
155 shift3 = shift2 = shift1 = shift0 = 0;
156 }
157 samples = i;
158
159 // for each bit we receive, test if we've detected a valid tag
160
161 // if we see 17 zeroes followed by 6 ones, we might have a tag
162 // remember the bits are backwards
163 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
164 // if start and end bytes match, we have a tag so break out of the loop
165 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
166 cycles = 0xF0B; //use this as a flag (ugly but whatever)
167 break;
168 }
169 }
170 }
171 }
172 }
173
174 // if flag is set we have a tag
175 if (cycles!=0xF0B) {
176 DbpString("Info: No valid tag detected.");
177 } else {
178 // put 64 bit data into shift1 and shift0
179 shift0 = (shift0>>24) | (shift1 << 8);
180 shift1 = (shift1>>24) | (shift2 << 8);
181
182 // align 16 bit crc into lower half of shift2
183 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
184
185 // if r/w tag, check ident match
186 if (shift3 & (1<<15) ) {
187 DbpString("Info: TI tag is rewriteable");
188 // only 15 bits compare, last bit of ident is not valid
189 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
190 DbpString("Error: Ident mismatch!");
191 } else {
192 DbpString("Info: TI tag ident is valid");
193 }
194 } else {
195 DbpString("Info: TI tag is readonly");
196 }
197
198 // WARNING the order of the bytes in which we calc crc below needs checking
199 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
200 // bytes in reverse or something
201 // calculate CRC
202 uint32_t crc=0;
203
204 crc = update_crc16(crc, (shift0)&0xff);
205 crc = update_crc16(crc, (shift0>>8)&0xff);
206 crc = update_crc16(crc, (shift0>>16)&0xff);
207 crc = update_crc16(crc, (shift0>>24)&0xff);
208 crc = update_crc16(crc, (shift1)&0xff);
209 crc = update_crc16(crc, (shift1>>8)&0xff);
210 crc = update_crc16(crc, (shift1>>16)&0xff);
211 crc = update_crc16(crc, (shift1>>24)&0xff);
212
213 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
214 if (crc != (shift2&0xffff)) {
215 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
216 } else {
217 DbpString("Info: CRC is good");
218 }
219 }
220 StopTicks();
221 }
222
223 void WriteTIbyte(uint8_t b)
224 {
225 int i = 0;
226
227 // modulate 8 bits out to the antenna
228 for (i=0; i<8; i++)
229 {
230 if ( b & ( 1 << i ) ) {
231 // stop modulating antenna 1ms
232 LOW(GPIO_SSC_DOUT);
233 WaitUS(1000);
234 // modulate antenna 1ms
235 HIGH(GPIO_SSC_DOUT);
236 WaitUS(1000);
237 } else {
238 // stop modulating antenna 1ms
239 LOW(GPIO_SSC_DOUT);
240 WaitUS(300);
241 // modulate antenna 1m
242 HIGH(GPIO_SSC_DOUT);
243 WaitUS(1700);
244 }
245 }
246 }
247
248 void AcquireTiType(void)
249 {
250 int i, j, n;
251 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
252 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
253 #define TIBUFLEN 1250
254
255 // clear buffer
256 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
257
258 //clear buffer now so it does not interfere with timing later
259 BigBuf_Clear_ext(false);
260
261 // Set up the synchronous serial port
262 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
263 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
264
265 // steal this pin from the SSP and use it to control the modulation
266 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
267 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
268
269 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
270 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
271
272 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
273 // 48/2 = 24 MHz clock must be divided by 12
274 AT91C_BASE_SSC->SSC_CMR = 12;
275
276 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
277 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
278 AT91C_BASE_SSC->SSC_TCMR = 0;
279 AT91C_BASE_SSC->SSC_TFMR = 0;
280 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
281 LED_D_ON();
282
283 // modulate antenna
284 HIGH(GPIO_SSC_DOUT);
285
286 // Charge TI tag for 50ms.
287 WaitMS(50);
288
289 // stop modulating antenna and listen
290 LOW(GPIO_SSC_DOUT);
291
292 LED_D_OFF();
293
294 i = 0;
295 for(;;) {
296 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
297 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
298 i++; if(i >= TIBUFLEN) break;
299 }
300 WDT_HIT();
301 }
302
303 // return stolen pin to SSP
304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
306
307 char *dest = (char *)BigBuf_get_addr();
308 n = TIBUFLEN * 32;
309
310 // unpack buffer
311 for (i = TIBUFLEN-1; i >= 0; i--) {
312 for (j = 0; j < 32; j++) {
313 if(buf[i] & (1 << j)) {
314 dest[--n] = 1;
315 } else {
316 dest[--n] = -1;
317 }
318 }
319 }
320 }
321
322 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
323 // if crc provided, it will be written with the data verbatim (even if bogus)
324 // if not provided a valid crc will be computed from the data and written.
325 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
326 {
327 StartTicks();
328 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
329 if(crc == 0) {
330 crc = update_crc16(crc, (idlo)&0xff);
331 crc = update_crc16(crc, (idlo>>8)&0xff);
332 crc = update_crc16(crc, (idlo>>16)&0xff);
333 crc = update_crc16(crc, (idlo>>24)&0xff);
334 crc = update_crc16(crc, (idhi)&0xff);
335 crc = update_crc16(crc, (idhi>>8)&0xff);
336 crc = update_crc16(crc, (idhi>>16)&0xff);
337 crc = update_crc16(crc, (idhi>>24)&0xff);
338 }
339 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
340
341 // TI tags charge at 134.2Khz
342 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
343 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
344 // connects to SSP_DIN and the SSP_DOUT logic level controls
345 // whether we're modulating the antenna (high)
346 // or listening to the antenna (low)
347 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
348 LED_A_ON();
349
350 // steal this pin from the SSP and use it to control the modulation
351 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
352 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
353
354 // writing algorithm:
355 // a high bit consists of a field off for 1ms and field on for 1ms
356 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
357 // initiate a charge time of 50ms (field on) then immediately start writing bits
358 // start by writing 0xBB (keyword) and 0xEB (password)
359 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
360 // finally end with 0x0300 (write frame)
361 // all data is sent lsb first
362 // finish with 15ms programming time
363
364 // modulate antenna
365 HIGH(GPIO_SSC_DOUT);
366 WaitMS(50); // charge time
367
368 WriteTIbyte(0xbb); // keyword
369 WriteTIbyte(0xeb); // password
370 WriteTIbyte( (idlo )&0xff );
371 WriteTIbyte( (idlo>>8 )&0xff );
372 WriteTIbyte( (idlo>>16)&0xff );
373 WriteTIbyte( (idlo>>24)&0xff );
374 WriteTIbyte( (idhi )&0xff );
375 WriteTIbyte( (idhi>>8 )&0xff );
376 WriteTIbyte( (idhi>>16)&0xff );
377 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
378 WriteTIbyte( (crc )&0xff ); // crc lo
379 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
380 WriteTIbyte(0x00); // write frame lo
381 WriteTIbyte(0x03); // write frame hi
382 HIGH(GPIO_SSC_DOUT);
383 WaitMS(50); // programming time
384
385 LED_A_OFF();
386
387 // get TI tag data into the buffer
388 AcquireTiType();
389
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
391 DbpString("Now use `lf ti read` to check");
392 StopTicks();
393 }
394
395 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
396 {
397 int i = 0;
398 uint8_t *buf = BigBuf_get_addr();
399
400 //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
401 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
402
403 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
404 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
405 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
406
407 StartTicks();
408
409 for(;;) {
410 WDT_HIT();
411
412 if (ledcontrol) LED_D_ON();
413
414 // wait until SSC_CLK goes HIGH
415 // used as a simple detection of a reader field?
416 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
417 WDT_HIT();
418 if ( usb_poll_validate_length() || BUTTON_PRESS() )
419 goto OUT;
420 }
421
422 if(buf[i])
423 OPEN_COIL();
424 else
425 SHORT_COIL();
426
427 if (ledcontrol) LED_D_OFF();
428
429 //wait until SSC_CLK goes LOW
430 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
431 WDT_HIT();
432 if ( usb_poll_validate_length() || BUTTON_PRESS() )
433 goto OUT;
434 }
435
436 i++;
437 if(i == period) {
438 i = 0;
439 if (gap) {
440 WDT_HIT();
441 SHORT_COIL();
442 WaitUS(gap);
443 }
444 }
445 }
446 OUT:
447 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
448 StopTicks();
449 LED_D_OFF();
450 DbpString("Simulation stopped");
451 return;
452 }
453
454 #define DEBUG_FRAME_CONTENTS 1
455 void SimulateTagLowFrequencyBidir(int divisor, int t0)
456 {
457 }
458
459 // compose fc/8 fc/10 waveform (FSK2)
460 static void fc(int c, int *n)
461 {
462 uint8_t *dest = BigBuf_get_addr();
463 int idx;
464
465 // for when we want an fc8 pattern every 4 logical bits
466 if(c==0) {
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 }
476
477 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
478 if(c==8) {
479 for (idx=0; idx<6; idx++) {
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 }
489 }
490
491 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
492 if(c==10) {
493 for (idx=0; idx<5; idx++) {
494 dest[((*n)++)]=1;
495 dest[((*n)++)]=1;
496 dest[((*n)++)]=1;
497 dest[((*n)++)]=1;
498 dest[((*n)++)]=1;
499 dest[((*n)++)]=0;
500 dest[((*n)++)]=0;
501 dest[((*n)++)]=0;
502 dest[((*n)++)]=0;
503 dest[((*n)++)]=0;
504 }
505 }
506 }
507 // compose fc/X fc/Y waveform (FSKx)
508 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
509 {
510 uint8_t *dest = BigBuf_get_addr();
511 uint8_t halfFC = fc/2;
512 uint8_t wavesPerClock = clock/fc;
513 uint8_t mod = clock % fc; //modifier
514 uint8_t modAdj = fc/mod; //how often to apply modifier
515 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
516 // loop through clock - step field clock
517 for (uint8_t idx=0; idx < wavesPerClock; idx++){
518 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
519 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
520 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
521 *n += fc;
522 }
523 if (mod>0) (*modCnt)++;
524 if ((mod>0) && modAdjOk){ //fsk2
525 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
526 memset(dest+(*n), 0, fc-halfFC);
527 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
528 *n += fc;
529 }
530 }
531 if (mod>0 && !modAdjOk){ //fsk1
532 memset(dest+(*n), 0, mod-(mod/2));
533 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
534 *n += mod;
535 }
536 }
537
538 // prepare a waveform pattern in the buffer based on the ID given then
539 // simulate a HID tag until the button is pressed
540 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
541 {
542 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
543 set_tracing(FALSE);
544
545 int n = 0, i = 0;
546 /*
547 HID tag bitstream format
548 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
549 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
550 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
551 A fc8 is inserted before every 4 bits
552 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
553 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
554 */
555
556 if (hi > 0xFFF) {
557 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
558 return;
559 }
560 fc(0,&n);
561 // special start of frame marker containing invalid bit sequences
562 fc(8, &n); fc(8, &n); // invalid
563 fc(8, &n); fc(10, &n); // logical 0
564 fc(10, &n); fc(10, &n); // invalid
565 fc(8, &n); fc(10, &n); // logical 0
566
567 WDT_HIT();
568 // manchester encode bits 43 to 32
569 for (i=11; i>=0; i--) {
570 if ((i%4)==3) fc(0,&n);
571 if ((hi>>i)&1) {
572 fc(10, &n); fc(8, &n); // low-high transition
573 } else {
574 fc(8, &n); fc(10, &n); // high-low transition
575 }
576 }
577
578 WDT_HIT();
579 // manchester encode bits 31 to 0
580 for (i=31; i>=0; i--) {
581 if ((i%4)==3) fc(0,&n);
582 if ((lo>>i)&1) {
583 fc(10, &n); fc(8, &n); // low-high transition
584 } else {
585 fc(8, &n); fc(10, &n); // high-low transition
586 }
587 }
588 WDT_HIT();
589
590 if (ledcontrol) LED_A_ON();
591 SimulateTagLowFrequency(n, 0, ledcontrol);
592 if (ledcontrol) LED_A_OFF();
593 }
594
595 // prepare a waveform pattern in the buffer based on the ID given then
596 // simulate a FSK tag until the button is pressed
597 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
598 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
599 {
600 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
601
602 // free eventually allocated BigBuf memory
603 BigBuf_free(); BigBuf_Clear_ext(false);
604 clear_trace();
605 set_tracing(FALSE);
606
607 int ledcontrol = 1, n = 0, i = 0;
608 uint8_t fcHigh = arg1 >> 8;
609 uint8_t fcLow = arg1 & 0xFF;
610 uint16_t modCnt = 0;
611 uint8_t clk = arg2 & 0xFF;
612 uint8_t invert = (arg2 >> 8) & 1;
613
614 for (i=0; i<size; i++){
615
616 if (BitStream[i] == invert)
617 fcAll(fcLow, &n, clk, &modCnt);
618 else
619 fcAll(fcHigh, &n, clk, &modCnt);
620 }
621 WDT_HIT();
622
623 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
624
625 if (ledcontrol) LED_A_ON();
626 SimulateTagLowFrequency(n, 0, ledcontrol);
627 if (ledcontrol) LED_A_OFF();
628 }
629
630 // compose ask waveform for one bit(ASK)
631 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
632 {
633 uint8_t *dest = BigBuf_get_addr();
634 uint8_t halfClk = clock/2;
635 // c = current bit 1 or 0
636 if (manchester==1){
637 memset(dest+(*n), c, halfClk);
638 memset(dest+(*n) + halfClk, c^1, halfClk);
639 } else {
640 memset(dest+(*n), c, clock);
641 }
642 *n += clock;
643 }
644
645 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
646 {
647 uint8_t *dest = BigBuf_get_addr();
648 uint8_t halfClk = clock/2;
649 if (c){
650 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
651 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
652 } else {
653 memset(dest+(*n), c ^ *phase, clock);
654 *phase ^= 1;
655 }
656 *n += clock;
657 }
658
659 static void stAskSimBit(int *n, uint8_t clock) {
660 uint8_t *dest = BigBuf_get_addr();
661 uint8_t halfClk = clock/2;
662 //ST = .5 high .5 low 1.5 high .5 low 1 high
663 memset(dest+(*n), 1, halfClk);
664 memset(dest+(*n) + halfClk, 0, halfClk);
665 memset(dest+(*n) + clock, 1, clock + halfClk);
666 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
667 memset(dest+(*n) + clock*3, 1, clock);
668 *n += clock*4;
669 }
670
671 // args clock, ask/man or askraw, invert, transmission separator
672 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
673 {
674 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
675 set_tracing(FALSE);
676
677 int ledcontrol = 1, n = 0, i = 0;
678 uint8_t clk = (arg1 >> 8) & 0xFF;
679 uint8_t encoding = arg1 & 0xFF;
680 uint8_t separator = arg2 & 1;
681 uint8_t invert = (arg2 >> 8) & 1;
682
683 if (encoding == 2){ //biphase
684 uint8_t phase = 0;
685 for (i=0; i<size; i++){
686 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
687 }
688 if (phase == 1) { //run a second set inverted to keep phase in check
689 for (i=0; i<size; i++){
690 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
691 }
692 }
693 } else { // ask/manchester || ask/raw
694 for (i=0; i<size; i++){
695 askSimBit(BitStream[i]^invert, &n, clk, encoding);
696 }
697 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
698 for (i=0; i<size; i++){
699 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
700 }
701 }
702 }
703 if (separator==1 && encoding == 1)
704 stAskSimBit(&n, clk);
705 else if (separator==1)
706 Dbprintf("sorry but separator option not yet available");
707
708 WDT_HIT();
709
710 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
711
712 if (ledcontrol) LED_A_ON();
713 SimulateTagLowFrequency(n, 0, ledcontrol);
714 if (ledcontrol) LED_A_OFF();
715 }
716
717 //carrier can be 2,4 or 8
718 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
719 {
720 uint8_t *dest = BigBuf_get_addr();
721 uint8_t halfWave = waveLen/2;
722 //uint8_t idx;
723 int i = 0;
724 if (phaseChg){
725 // write phase change
726 memset(dest+(*n), *curPhase^1, halfWave);
727 memset(dest+(*n) + halfWave, *curPhase, halfWave);
728 *n += waveLen;
729 *curPhase ^= 1;
730 i += waveLen;
731 }
732 //write each normal clock wave for the clock duration
733 for (; i < clk; i+=waveLen){
734 memset(dest+(*n), *curPhase, halfWave);
735 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
736 *n += waveLen;
737 }
738 }
739
740 // args clock, carrier, invert,
741 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
742 {
743 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
744 set_tracing(FALSE);
745
746 int ledcontrol = 1, n = 0, i = 0;
747 uint8_t clk = arg1 >> 8;
748 uint8_t carrier = arg1 & 0xFF;
749 uint8_t invert = arg2 & 0xFF;
750 uint8_t curPhase = 0;
751 for (i=0; i<size; i++){
752 if (BitStream[i] == curPhase){
753 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
754 } else {
755 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
756 }
757 }
758
759 WDT_HIT();
760
761 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
762
763 if (ledcontrol) LED_A_ON();
764 SimulateTagLowFrequency(n, 0, ledcontrol);
765 if (ledcontrol) LED_A_OFF();
766 }
767
768 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
769 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
770 {
771 uint8_t *dest = BigBuf_get_addr();
772 size_t size = 0;
773 uint32_t hi2=0, hi=0, lo=0;
774 int idx=0;
775 // Configure to go in 125Khz listen mode
776 LFSetupFPGAForADC(95, true);
777
778 //clear read buffer
779 BigBuf_Clear_keep_EM();
780
781 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
782
783 WDT_HIT();
784 if (ledcontrol) LED_A_ON();
785
786 DoAcquisition_default(-1,true);
787 // FSK demodulator
788 size = 50*128*2; //big enough to catch 2 sequences of largest format
789 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
790
791 if (idx>0 && lo>0 && (size==96 || size==192)){
792 // go over previously decoded manchester data and decode into usable tag ID
793 if (hi2 != 0){ //extra large HID tags 88/192 bits
794 Dbprintf("TAG ID: %x%08x%08x (%d)",
795 (unsigned int) hi2,
796 (unsigned int) hi,
797 (unsigned int) lo,
798 (unsigned int) (lo>>1) & 0xFFFF
799 );
800 } else { //standard HID tags 44/96 bits
801 uint8_t bitlen = 0;
802 uint32_t fc = 0;
803 uint32_t cardnum = 0;
804
805 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
806 uint32_t lo2=0;
807 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
808 uint8_t idx3 = 1;
809 while(lo2 > 1){ //find last bit set to 1 (format len bit)
810 lo2=lo2 >> 1;
811 idx3++;
812 }
813 bitlen = idx3+19;
814 fc =0;
815 cardnum=0;
816 if(bitlen == 26){
817 cardnum = (lo>>1)&0xFFFF;
818 fc = (lo>>17)&0xFF;
819 }
820 if(bitlen == 37){
821 cardnum = (lo>>1)&0x7FFFF;
822 fc = ((hi&0xF)<<12)|(lo>>20);
823 }
824 if(bitlen == 34){
825 cardnum = (lo>>1)&0xFFFF;
826 fc= ((hi&1)<<15)|(lo>>17);
827 }
828 if(bitlen == 35){
829 cardnum = (lo>>1)&0xFFFFF;
830 fc = ((hi&1)<<11)|(lo>>21);
831 }
832 }
833 else { //if bit 38 is not set then 37 bit format is used
834 bitlen= 37;
835 fc =0;
836 cardnum=0;
837 if(bitlen==37){
838 cardnum = (lo>>1)&0x7FFFF;
839 fc = ((hi&0xF)<<12)|(lo>>20);
840 }
841 }
842 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
843 (unsigned int) hi,
844 (unsigned int) lo,
845 (unsigned int) (lo>>1) & 0xFFFF,
846 (unsigned int) bitlen,
847 (unsigned int) fc,
848 (unsigned int) cardnum);
849 }
850 if (findone){
851 if (ledcontrol) LED_A_OFF();
852 *high = hi;
853 *low = lo;
854 return;
855 }
856 // reset
857 }
858 hi2 = hi = lo = idx = 0;
859 WDT_HIT();
860 }
861 DbpString("Stopped");
862 if (ledcontrol) LED_A_OFF();
863 }
864
865 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
866 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
867 {
868 uint8_t *dest = BigBuf_get_addr();
869 size_t size;
870 int idx=0;
871 //clear read buffer
872 BigBuf_Clear_keep_EM();
873 // Configure to go in 125Khz listen mode
874 LFSetupFPGAForADC(95, true);
875
876 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
877
878 WDT_HIT();
879 if (ledcontrol) LED_A_ON();
880
881 DoAcquisition_default(-1,true);
882 // FSK demodulator
883 size = 50*128*2; //big enough to catch 2 sequences of largest format
884 idx = AWIDdemodFSK(dest, &size);
885
886 if (idx<=0 || size!=96) continue;
887 // Index map
888 // 0 10 20 30 40 50 60
889 // | | | | | | |
890 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
891 // -----------------------------------------------------------------------------
892 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
893 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
894 // |---26 bit---| |-----117----||-------------142-------------|
895 // b = format bit len, o = odd parity of last 3 bits
896 // f = facility code, c = card number
897 // w = wiegand parity
898 // (26 bit format shown)
899
900 //get raw ID before removing parities
901 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
902 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
903 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
904
905 size = removeParity(dest, idx+8, 4, 1, 88);
906 if (size != 66) continue;
907
908 // Index map
909 // 0 10 20 30 40 50 60
910 // | | | | | | |
911 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
912 // -----------------------------------------------------------------------------
913 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
914 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
915 // |26 bit| |-117--| |-----142------|
916 //
917 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
918 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
919 // |50 bit| |----4000------||-----------2248975-------------|
920 //
921 // b = format bit len, o = odd parity of last 3 bits
922 // f = facility code, c = card number
923 // w = wiegand parity
924
925 uint32_t fc = 0;
926 uint32_t cardnum = 0;
927 uint32_t code1 = 0;
928 uint32_t code2 = 0;
929 uint8_t fmtLen = bytebits_to_byte(dest,8);
930 switch(fmtLen) {
931 case 26:
932 fc = bytebits_to_byte(dest + 9, 8);
933 cardnum = bytebits_to_byte(dest + 17, 16);
934 code1 = bytebits_to_byte(dest + 8,fmtLen);
935 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
936 break;
937 case 50:
938 fc = bytebits_to_byte(dest + 9, 16);
939 cardnum = bytebits_to_byte(dest + 25, 32);
940 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
941 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
942 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
943 break;
944 default:
945 if (fmtLen > 32 ) {
946 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
947 code1 = bytebits_to_byte(dest+8,fmtLen-32);
948 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
949 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
950 } else {
951 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
952 code1 = bytebits_to_byte(dest+8,fmtLen);
953 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
954 }
955 break;
956 }
957 if (findone){
958 if (ledcontrol) LED_A_OFF();
959 return;
960 }
961 idx = 0;
962 WDT_HIT();
963 }
964 DbpString("Stopped");
965 if (ledcontrol) LED_A_OFF();
966 }
967
968 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
969 {
970 uint8_t *dest = BigBuf_get_addr();
971
972 size_t size=0, idx=0;
973 int clk=0, invert=0, errCnt=0, maxErr=20;
974 uint32_t hi=0;
975 uint64_t lo=0;
976 //clear read buffer
977 BigBuf_Clear_keep_EM();
978 // Configure to go in 125Khz listen mode
979 LFSetupFPGAForADC(95, true);
980
981 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
982
983 WDT_HIT();
984 if (ledcontrol) LED_A_ON();
985
986 DoAcquisition_default(-1,true);
987 size = BigBuf_max_traceLen();
988 //askdemod and manchester decode
989 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
990 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
991 WDT_HIT();
992
993 if (errCnt<0) continue;
994
995 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
996 if (errCnt){
997 if (size>64){
998 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
999 hi,
1000 (uint32_t)(lo>>32),
1001 (uint32_t)lo,
1002 (uint32_t)(lo&0xFFFF),
1003 (uint32_t)((lo>>16LL) & 0xFF),
1004 (uint32_t)(lo & 0xFFFFFF));
1005 } else {
1006 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1007 (uint32_t)(lo>>32),
1008 (uint32_t)lo,
1009 (uint32_t)(lo&0xFFFF),
1010 (uint32_t)((lo>>16LL) & 0xFF),
1011 (uint32_t)(lo & 0xFFFFFF));
1012 }
1013
1014 if (findone){
1015 if (ledcontrol) LED_A_OFF();
1016 *high=lo>>32;
1017 *low=lo & 0xFFFFFFFF;
1018 return;
1019 }
1020 }
1021 WDT_HIT();
1022 hi = lo = size = idx = 0;
1023 clk = invert = errCnt = 0;
1024 }
1025 DbpString("Stopped");
1026 if (ledcontrol) LED_A_OFF();
1027 }
1028
1029 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1030 {
1031 uint8_t *dest = BigBuf_get_addr();
1032 int idx=0;
1033 uint32_t code=0, code2=0;
1034 uint8_t version=0;
1035 uint8_t facilitycode=0;
1036 uint16_t number=0;
1037 uint8_t crc = 0;
1038 uint16_t calccrc = 0;
1039
1040 //clear read buffer
1041 BigBuf_Clear_keep_EM();
1042
1043 // Configure to go in 125Khz listen mode
1044 LFSetupFPGAForADC(95, true);
1045
1046 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1047 WDT_HIT();
1048 if (ledcontrol) LED_A_ON();
1049 DoAcquisition_default(-1,true);
1050 //fskdemod and get start index
1051 WDT_HIT();
1052 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1053 if (idx<0) continue;
1054 //valid tag found
1055
1056 //Index map
1057 //0 10 20 30 40 50 60
1058 //| | | | | | |
1059 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1060 //-----------------------------------------------------------------------------
1061 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1062 //
1063 //Checksum:
1064 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1065 //preamble F0 E0 01 03 B6 75
1066 // How to calc checksum,
1067 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1068 // F0 + E0 + 01 + 03 + B6 = 28A
1069 // 28A & FF = 8A
1070 // FF - 8A = 75
1071 // Checksum: 0x75
1072 //XSF(version)facility:codeone+codetwo
1073 //Handle the data
1074 if(findone){ //only print binary if we are doing one
1075 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1076 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1077 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1078 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1079 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1080 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1081 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1082 }
1083 code = bytebits_to_byte(dest+idx,32);
1084 code2 = bytebits_to_byte(dest+idx+32,32);
1085 version = bytebits_to_byte(dest+idx+27,8); //14,4
1086 facilitycode = bytebits_to_byte(dest+idx+18,8);
1087 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1088
1089 crc = bytebits_to_byte(dest+idx+54,8);
1090 for (uint8_t i=1; i<6; ++i)
1091 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1092 calccrc &= 0xff;
1093 calccrc = 0xff - calccrc;
1094
1095 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1096
1097 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1098 // if we're only looking for one tag
1099 if (findone){
1100 if (ledcontrol) LED_A_OFF();
1101 *high=code;
1102 *low=code2;
1103 return;
1104 }
1105 code=code2=0;
1106 version=facilitycode=0;
1107 number=0;
1108 idx=0;
1109
1110 WDT_HIT();
1111 }
1112 DbpString("Stopped");
1113 if (ledcontrol) LED_A_OFF();
1114 }
1115
1116 /*------------------------------
1117 * T5555/T5557/T5567/T5577 routines
1118 *------------------------------
1119 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1120 *
1121 * Relevant communication times in microsecond
1122 * To compensate antenna falling times shorten the write times
1123 * and enlarge the gap ones.
1124 * Q5 tags seems to have issues when these values changes.
1125 */
1126
1127 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
1128 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
1129 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
1130 #define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
1131 #define READ_GAP 15*8
1132
1133 // VALUES TAKEN FROM EM4x function: SendForward
1134 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1135 // WRITE_GAP = 128; (16*8)
1136 // WRITE_1 = 256 32*8; (32*8)
1137
1138 // These timings work for 4469/4269/4305 (with the 55*8 above)
1139 // WRITE_0 = 23*8 , 9*8
1140
1141 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1142 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1143 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1144 // T0 = TIMER_CLOCK1 / 125000 = 192
1145 // 1 Cycle = 8 microseconds(us) == 1 field clock
1146
1147 // new timer:
1148 // = 1us = 1.5ticks
1149 // 1fc = 8us = 12ticks
1150 void TurnReadLFOn(uint32_t delay) {
1151 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1152
1153 // measure antenna strength.
1154 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1155
1156 // Give it a bit of time for the resonant antenna to settle.
1157 WaitUS(delay);
1158 }
1159
1160 // Write one bit to card
1161 void T55xxWriteBit(int bit) {
1162 if (!bit)
1163 TurnReadLFOn(WRITE_0);
1164 else
1165 TurnReadLFOn(WRITE_1);
1166 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1167 WaitUS(WRITE_GAP);
1168 }
1169
1170 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1171 void T55xxResetRead(void) {
1172 LED_A_ON();
1173 //clear buffer now so it does not interfere with timing later
1174 BigBuf_Clear_keep_EM();
1175
1176 // Set up FPGA, 125kHz
1177 LFSetupFPGAForADC(95, true);
1178
1179 // Trigger T55x7 in mode.
1180 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1181 WaitUS(START_GAP);
1182
1183 // reset tag - op code 00
1184 T55xxWriteBit(0);
1185 T55xxWriteBit(0);
1186
1187 // Turn field on to read the response
1188 TurnReadLFOn(READ_GAP);
1189
1190 // Acquisition
1191 doT55x7Acquisition(BigBuf_max_traceLen());
1192
1193 // Turn the field off
1194 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1195 cmd_send(CMD_ACK,0,0,0,0,0);
1196 LED_A_OFF();
1197 }
1198
1199 // Write one card block in page 0, no lock
1200 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1201 LED_A_ON();
1202 bool PwdMode = arg & 0x1;
1203 uint8_t Page = (arg & 0x2)>>1;
1204 uint32_t i = 0;
1205
1206 // Set up FPGA, 125kHz
1207 LFSetupFPGAForADC(95, true);
1208
1209 // Trigger T55x7 in mode.
1210 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1211 WaitUS(START_GAP);
1212
1213 // Opcode 10
1214 T55xxWriteBit(1);
1215 T55xxWriteBit(Page); //Page 0
1216 if (PwdMode){
1217 // Send Pwd
1218 for (i = 0x80000000; i != 0; i >>= 1)
1219 T55xxWriteBit(Pwd & i);
1220 }
1221 // Send Lock bit
1222 T55xxWriteBit(0);
1223
1224 // Send Data
1225 for (i = 0x80000000; i != 0; i >>= 1)
1226 T55xxWriteBit(Data & i);
1227
1228 // Send Block number
1229 for (i = 0x04; i != 0; i >>= 1)
1230 T55xxWriteBit(Block & i);
1231
1232 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1233 // so wait a little more)
1234 TurnReadLFOn(20 * 1000);
1235
1236 //could attempt to do a read to confirm write took
1237 // as the tag should repeat back the new block
1238 // until it is reset, but to confirm it we would
1239 // need to know the current block 0 config mode
1240
1241 // turn field off
1242 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1243 LED_A_OFF();
1244 }
1245
1246 // Write one card block in page 0, no lock
1247 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1248 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1249 cmd_send(CMD_ACK,0,0,0,0,0);
1250 }
1251
1252 // Read one card block in page [page]
1253 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1254 LED_A_ON();
1255 bool PwdMode = arg0 & 0x1;
1256 uint8_t Page = (arg0 & 0x2) >> 1;
1257 uint32_t i = 0;
1258 bool RegReadMode = (Block == 0xFF);
1259
1260 //clear buffer now so it does not interfere with timing later
1261 BigBuf_Clear_keep_EM();
1262
1263 //make sure block is at max 7
1264 Block &= 0x7;
1265
1266 // Set up FPGA, 125kHz to power up the tag
1267 LFSetupFPGAForADC(95, true);
1268 SpinDelay(3);
1269
1270 // Trigger T55x7 Direct Access Mode with start gap
1271 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1272 WaitUS(START_GAP);
1273
1274 // Opcode 1[page]
1275 T55xxWriteBit(1);
1276 T55xxWriteBit(Page); //Page 0
1277
1278 if (PwdMode){
1279 // Send Pwd
1280 for (i = 0x80000000; i != 0; i >>= 1)
1281 T55xxWriteBit(Pwd & i);
1282 }
1283 // Send a zero bit separation
1284 T55xxWriteBit(0);
1285
1286 // Send Block number (if direct access mode)
1287 if (!RegReadMode)
1288 for (i = 0x04; i != 0; i >>= 1)
1289 T55xxWriteBit(Block & i);
1290
1291 // Turn field on to read the response
1292 TurnReadLFOn(READ_GAP);
1293
1294 // Acquisition
1295 doT55x7Acquisition(12000);
1296
1297 // Turn the field off
1298 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1299 cmd_send(CMD_ACK,0,0,0,0,0);
1300 LED_A_OFF();
1301 }
1302
1303 void T55xxWakeUp(uint32_t Pwd){
1304 LED_B_ON();
1305 uint32_t i = 0;
1306
1307 // Set up FPGA, 125kHz
1308 LFSetupFPGAForADC(95, true);
1309
1310 // Trigger T55x7 Direct Access Mode
1311 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1312 WaitUS(START_GAP);
1313
1314 // Opcode 10
1315 T55xxWriteBit(1);
1316 T55xxWriteBit(0); //Page 0
1317
1318 // Send Pwd
1319 for (i = 0x80000000; i != 0; i >>= 1)
1320 T55xxWriteBit(Pwd & i);
1321
1322 // Turn and leave field on to let the begin repeating transmission
1323 TurnReadLFOn(20*1000);
1324 }
1325
1326 /*-------------- Cloning routines -----------*/
1327 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1328 // write last block first and config block last (if included)
1329 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1330 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1331 }
1332
1333 // Copy HID id to card and setup block 0 config
1334 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1335 uint32_t data[] = {0,0,0,0,0,0,0};
1336 uint8_t last_block = 0;
1337
1338 if (longFMT){
1339 // Ensure no more than 84 bits supplied
1340 if (hi2 > 0xFFFFF) {
1341 DbpString("Tags can only have 84 bits.");
1342 return;
1343 }
1344 // Build the 6 data blocks for supplied 84bit ID
1345 last_block = 6;
1346 // load preamble (1D) & long format identifier (9E manchester encoded)
1347 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1348 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1349 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1350 data[3] = manchesterEncode2Bytes(hi >> 16);
1351 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1352 data[5] = manchesterEncode2Bytes(lo >> 16);
1353 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1354 } else {
1355 // Ensure no more than 44 bits supplied
1356 if (hi > 0xFFF) {
1357 DbpString("Tags can only have 44 bits.");
1358 return;
1359 }
1360 // Build the 3 data blocks for supplied 44bit ID
1361 last_block = 3;
1362 // load preamble
1363 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1364 data[2] = manchesterEncode2Bytes(lo >> 16);
1365 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1366 }
1367 // load chip config block
1368 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1369
1370 //TODO add selection of chip for Q5 or T55x7
1371 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1372
1373 LED_D_ON();
1374 // Program the data blocks for supplied ID
1375 // and the block 0 for HID format
1376 WriteT55xx(data, 0, last_block+1);
1377
1378 LED_D_OFF();
1379
1380 DbpString("DONE!");
1381 }
1382
1383 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1384 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1385 //TODO add selection of chip for Q5 or T55x7
1386 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1387 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1388
1389 LED_D_ON();
1390 // Program the data blocks for supplied ID
1391 // and the block 0 config
1392 WriteT55xx(data, 0, 3);
1393 LED_D_OFF();
1394 DbpString("DONE!");
1395 }
1396
1397 // Clone Indala 64-bit tag by UID to T55x7
1398 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1399 //Program the 2 data blocks for supplied 64bit UID
1400 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1401 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1402 //TODO add selection of chip for Q5 or T55x7
1403 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1404
1405 WriteT55xx(data, 0, 3);
1406 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1407 // T5567WriteBlock(0x603E1042,0);
1408 DbpString("DONE!");
1409 }
1410 // Clone Indala 224-bit tag by UID to T55x7
1411 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1412 //Program the 7 data blocks for supplied 224bit UID
1413 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1414 // and the block 0 for Indala224 format
1415 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1416 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1417 //TODO add selection of chip for Q5 or T55x7
1418 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1419 WriteT55xx(data, 0, 8);
1420 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1421 // T5567WriteBlock(0x603E10E2,0);
1422 DbpString("DONE!");
1423 }
1424 // clone viking tag to T55xx
1425 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1426 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1427 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1428 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1429 // Program the data blocks for supplied ID and the block 0 config
1430 WriteT55xx(data, 0, 3);
1431 LED_D_OFF();
1432 cmd_send(CMD_ACK,0,0,0,0,0);
1433 }
1434
1435 // Define 9bit header for EM410x tags
1436 #define EM410X_HEADER 0x1FF
1437 #define EM410X_ID_LENGTH 40
1438
1439 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1440 int i, id_bit;
1441 uint64_t id = EM410X_HEADER;
1442 uint64_t rev_id = 0; // reversed ID
1443 int c_parity[4]; // column parity
1444 int r_parity = 0; // row parity
1445 uint32_t clock = 0;
1446
1447 // Reverse ID bits given as parameter (for simpler operations)
1448 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1449 if (i < 32) {
1450 rev_id = (rev_id << 1) | (id_lo & 1);
1451 id_lo >>= 1;
1452 } else {
1453 rev_id = (rev_id << 1) | (id_hi & 1);
1454 id_hi >>= 1;
1455 }
1456 }
1457
1458 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1459 id_bit = rev_id & 1;
1460
1461 if (i % 4 == 0) {
1462 // Don't write row parity bit at start of parsing
1463 if (i)
1464 id = (id << 1) | r_parity;
1465 // Start counting parity for new row
1466 r_parity = id_bit;
1467 } else {
1468 // Count row parity
1469 r_parity ^= id_bit;
1470 }
1471
1472 // First elements in column?
1473 if (i < 4)
1474 // Fill out first elements
1475 c_parity[i] = id_bit;
1476 else
1477 // Count column parity
1478 c_parity[i % 4] ^= id_bit;
1479
1480 // Insert ID bit
1481 id = (id << 1) | id_bit;
1482 rev_id >>= 1;
1483 }
1484
1485 // Insert parity bit of last row
1486 id = (id << 1) | r_parity;
1487
1488 // Fill out column parity at the end of tag
1489 for (i = 0; i < 4; ++i)
1490 id = (id << 1) | c_parity[i];
1491
1492 // Add stop bit
1493 id <<= 1;
1494
1495 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1496 LED_D_ON();
1497
1498 // Write EM410x ID
1499 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1500
1501 clock = (card & 0xFF00) >> 8;
1502 clock = (clock == 0) ? 64 : clock;
1503 Dbprintf("Clock rate: %d", clock);
1504 if (card & 0xFF) { //t55x7
1505 clock = GetT55xxClockBit(clock);
1506 if (clock == 0) {
1507 Dbprintf("Invalid clock rate: %d", clock);
1508 return;
1509 }
1510 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1511 } else { //t5555 (Q5)
1512 clock = (clock-2)>>1; //n = (RF-2)/2
1513 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1514 }
1515
1516 WriteT55xx(data, 0, 3);
1517
1518 LED_D_OFF();
1519 Dbprintf("Tag %s written with 0x%08x%08x\n",
1520 card ? "T55x7":"T5555",
1521 (uint32_t)(id >> 32),
1522 (uint32_t)id);
1523 }
1524
1525 //-----------------------------------
1526 // EM4469 / EM4305 routines
1527 //-----------------------------------
1528 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1529 #define FWD_CMD_WRITE 0xA
1530 #define FWD_CMD_READ 0x9
1531 #define FWD_CMD_DISABLE 0x5
1532
1533 uint8_t forwardLink_data[64]; //array of forwarded bits
1534 uint8_t * forward_ptr; //ptr for forward message preparation
1535 uint8_t fwd_bit_sz; //forwardlink bit counter
1536 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1537
1538 //====================================================================
1539 // prepares command bits
1540 // see EM4469 spec
1541 //====================================================================
1542 //--------------------------------------------------------------------
1543 // VALUES TAKEN FROM EM4x function: SendForward
1544 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1545 // WRITE_GAP = 128; (16*8)
1546 // WRITE_1 = 256 32*8; (32*8)
1547
1548 // These timings work for 4469/4269/4305 (with the 55*8 above)
1549 // WRITE_0 = 23*8 , 9*8
1550
1551 uint8_t Prepare_Cmd( uint8_t cmd ) {
1552
1553 *forward_ptr++ = 0; //start bit
1554 *forward_ptr++ = 0; //second pause for 4050 code
1555
1556 *forward_ptr++ = cmd;
1557 cmd >>= 1;
1558 *forward_ptr++ = cmd;
1559 cmd >>= 1;
1560 *forward_ptr++ = cmd;
1561 cmd >>= 1;
1562 *forward_ptr++ = cmd;
1563
1564 return 6; //return number of emited bits
1565 }
1566
1567 //====================================================================
1568 // prepares address bits
1569 // see EM4469 spec
1570 //====================================================================
1571 uint8_t Prepare_Addr( uint8_t addr ) {
1572
1573 register uint8_t line_parity;
1574
1575 uint8_t i;
1576 line_parity = 0;
1577 for(i=0;i<6;i++) {
1578 *forward_ptr++ = addr;
1579 line_parity ^= addr;
1580 addr >>= 1;
1581 }
1582
1583 *forward_ptr++ = (line_parity & 1);
1584
1585 return 7; //return number of emited bits
1586 }
1587
1588 //====================================================================
1589 // prepares data bits intreleaved with parity bits
1590 // see EM4469 spec
1591 //====================================================================
1592 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1593
1594 register uint8_t line_parity;
1595 register uint8_t column_parity;
1596 register uint8_t i, j;
1597 register uint16_t data;
1598
1599 data = data_low;
1600 column_parity = 0;
1601
1602 for(i=0; i<4; i++) {
1603 line_parity = 0;
1604 for(j=0; j<8; j++) {
1605 line_parity ^= data;
1606 column_parity ^= (data & 1) << j;
1607 *forward_ptr++ = data;
1608 data >>= 1;
1609 }
1610 *forward_ptr++ = line_parity;
1611 if(i == 1)
1612 data = data_hi;
1613 }
1614
1615 for(j=0; j<8; j++) {
1616 *forward_ptr++ = column_parity;
1617 column_parity >>= 1;
1618 }
1619 *forward_ptr = 0;
1620
1621 return 45; //return number of emited bits
1622 }
1623
1624 //====================================================================
1625 // Forward Link send function
1626 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1627 // fwd_bit_count set with number of bits to be sent
1628 //====================================================================
1629 void SendForward(uint8_t fwd_bit_count) {
1630
1631 fwd_write_ptr = forwardLink_data;
1632 fwd_bit_sz = fwd_bit_count;
1633
1634 LED_D_ON();
1635
1636 // Set up FPGA, 125kHz
1637 LFSetupFPGAForADC(95, true);
1638
1639 // force 1st mod pulse (start gap must be longer for 4305)
1640 fwd_bit_sz--; //prepare next bit modulation
1641 fwd_write_ptr++;
1642 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1643 WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
1644 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1645 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1646
1647 // now start writting
1648 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1649 if(((*fwd_write_ptr++) & 1) == 1)
1650 WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1651 else {
1652 //These timings work for 4469/4269/4305 (with the 55*8 above)
1653 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1654 WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1655 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1656 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1657 }
1658 }
1659 }
1660
1661 void EM4xLogin(uint32_t Password) {
1662
1663 uint8_t fwd_bit_count;
1664 forward_ptr = forwardLink_data;
1665 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1666 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1667 SendForward(fwd_bit_count);
1668
1669 //Wait for command to complete
1670 WaitMS(20);
1671 }
1672
1673 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1674
1675 uint8_t fwd_bit_count;
1676 uint8_t *dest = BigBuf_get_addr();
1677 uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
1678 uint32_t i = 0;
1679
1680 // Clear destination buffer before sending the command
1681 BigBuf_Clear_ext(false);
1682
1683 //If password mode do login
1684 if (PwdMode == 1) EM4xLogin(Pwd);
1685
1686 forward_ptr = forwardLink_data;
1687 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1688 fwd_bit_count += Prepare_Addr( Address );
1689
1690 SendForward(fwd_bit_count);
1691
1692 // Now do the acquisition
1693 // ICEMAN, change to the one in lfsampling.c
1694 i = 0;
1695 for(;;) {
1696 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1697 AT91C_BASE_SSC->SSC_THR = 0x43;
1698 }
1699 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1700 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1701 ++i;
1702 if (i >= bufsize) break;
1703 }
1704 }
1705
1706 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1707 cmd_send(CMD_ACK,0,0,0,0,0);
1708 LED_D_OFF();
1709 }
1710
1711 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1712
1713 uint8_t fwd_bit_count;
1714
1715 //If password mode do login
1716 if (PwdMode == 1) EM4xLogin(Pwd);
1717
1718 forward_ptr = forwardLink_data;
1719 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1720 fwd_bit_count += Prepare_Addr( Address );
1721 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1722
1723 SendForward(fwd_bit_count);
1724
1725 //Wait for write to complete
1726 WaitMS(20);
1727 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1728 LED_D_OFF();
1729 }
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