git.zerfleddert.de Git - proxmark3-svn/blob - bootrom/bootrom.c

   1 #include <proxmark3.h>
   2
   3 struct common_area common_area __attribute__((section(".commonarea")));
   4 unsigned int start_addr, end_addr, bootrom_unlocked;
   5 extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
   6
   7 static void ConfigClocks(void)
   8 {
   9     // we are using a 16 MHz crystal as the basis for everything
  10     // slow clock runs at 32Khz typical regardless of crystal
  11
  12     // enable system clock and USB clock
  13     AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;
  14
  15         // enable the clock to the following peripherals
  16     AT91C_BASE_PMC->PMC_PCER =
  17                 (1<<AT91C_ID_PIOA)      |
  18                 (1<<AT91C_ID_ADC)       |
  19                 (1<<AT91C_ID_SPI)       |
  20                 (1<<AT91C_ID_SSC)       |
  21                 (1<<AT91C_ID_PWMC)      |
  22                 (1<<AT91C_ID_UDP);
  23
  24         // worst case scenario, with 16Mhz xtal startup delay is 14.5ms
  25         // with a slow clock running at it worst case (max) frequency of 42khz
  26         // max startup delay = (14.5ms*42k)/8 = 76 = 0x4C round up to 0x50
  27
  28         // enable main oscillator and set startup delay
  29     AT91C_BASE_PMC->PMC_MOR =
  30         PMC_MAIN_OSC_ENABLE |
  31         PMC_MAIN_OSC_STARTUP_DELAY(0x50);
  32
  33         // wait for main oscillator to stabilize
  34         while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_STABILIZED) )
  35                 ;
  36
  37     // minimum PLL clock frequency is 80 MHz in range 00 (96 here so okay)
  38     // frequency is crystal * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
  39     AT91C_BASE_PMC->PMC_PLLR =
  40         PMC_PLL_DIVISOR(2) |
  41                 PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
  42                 PMC_PLL_FREQUENCY_RANGE(0) |
  43                 PMC_PLL_MULTIPLIER(12) |
  44                 PMC_PLL_USB_DIVISOR(1);
  45
  46         // wait for PLL to lock
  47         while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_PLL_LOCK) )
  48                 ;
  49
  50         // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
  51         // as per datasheet, this register must be programmed in two operations
  52         // when changing to PLL, program the prescaler first then the source
  53     AT91C_BASE_PMC->PMC_MCKR = PMC_CLK_PRESCALE_DIV_2;
  54
  55         // wait for main clock ready signal
  56         while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) )
  57                 ;
  58
  59         // set the source to PLL
  60     AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | PMC_CLK_PRESCALE_DIV_2;
  61
  62         // wait for main clock ready signal
  63         while ( !(AT91C_BASE_PMC->PMC_SR & PMC_MAIN_OSC_MCK_READY) )
  64                 ;
  65 }
  66
  67 static void Fatal(void)
  68 {
  69     for(;;);
  70 }
  71
  72 void UsbPacketReceived(BYTE *packet, int len)
  73 {
  74     int i, dont_ack=0;
  75     UsbCommand *c = (UsbCommand *)packet;
  76     volatile DWORD *p;
  77
  78     if(len != sizeof(*c)) {
  79         Fatal();
  80     }
  81
  82     switch(c->cmd) {
  83         case CMD_DEVICE_INFO:
  84             dont_ack = 1;
  85             c->cmd = CMD_DEVICE_INFO;
  86             c->arg[0] = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
  87                 DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
  88             if(common_area.flags.osimage_present) c->arg[0] |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
  89             UsbSendPacket(packet, len);
  90             break;
  91
  92         case CMD_SETUP_WRITE:
  93             /* The temporary write buffer of the embedded flash controller is mapped to the
  94              * whole memory region, only the last 8 bits are decoded.
  95              */
  96             p = (volatile DWORD *)&_flash_start;
  97             for(i = 0; i < 12; i++) {
  98                 p[i+c->arg[0]] = c->d.asDwords[i];
  99             }
 100             break;
 101
 102         case CMD_FINISH_WRITE:
 103             p = (volatile DWORD *)&_flash_start;
 104             for(i = 0; i < 4; i++) {
 105                 p[i+60] = c->d.asDwords[i];
 106             }
 107
 108             /* Check that the address that we are supposed to write to is within our allowed region */
 109             if( ((c->arg[0]+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (c->arg[0] < start_addr) ) {
 110                 /* Disallow write */
 111                 dont_ack = 1;
 112                 c->cmd = CMD_NACK;
 113                 UsbSendPacket(packet, len);
 114             } else {
 115                 /* Translate address to flash page and do flash, update here for the 512k part */
 116                 AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
 117                     MC_FLASH_COMMAND_PAGEN((c->arg[0]-(int)&_flash_start)/AT91C_IFLASH_PAGE_SIZE) |
 118                     AT91C_MC_FCMD_START_PROG;
 119             }
 120             while(!(AT91C_BASE_EFC0->EFC_FSR & MC_FLASH_STATUS_READY))
 121                 ;
 122             break;
 123
 124         case CMD_HARDWARE_RESET:
 125             USB_D_PLUS_PULLUP_OFF();
 126             AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
 127             break;
 128
 129         case CMD_START_FLASH:
 130             if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
 131             else bootrom_unlocked = 0;
 132             {
 133                 int prot_start = (int)&_bootrom_start;
 134                 int prot_end = (int)&_bootrom_end;
 135                 int allow_start = (int)&_flash_start;
 136                 int allow_end = (int)&_flash_end;
 137                 int cmd_start = c->arg[0];
 138                 int cmd_end = c->arg[1];
 139
 140                 /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
 141                  * bootrom area. In any case they must be within the flash area.
 142                  */
 143                 if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
 144                     && (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
 145                     start_addr = cmd_start;
 146                     end_addr = cmd_end;
 147                 } else {
 148                     start_addr = end_addr = 0;
 149                     dont_ack = 1;
 150                     c->cmd = CMD_NACK;
 151                     UsbSendPacket(packet, len);
 152                 }
 153             }
 154             break;
 155
 156         default:
 157             Fatal();
 158             break;
 159     }
 160
 161     if(!dont_ack) {
 162         c->cmd = CMD_ACK;
 163         UsbSendPacket(packet, len);
 164     }
 165 }
 166
 167 static void flash_mode(int externally_entered)
 168 {
 169         start_addr = 0;
 170         end_addr = 0;
 171         bootrom_unlocked = 0;
 172
 173         UsbStart();
 174         for(;;) {
 175                 WDT_HIT();
 176
 177                 UsbPoll(TRUE);
 178
 179                 if(!externally_entered && !BUTTON_PRESS()) {
 180                         /* Perform a reset to leave flash mode */
 181                         USB_D_PLUS_PULLUP_OFF();
 182                         LED_B_ON();
 183                         AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
 184                         for(;;);
 185                 }
 186                 if(externally_entered && BUTTON_PRESS()) {
 187                         /* Let the user's button press override the automatic leave */
 188                         externally_entered = 0;
 189                 }
 190         }
 191 }
 192
 193 extern char _osimage_entry;
 194 void BootROM(void)
 195 {
 196     //------------
 197     // First set up all the I/O pins; GPIOs configured directly, other ones
 198     // just need to be assigned to the appropriate peripheral.
 199
 200     // Kill all the pullups, especially the one on USB D+; leave them for
 201     // the unused pins, though.
 202     AT91C_BASE_PIOA->PIO_PPUDR =
 203         GPIO_USB_PU                     |
 204                 GPIO_LED_A                      |
 205                 GPIO_LED_B                      |
 206                 GPIO_LED_C                      |
 207                 GPIO_LED_D                      |
 208                 GPIO_FPGA_DIN           |
 209                 GPIO_FPGA_DOUT          |
 210                 GPIO_FPGA_CCLK          |
 211                 GPIO_FPGA_NINIT         |
 212                 GPIO_FPGA_NPROGRAM      |
 213                 GPIO_FPGA_DONE          |
 214                 GPIO_MUXSEL_HIPKD       |
 215                 GPIO_MUXSEL_HIRAW       |
 216                 GPIO_MUXSEL_LOPKD       |
 217                 GPIO_MUXSEL_LORAW       |
 218                 GPIO_RELAY                      |
 219                 GPIO_NVDD_ON;
 220                 // (and add GPIO_FPGA_ON)
 221         // These pins are outputs
 222     AT91C_BASE_PIOA->PIO_OER =
 223         GPIO_LED_A                      |
 224                 GPIO_LED_B                      |
 225                 GPIO_LED_C                      |
 226                 GPIO_LED_D                      |
 227                 GPIO_RELAY                      |
 228                 GPIO_NVDD_ON;
 229         // PIO controls the following pins
 230     AT91C_BASE_PIOA->PIO_PER =
 231         GPIO_USB_PU                     |
 232                 GPIO_LED_A                      |
 233                 GPIO_LED_B                      |
 234                 GPIO_LED_C                      |
 235                 GPIO_LED_D;
 236
 237     USB_D_PLUS_PULLUP_OFF();
 238     LED_D_OFF();
 239     LED_C_ON();
 240     LED_B_OFF();
 241     LED_A_OFF();
 242
 243     // if 512K FLASH part - TODO make some defines :)
 244     if ((AT91C_BASE_DBGU->DBGU_CIDR | 0xf00) == 0xa00) {
 245             AT91C_BASE_EFC0->EFC_FMR =
 246                 MC_FLASH_MODE_FLASH_WAIT_STATES(1) |
 247                         MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);
 248             AT91C_BASE_EFC1->EFC_FMR =
 249                 MC_FLASH_MODE_FLASH_WAIT_STATES(1) |
 250                         MC_FLASH_MODE_MASTER_CLK_IN_MHZ(0x48);
 251     } else {
 252             AT91C_BASE_EFC0->EFC_FMR =
 253                 MC_FLASH_MODE_FLASH_WAIT_STATES(0) |
 254                         MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
 255     }
 256
 257     // Initialize all system clocks
 258     ConfigClocks();
 259
 260     LED_A_ON();
 261
 262     int common_area_present = 0;
 263     switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
 264     case AT91C_RSTC_RSTTYP_WATCHDOG:
 265     case AT91C_RSTC_RSTTYP_SOFTWARE:
 266     case AT91C_RSTC_RSTTYP_USER:
 267             /* In these cases the common_area in RAM should be ok, retain it if it's there */
 268             if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
 269                     common_area_present = 1;
 270             }
 271             break;
 272     default: /* Otherwise, initialize it from scratch */
 273             break;
 274     }
 275
 276     if(!common_area_present){
 277             /* Common area not ok, initialize it */
 278             int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
 279                     ((char*)&common_area)[i] = 0;
 280             }
 281             common_area.magic = COMMON_AREA_MAGIC;
 282             common_area.version = 1;
 283             common_area.flags.bootrom_present = 1;
 284     }
 285
 286     common_area.flags.bootrom_present = 1;
 287     if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
 288             common_area.command = COMMON_AREA_COMMAND_NONE;
 289             flash_mode(1);
 290     } else if(BUTTON_PRESS()) {
 291             flash_mode(0);
 292     } else {
 293             // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
 294             asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
 295     }
 296 }