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[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23 #include "BigBuf.h"
24 static uint32_t iso14a_timeout;
25 int rsamples = 0;
26 uint8_t trigger = 0;
27 // the block number for the ISO14443-4 PCB
28 static uint8_t iso14_pcb_blocknum = 0;
29
30 //
31 // ISO14443 timing:
32 //
33 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
34 #define REQUEST_GUARD_TIME (7000/16 + 1)
35 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
36 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
37 // bool LastCommandWasRequest = FALSE;
38
39 //
40 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
41 //
42 // When the PM acts as reader and is receiving tag data, it takes
43 // 3 ticks delay in the AD converter
44 // 16 ticks until the modulation detector completes and sets curbit
45 // 8 ticks until bit_to_arm is assigned from curbit
46 // 8*16 ticks for the transfer from FPGA to ARM
47 // 4*16 ticks until we measure the time
48 // - 8*16 ticks because we measure the time of the previous transfer
49 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
50
51 // When the PM acts as a reader and is sending, it takes
52 // 4*16 ticks until we can write data to the sending hold register
53 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
54 // 8 ticks until the first transfer starts
55 // 8 ticks later the FPGA samples the data
56 // 1 tick to assign mod_sig_coil
57 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
58
59 // When the PM acts as tag and is receiving it takes
60 // 2 ticks delay in the RF part (for the first falling edge),
61 // 3 ticks for the A/D conversion,
62 // 8 ticks on average until the start of the SSC transfer,
63 // 8 ticks until the SSC samples the first data
64 // 7*16 ticks to complete the transfer from FPGA to ARM
65 // 8 ticks until the next ssp_clk rising edge
66 // 4*16 ticks until we measure the time
67 // - 8*16 ticks because we measure the time of the previous transfer
68 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
69
70 // The FPGA will report its internal sending delay in
71 uint16_t FpgaSendQueueDelay;
72 // the 5 first bits are the number of bits buffered in mod_sig_buf
73 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
74 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
75
76 // When the PM acts as tag and is sending, it takes
77 // 4*16 ticks until we can write data to the sending hold register
78 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
79 // 8 ticks until the first transfer starts
80 // 8 ticks later the FPGA samples the data
81 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
82 // + 1 tick to assign mod_sig_coil
83 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
84
85 // When the PM acts as sniffer and is receiving tag data, it takes
86 // 3 ticks A/D conversion
87 // 14 ticks to complete the modulation detection
88 // 8 ticks (on average) until the result is stored in to_arm
89 // + the delays in transferring data - which is the same for
90 // sniffing reader and tag data and therefore not relevant
91 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
92
93 // When the PM acts as sniffer and is receiving reader data, it takes
94 // 2 ticks delay in analogue RF receiver (for the falling edge of the
95 // start bit, which marks the start of the communication)
96 // 3 ticks A/D conversion
97 // 8 ticks on average until the data is stored in to_arm.
98 // + the delays in transferring data - which is the same for
99 // sniffing reader and tag data and therefore not relevant
100 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
101
102 //variables used for timing purposes:
103 //these are in ssp_clk cycles:
104 static uint32_t NextTransferTime;
105 static uint32_t LastTimeProxToAirStart;
106 static uint32_t LastProxToAirDuration;
107
108
109
110 // CARD TO READER - manchester
111 // Sequence D: 11110000 modulation with subcarrier during first half
112 // Sequence E: 00001111 modulation with subcarrier during second half
113 // Sequence F: 00000000 no modulation with subcarrier
114 // READER TO CARD - miller
115 // Sequence X: 00001100 drop after half a period
116 // Sequence Y: 00000000 no drop
117 // Sequence Z: 11000000 drop at start
118 #define SEC_D 0xf0
119 #define SEC_E 0x0f
120 #define SEC_F 0x00
121 #define SEC_X 0x0c
122 #define SEC_Y 0x00
123 #define SEC_Z 0xc0
124
125 const uint8_t OddByteParity[256] = {
126 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
142 };
143
144
145 void iso14a_set_trigger(bool enable) {
146 trigger = enable;
147 }
148
149
150 void iso14a_set_timeout(uint32_t timeout) {
151 iso14a_timeout = timeout;
152 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
153 }
154
155
156 void iso14a_set_ATS_timeout(uint8_t *ats) {
157
158 uint8_t tb1;
159 uint8_t fwi;
160 uint32_t fwt;
161
162 if (ats[0] > 1) { // there is a format byte T0
163 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
164 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
165 tb1 = ats[3];
166 } else {
167 tb1 = ats[2];
168 }
169 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
170 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
171
172 iso14a_set_timeout(fwt/(8*16));
173 }
174 }
175 }
176
177
178 //-----------------------------------------------------------------------------
179 // Generate the parity value for a byte sequence
180 //
181 //-----------------------------------------------------------------------------
182 byte_t oddparity (const byte_t bt)
183 {
184 return OddByteParity[bt];
185 }
186
187 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
188 {
189 uint16_t paritybit_cnt = 0;
190 uint16_t paritybyte_cnt = 0;
191 uint8_t parityBits = 0;
192
193 for (uint16_t i = 0; i < iLen; i++) {
194 // Generate the parity bits
195 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
196 if (paritybit_cnt == 7) {
197 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
198 parityBits = 0; // and advance to next Parity Byte
199 paritybyte_cnt++;
200 paritybit_cnt = 0;
201 } else {
202 paritybit_cnt++;
203 }
204 }
205
206 // save remaining parity bits
207 par[paritybyte_cnt] = parityBits;
208
209 }
210
211 void AppendCrc14443a(uint8_t* data, int len)
212 {
213 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
214 }
215
216 void AppendCrc14443b(uint8_t* data, int len)
217 {
218 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
219 }
220
221
222 //=============================================================================
223 // ISO 14443 Type A - Miller decoder
224 //=============================================================================
225 // Basics:
226 // This decoder is used when the PM3 acts as a tag.
227 // The reader will generate "pauses" by temporarily switching of the field.
228 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
229 // The FPGA does a comparison with a threshold and would deliver e.g.:
230 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
231 // The Miller decoder needs to identify the following sequences:
232 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
233 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
234 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
235 // Note 1: the bitstream may start at any time. We therefore need to sync.
236 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
237 //-----------------------------------------------------------------------------
238 static tUart Uart;
239
240 // Lookup-Table to decide if 4 raw bits are a modulation.
241 // We accept the following:
242 // 0001 - a 3 tick wide pause
243 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
244 // 0111 - a 2 tick wide pause shifted left
245 // 1001 - a 2 tick wide pause shifted right
246 const bool Mod_Miller_LUT[] = {
247 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
248 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
249 };
250 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
251 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
252
253 void UartReset()
254 {
255 Uart.state = STATE_UNSYNCD;
256 Uart.bitCount = 0;
257 Uart.len = 0; // number of decoded data bytes
258 Uart.parityLen = 0; // number of decoded parity bytes
259 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
260 Uart.parityBits = 0; // holds 8 parity bits
261 Uart.startTime = 0;
262 Uart.endTime = 0;
263 }
264
265 void UartInit(uint8_t *data, uint8_t *parity)
266 {
267 Uart.output = data;
268 Uart.parity = parity;
269 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
270 UartReset();
271 }
272
273 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
274 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
275 {
276
277 Uart.fourBits = (Uart.fourBits << 8) | bit;
278
279 if (Uart.state == STATE_UNSYNCD) { // not yet synced
280
281 Uart.syncBit = 9999; // not set
282 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
283 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
284 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
285 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
286 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
287 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
288 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
289 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
290 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
291 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
292 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
293 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
294 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
295 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
296
297 if (Uart.syncBit != 9999) { // found a sync bit
298 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
299 Uart.startTime -= Uart.syncBit;
300 Uart.endTime = Uart.startTime;
301 Uart.state = STATE_START_OF_COMMUNICATION;
302 }
303
304 } else {
305
306 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
307 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
308 UartReset();
309 } else { // Modulation in first half = Sequence Z = logic "0"
310 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
311 UartReset();
312 } else {
313 Uart.bitCount++;
314 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
315 Uart.state = STATE_MILLER_Z;
316 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
317 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
318 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
319 Uart.parityBits <<= 1; // make room for the parity bit
320 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
321 Uart.bitCount = 0;
322 Uart.shiftReg = 0;
323 if((Uart.len&0x0007) == 0) { // every 8 data bytes
324 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
325 Uart.parityBits = 0;
326 }
327 }
328 }
329 }
330 } else {
331 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
332 Uart.bitCount++;
333 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
334 Uart.state = STATE_MILLER_X;
335 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
336 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
337 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
338 Uart.parityBits <<= 1; // make room for the new parity bit
339 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
340 Uart.bitCount = 0;
341 Uart.shiftReg = 0;
342 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
343 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
344 Uart.parityBits = 0;
345 }
346 }
347 } else { // no modulation in both halves - Sequence Y
348 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
349 Uart.state = STATE_UNSYNCD;
350 Uart.bitCount--; // last "0" was part of EOC sequence
351 Uart.shiftReg <<= 1; // drop it
352 if(Uart.bitCount > 0) { // if we decoded some bits
353 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
354 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
355 Uart.parityBits <<= 1; // add a (void) parity bit
356 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
357 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
358 return TRUE;
359 } else if (Uart.len & 0x0007) { // there are some parity bits to store
360 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
361 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
362 }
363 if (Uart.len) {
364 return TRUE; // we are finished with decoding the raw data sequence
365 } else {
366 UartReset(); // Nothing received - start over
367 }
368 }
369 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
370 UartReset();
371 } else { // a logic "0"
372 Uart.bitCount++;
373 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
374 Uart.state = STATE_MILLER_Y;
375 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
376 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
377 Uart.parityBits <<= 1; // make room for the parity bit
378 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
379 Uart.bitCount = 0;
380 Uart.shiftReg = 0;
381 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
382 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
383 Uart.parityBits = 0;
384 }
385 }
386 }
387 }
388 }
389
390 }
391
392 return FALSE; // not finished yet, need more data
393 }
394
395
396
397 //=============================================================================
398 // ISO 14443 Type A - Manchester decoder
399 //=============================================================================
400 // Basics:
401 // This decoder is used when the PM3 acts as a reader.
402 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
403 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
404 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
405 // The Manchester decoder needs to identify the following sequences:
406 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
407 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
408 // 8 ticks unmodulated: Sequence F = end of communication
409 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
410 // Note 1: the bitstream may start at any time. We therefore need to sync.
411 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
412 static tDemod Demod;
413
414 // Lookup-Table to decide if 4 raw bits are a modulation.
415 // We accept three or four "1" in any position
416 const bool Mod_Manchester_LUT[] = {
417 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
418 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
419 };
420
421 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
422 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
423
424
425 void DemodReset()
426 {
427 Demod.state = DEMOD_UNSYNCD;
428 Demod.len = 0; // number of decoded data bytes
429 Demod.parityLen = 0;
430 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
431 Demod.parityBits = 0; //
432 Demod.collisionPos = 0; // Position of collision bit
433 Demod.twoBits = 0xffff; // buffer for 2 Bits
434 Demod.highCnt = 0;
435 Demod.startTime = 0;
436 Demod.endTime = 0;
437 }
438
439 void DemodInit(uint8_t *data, uint8_t *parity)
440 {
441 Demod.output = data;
442 Demod.parity = parity;
443 DemodReset();
444 }
445
446 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
447 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
448 {
449
450 Demod.twoBits = (Demod.twoBits << 8) | bit;
451
452 if (Demod.state == DEMOD_UNSYNCD) {
453
454 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
455 if (Demod.twoBits == 0x0000) {
456 Demod.highCnt++;
457 } else {
458 Demod.highCnt = 0;
459 }
460 } else {
461 Demod.syncBit = 0xFFFF; // not set
462 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
463 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
464 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
465 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
466 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
467 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
468 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
469 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
470 if (Demod.syncBit != 0xFFFF) {
471 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
472 Demod.startTime -= Demod.syncBit;
473 Demod.bitCount = offset; // number of decoded data bits
474 Demod.state = DEMOD_MANCHESTER_DATA;
475 }
476 }
477
478 } else {
479
480 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
481 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
482 if (!Demod.collisionPos) {
483 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
484 }
485 } // modulation in first half only - Sequence D = 1
486 Demod.bitCount++;
487 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
488 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
489 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
490 Demod.parityBits <<= 1; // make room for the parity bit
491 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
492 Demod.bitCount = 0;
493 Demod.shiftReg = 0;
494 if((Demod.len&0x0007) == 0) { // every 8 data bytes
495 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
496 Demod.parityBits = 0;
497 }
498 }
499 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
500 } else { // no modulation in first half
501 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
502 Demod.bitCount++;
503 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
504 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
505 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
506 Demod.parityBits <<= 1; // make room for the new parity bit
507 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
508 Demod.bitCount = 0;
509 Demod.shiftReg = 0;
510 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
511 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
512 Demod.parityBits = 0;
513 }
514 }
515 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
516 } else { // no modulation in both halves - End of communication
517 if(Demod.bitCount > 0) { // there are some remaining data bits
518 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
519 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
520 Demod.parityBits <<= 1; // add a (void) parity bit
521 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
522 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
523 return TRUE;
524 } else if (Demod.len & 0x0007) { // there are some parity bits to store
525 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
526 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
527 }
528 if (Demod.len) {
529 return TRUE; // we are finished with decoding the raw data sequence
530 } else { // nothing received. Start over
531 DemodReset();
532 }
533 }
534 }
535
536 }
537
538 return FALSE; // not finished yet, need more data
539 }
540
541 //=============================================================================
542 // Finally, a `sniffer' for ISO 14443 Type A
543 // Both sides of communication!
544 //=============================================================================
545
546 //-----------------------------------------------------------------------------
547 // Record the sequence of commands sent by the reader to the tag, with
548 // triggering so that we start recording at the point that the tag is moved
549 // near the reader.
550 //-----------------------------------------------------------------------------
551 void RAMFUNC SnoopIso14443a(uint8_t param) {
552 // param:
553 // bit 0 - trigger from first card answer
554 // bit 1 - trigger from first reader 7-bit request
555
556 LEDsoff();
557
558 // We won't start recording the frames that we acquire until we trigger;
559 // a good trigger condition to get started is probably when we see a
560 // response from the tag.
561 // triggered == FALSE -- to wait first for card
562 bool triggered = !(param & 0x03);
563
564 // Allocate memory from BigBuf for some buffers
565 // free all previous allocations first
566 BigBuf_free();
567
568 // The command (reader -> tag) that we're receiving.
569 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
570 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
571
572 // The response (tag -> reader) that we're receiving.
573 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
574 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
575
576 // The DMA buffer, used to stream samples from the FPGA
577 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
578
579 // init trace buffer
580 clear_trace();
581 set_tracing(TRUE);
582
583 uint8_t *data = dmaBuf;
584 uint8_t previous_data = 0;
585 int maxDataLen = 0;
586 int dataLen = 0;
587 bool TagIsActive = FALSE;
588 bool ReaderIsActive = FALSE;
589
590 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
591
592 // Set up the demodulator for tag -> reader responses.
593 DemodInit(receivedResponse, receivedResponsePar);
594
595 // Set up the demodulator for the reader -> tag commands
596 UartInit(receivedCmd, receivedCmdPar);
597
598 // Setup and start DMA.
599 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
600
601 // And now we loop, receiving samples.
602 for(uint32_t rsamples = 0; TRUE; ) {
603
604 if(BUTTON_PRESS()) {
605 DbpString("cancelled by button");
606 break;
607 }
608
609 LED_A_ON();
610 WDT_HIT();
611
612 int register readBufDataP = data - dmaBuf;
613 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
614 if (readBufDataP <= dmaBufDataP){
615 dataLen = dmaBufDataP - readBufDataP;
616 } else {
617 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
618 }
619 // test for length of buffer
620 if(dataLen > maxDataLen) {
621 maxDataLen = dataLen;
622 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
623 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
624 break;
625 }
626 }
627 if(dataLen < 1) continue;
628
629 // primary buffer was stopped( <-- we lost data!
630 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
631 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
632 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
633 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
634 }
635 // secondary buffer sets as primary, secondary buffer was stopped
636 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
637 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
638 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
639 }
640
641 LED_A_OFF();
642
643 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
644
645 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
646 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
647 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
648 LED_C_ON();
649
650 // check - if there is a short 7bit request from reader
651 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
652
653 if(triggered) {
654 if (!LogTrace(receivedCmd,
655 Uart.len,
656 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
657 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
658 Uart.parity,
659 TRUE)) break;
660 }
661 /* And ready to receive another command. */
662 UartReset();
663 /* And also reset the demod code, which might have been */
664 /* false-triggered by the commands from the reader. */
665 DemodReset();
666 LED_B_OFF();
667 }
668 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
669 }
670
671 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
672 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
673 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
674 LED_B_ON();
675
676 if (!LogTrace(receivedResponse,
677 Demod.len,
678 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
679 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
680 Demod.parity,
681 FALSE)) break;
682
683 if ((!triggered) && (param & 0x01)) triggered = TRUE;
684
685 // And ready to receive another response.
686 DemodReset();
687 // And reset the Miller decoder including itS (now outdated) input buffer
688 UartInit(receivedCmd, receivedCmdPar);
689
690 LED_C_OFF();
691 }
692 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
693 }
694 }
695
696 previous_data = *data;
697 rsamples++;
698 data++;
699 if(data == dmaBuf + DMA_BUFFER_SIZE) {
700 data = dmaBuf;
701 }
702 } // main cycle
703
704 DbpString("COMMAND FINISHED");
705
706 FpgaDisableSscDma();
707 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
708 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
709 LEDsoff();
710 }
711
712 //-----------------------------------------------------------------------------
713 // Prepare tag messages
714 //-----------------------------------------------------------------------------
715 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
716 {
717 ToSendReset();
718
719 // Correction bit, might be removed when not needed
720 ToSendStuffBit(0);
721 ToSendStuffBit(0);
722 ToSendStuffBit(0);
723 ToSendStuffBit(0);
724 ToSendStuffBit(1); // 1
725 ToSendStuffBit(0);
726 ToSendStuffBit(0);
727 ToSendStuffBit(0);
728
729 // Send startbit
730 ToSend[++ToSendMax] = SEC_D;
731 LastProxToAirDuration = 8 * ToSendMax - 4;
732
733 for(uint16_t i = 0; i < len; i++) {
734 uint8_t b = cmd[i];
735
736 // Data bits
737 for(uint16_t j = 0; j < 8; j++) {
738 if(b & 1) {
739 ToSend[++ToSendMax] = SEC_D;
740 } else {
741 ToSend[++ToSendMax] = SEC_E;
742 }
743 b >>= 1;
744 }
745
746 // Get the parity bit
747 if (parity[i>>3] & (0x80>>(i&0x0007))) {
748 ToSend[++ToSendMax] = SEC_D;
749 LastProxToAirDuration = 8 * ToSendMax - 4;
750 } else {
751 ToSend[++ToSendMax] = SEC_E;
752 LastProxToAirDuration = 8 * ToSendMax;
753 }
754 }
755
756 // Send stopbit
757 ToSend[++ToSendMax] = SEC_F;
758
759 // Convert from last byte pos to length
760 ToSendMax++;
761 }
762
763 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
764 {
765 uint8_t par[MAX_PARITY_SIZE];
766
767 GetParity(cmd, len, par);
768 CodeIso14443aAsTagPar(cmd, len, par);
769 }
770
771
772 static void Code4bitAnswerAsTag(uint8_t cmd)
773 {
774 int i;
775
776 ToSendReset();
777
778 // Correction bit, might be removed when not needed
779 ToSendStuffBit(0);
780 ToSendStuffBit(0);
781 ToSendStuffBit(0);
782 ToSendStuffBit(0);
783 ToSendStuffBit(1); // 1
784 ToSendStuffBit(0);
785 ToSendStuffBit(0);
786 ToSendStuffBit(0);
787
788 // Send startbit
789 ToSend[++ToSendMax] = SEC_D;
790
791 uint8_t b = cmd;
792 for(i = 0; i < 4; i++) {
793 if(b & 1) {
794 ToSend[++ToSendMax] = SEC_D;
795 LastProxToAirDuration = 8 * ToSendMax - 4;
796 } else {
797 ToSend[++ToSendMax] = SEC_E;
798 LastProxToAirDuration = 8 * ToSendMax;
799 }
800 b >>= 1;
801 }
802
803 // Send stopbit
804 ToSend[++ToSendMax] = SEC_F;
805
806 // Convert from last byte pos to length
807 ToSendMax++;
808 }
809
810 //-----------------------------------------------------------------------------
811 // Wait for commands from reader
812 // Stop when button is pressed
813 // Or return TRUE when command is captured
814 //-----------------------------------------------------------------------------
815 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
816 {
817 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
818 // only, since we are receiving, not transmitting).
819 // Signal field is off with the appropriate LED
820 LED_D_OFF();
821 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
822
823 // Now run a `software UART' on the stream of incoming samples.
824 UartInit(received, parity);
825
826 // clear RXRDY:
827 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
828
829 for(;;) {
830 WDT_HIT();
831
832 if(BUTTON_PRESS()) return FALSE;
833
834 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
835 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
836 if(MillerDecoding(b, 0)) {
837 *len = Uart.len;
838 return TRUE;
839 }
840 }
841 }
842 }
843
844 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
845 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
846 int EmSend4bit(uint8_t resp);
847 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
848 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
849 int EmSendCmd(uint8_t *resp, uint16_t respLen);
850 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
851 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
852 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
853
854 static uint8_t* free_buffer_pointer;
855
856 typedef struct {
857 uint8_t* response;
858 size_t response_n;
859 uint8_t* modulation;
860 size_t modulation_n;
861 uint32_t ProxToAirDuration;
862 } tag_response_info_t;
863
864 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
865 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
866 // This will need the following byte array for a modulation sequence
867 // 144 data bits (18 * 8)
868 // 18 parity bits
869 // 2 Start and stop
870 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
871 // 1 just for the case
872 // ----------- +
873 // 166 bytes, since every bit that needs to be send costs us a byte
874 //
875
876
877 // Prepare the tag modulation bits from the message
878 CodeIso14443aAsTag(response_info->response,response_info->response_n);
879
880 // Make sure we do not exceed the free buffer space
881 if (ToSendMax > max_buffer_size) {
882 Dbprintf("Out of memory, when modulating bits for tag answer:");
883 Dbhexdump(response_info->response_n,response_info->response,false);
884 return false;
885 }
886
887 // Copy the byte array, used for this modulation to the buffer position
888 memcpy(response_info->modulation,ToSend,ToSendMax);
889
890 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
891 response_info->modulation_n = ToSendMax;
892 response_info->ProxToAirDuration = LastProxToAirDuration;
893
894 return true;
895 }
896
897
898 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
899 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
900 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
901 // -> need 273 bytes buffer
902 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
903
904 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
905 // Retrieve and store the current buffer index
906 response_info->modulation = free_buffer_pointer;
907
908 // Determine the maximum size we can use from our buffer
909 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
910
911 // Forward the prepare tag modulation function to the inner function
912 if (prepare_tag_modulation(response_info, max_buffer_size)) {
913 // Update the free buffer offset
914 free_buffer_pointer += ToSendMax;
915 return true;
916 } else {
917 return false;
918 }
919 }
920
921 //-----------------------------------------------------------------------------
922 // Main loop of simulated tag: receive commands from reader, decide what
923 // response to send, and send it.
924 //-----------------------------------------------------------------------------
925 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
926 {
927 uint8_t sak;
928
929 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
930 uint8_t response1[2];
931
932 switch (tagType) {
933 case 1: { // MIFARE Classic
934 // Says: I am Mifare 1k - original line
935 response1[0] = 0x04;
936 response1[1] = 0x00;
937 sak = 0x08;
938 } break;
939 case 2: { // MIFARE Ultralight
940 // Says: I am a stupid memory tag, no crypto
941 response1[0] = 0x04;
942 response1[1] = 0x00;
943 sak = 0x00;
944 } break;
945 case 3: { // MIFARE DESFire
946 // Says: I am a DESFire tag, ph33r me
947 response1[0] = 0x04;
948 response1[1] = 0x03;
949 sak = 0x20;
950 } break;
951 case 4: { // ISO/IEC 14443-4
952 // Says: I am a javacard (JCOP)
953 response1[0] = 0x04;
954 response1[1] = 0x00;
955 sak = 0x28;
956 } break;
957 case 5: { // MIFARE TNP3XXX
958 // Says: I am a toy
959 response1[0] = 0x01;
960 response1[1] = 0x0f;
961 sak = 0x01;
962 } break;
963 default: {
964 Dbprintf("Error: unkown tagtype (%d)",tagType);
965 return;
966 } break;
967 }
968
969 // The second response contains the (mandatory) first 24 bits of the UID
970 uint8_t response2[5] = {0x00};
971
972 // Check if the uid uses the (optional) part
973 uint8_t response2a[5] = {0x00};
974
975 if (uid_2nd) {
976 response2[0] = 0x88;
977 num_to_bytes(uid_1st,3,response2+1);
978 num_to_bytes(uid_2nd,4,response2a);
979 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
980
981 // Configure the ATQA and SAK accordingly
982 response1[0] |= 0x40;
983 sak |= 0x04;
984 } else {
985 num_to_bytes(uid_1st,4,response2);
986 // Configure the ATQA and SAK accordingly
987 response1[0] &= 0xBF;
988 sak &= 0xFB;
989 }
990
991 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
992 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
993
994 // Prepare the mandatory SAK (for 4 and 7 byte UID)
995 uint8_t response3[3] = {0x00};
996 response3[0] = sak;
997 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
998
999 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1000 uint8_t response3a[3] = {0x00};
1001 response3a[0] = sak & 0xFB;
1002 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1003
1004 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1005 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1006 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1007 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1008 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1009 // TC(1) = 0x02: CID supported, NAD not supported
1010 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1011
1012 #define TAG_RESPONSE_COUNT 7
1013 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1014 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1015 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1016 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1017 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1018 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1019 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1020 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1021 };
1022
1023 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1024 // Such a response is less time critical, so we can prepare them on the fly
1025 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1026 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1027 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1028 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1029 tag_response_info_t dynamic_response_info = {
1030 .response = dynamic_response_buffer,
1031 .response_n = 0,
1032 .modulation = dynamic_modulation_buffer,
1033 .modulation_n = 0
1034 };
1035
1036 BigBuf_free_keep_EM();
1037
1038 // allocate buffers:
1039 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1040 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1041 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1042
1043 // clear trace
1044 clear_trace();
1045 set_tracing(TRUE);
1046
1047 // Prepare the responses of the anticollision phase
1048 // there will be not enough time to do this at the moment the reader sends it REQA
1049 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1050 prepare_allocated_tag_modulation(&responses[i]);
1051 }
1052
1053 int len = 0;
1054
1055 // To control where we are in the protocol
1056 int order = 0;
1057 int lastorder;
1058
1059 // Just to allow some checks
1060 int happened = 0;
1061 int happened2 = 0;
1062 int cmdsRecvd = 0;
1063
1064 // We need to listen to the high-frequency, peak-detected path.
1065 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1066
1067 cmdsRecvd = 0;
1068 tag_response_info_t* p_response;
1069
1070 LED_A_ON();
1071 for(;;) {
1072 // Clean receive command buffer
1073
1074 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1075 DbpString("Button press");
1076 break;
1077 }
1078
1079 p_response = NULL;
1080
1081 // Okay, look at the command now.
1082 lastorder = order;
1083 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1084 p_response = &responses[0]; order = 1;
1085 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1086 p_response = &responses[0]; order = 6;
1087 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1088 p_response = &responses[1]; order = 2;
1089 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1090 p_response = &responses[2]; order = 20;
1091 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1092 p_response = &responses[3]; order = 3;
1093 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1094 p_response = &responses[4]; order = 30;
1095 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1096 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1097 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1098 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1099 p_response = NULL;
1100 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1101
1102 if (tracing) {
1103 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1104 }
1105 p_response = NULL;
1106 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1107 p_response = &responses[5]; order = 7;
1108 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1109 if (tagType == 1 || tagType == 2) { // RATS not supported
1110 EmSend4bit(CARD_NACK_NA);
1111 p_response = NULL;
1112 } else {
1113 p_response = &responses[6]; order = 70;
1114 }
1115 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1116 if (tracing) {
1117 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1118 }
1119 uint32_t nr = bytes_to_num(receivedCmd,4);
1120 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1121 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1122 } else {
1123 // Check for ISO 14443A-4 compliant commands, look at left nibble
1124 switch (receivedCmd[0]) {
1125
1126 case 0x0B:
1127 case 0x0A: { // IBlock (command)
1128 dynamic_response_info.response[0] = receivedCmd[0];
1129 dynamic_response_info.response[1] = 0x00;
1130 dynamic_response_info.response[2] = 0x90;
1131 dynamic_response_info.response[3] = 0x00;
1132 dynamic_response_info.response_n = 4;
1133 } break;
1134
1135 case 0x1A:
1136 case 0x1B: { // Chaining command
1137 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1138 dynamic_response_info.response_n = 2;
1139 } break;
1140
1141 case 0xaa:
1142 case 0xbb: {
1143 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1144 dynamic_response_info.response_n = 2;
1145 } break;
1146
1147 case 0xBA: { //
1148 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1149 dynamic_response_info.response_n = 2;
1150 } break;
1151
1152 case 0xCA:
1153 case 0xC2: { // Readers sends deselect command
1154 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1155 dynamic_response_info.response_n = 2;
1156 } break;
1157
1158 default: {
1159 // Never seen this command before
1160 if (tracing) {
1161 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1162 }
1163 Dbprintf("Received unknown command (len=%d):",len);
1164 Dbhexdump(len,receivedCmd,false);
1165 // Do not respond
1166 dynamic_response_info.response_n = 0;
1167 } break;
1168 }
1169
1170 if (dynamic_response_info.response_n > 0) {
1171 // Copy the CID from the reader query
1172 dynamic_response_info.response[1] = receivedCmd[1];
1173
1174 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1175 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1176 dynamic_response_info.response_n += 2;
1177
1178 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1179 Dbprintf("Error preparing tag response");
1180 if (tracing) {
1181 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1182 }
1183 break;
1184 }
1185 p_response = &dynamic_response_info;
1186 }
1187 }
1188
1189 // Count number of wakeups received after a halt
1190 if(order == 6 && lastorder == 5) { happened++; }
1191
1192 // Count number of other messages after a halt
1193 if(order != 6 && lastorder == 5) { happened2++; }
1194
1195 if(cmdsRecvd > 999) {
1196 DbpString("1000 commands later...");
1197 break;
1198 }
1199 cmdsRecvd++;
1200
1201 if (p_response != NULL) {
1202 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1203 // do the tracing for the previous reader request and this tag answer:
1204 uint8_t par[MAX_PARITY_SIZE];
1205 GetParity(p_response->response, p_response->response_n, par);
1206
1207 EmLogTrace(Uart.output,
1208 Uart.len,
1209 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1210 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1211 Uart.parity,
1212 p_response->response,
1213 p_response->response_n,
1214 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1215 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1216 par);
1217 }
1218
1219 if (!tracing) {
1220 Dbprintf("Trace Full. Simulation stopped.");
1221 break;
1222 }
1223 }
1224
1225 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1226 LED_A_OFF();
1227 BigBuf_free_keep_EM();
1228 }
1229
1230
1231 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1232 // of bits specified in the delay parameter.
1233 void PrepareDelayedTransfer(uint16_t delay)
1234 {
1235 uint8_t bitmask = 0;
1236 uint8_t bits_to_shift = 0;
1237 uint8_t bits_shifted = 0;
1238
1239 delay &= 0x07;
1240 if (delay) {
1241 for (uint16_t i = 0; i < delay; i++) {
1242 bitmask |= (0x01 << i);
1243 }
1244 ToSend[ToSendMax++] = 0x00;
1245 for (uint16_t i = 0; i < ToSendMax; i++) {
1246 bits_to_shift = ToSend[i] & bitmask;
1247 ToSend[i] = ToSend[i] >> delay;
1248 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1249 bits_shifted = bits_to_shift;
1250 }
1251 }
1252 }
1253
1254
1255 //-------------------------------------------------------------------------------------
1256 // Transmit the command (to the tag) that was placed in ToSend[].
1257 // Parameter timing:
1258 // if NULL: transfer at next possible time, taking into account
1259 // request guard time and frame delay time
1260 // if == 0: transfer immediately and return time of transfer
1261 // if != 0: delay transfer until time specified
1262 //-------------------------------------------------------------------------------------
1263 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1264 {
1265
1266 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1267
1268 uint32_t ThisTransferTime = 0;
1269
1270 if (timing) {
1271 if(*timing == 0) { // Measure time
1272 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1273 } else {
1274 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1275 }
1276 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1277 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1278 LastTimeProxToAirStart = *timing;
1279 } else {
1280 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1281 while(GetCountSspClk() < ThisTransferTime);
1282 LastTimeProxToAirStart = ThisTransferTime;
1283 }
1284
1285 // clear TXRDY
1286 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1287
1288 uint16_t c = 0;
1289 for(;;) {
1290 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1291 AT91C_BASE_SSC->SSC_THR = cmd[c];
1292 c++;
1293 if(c >= len) {
1294 break;
1295 }
1296 }
1297 }
1298
1299 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1300 }
1301
1302
1303 //-----------------------------------------------------------------------------
1304 // Prepare reader command (in bits, support short frames) to send to FPGA
1305 //-----------------------------------------------------------------------------
1306 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1307 {
1308 int i, j;
1309 int last;
1310 uint8_t b;
1311
1312 ToSendReset();
1313
1314 // Start of Communication (Seq. Z)
1315 ToSend[++ToSendMax] = SEC_Z;
1316 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1317 last = 0;
1318
1319 size_t bytecount = nbytes(bits);
1320 // Generate send structure for the data bits
1321 for (i = 0; i < bytecount; i++) {
1322 // Get the current byte to send
1323 b = cmd[i];
1324 size_t bitsleft = MIN((bits-(i*8)),8);
1325
1326 for (j = 0; j < bitsleft; j++) {
1327 if (b & 1) {
1328 // Sequence X
1329 ToSend[++ToSendMax] = SEC_X;
1330 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1331 last = 1;
1332 } else {
1333 if (last == 0) {
1334 // Sequence Z
1335 ToSend[++ToSendMax] = SEC_Z;
1336 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1337 } else {
1338 // Sequence Y
1339 ToSend[++ToSendMax] = SEC_Y;
1340 last = 0;
1341 }
1342 }
1343 b >>= 1;
1344 }
1345
1346 // Only transmit parity bit if we transmitted a complete byte
1347 if (j == 8 && parity != NULL) {
1348 // Get the parity bit
1349 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1350 // Sequence X
1351 ToSend[++ToSendMax] = SEC_X;
1352 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1353 last = 1;
1354 } else {
1355 if (last == 0) {
1356 // Sequence Z
1357 ToSend[++ToSendMax] = SEC_Z;
1358 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1359 } else {
1360 // Sequence Y
1361 ToSend[++ToSendMax] = SEC_Y;
1362 last = 0;
1363 }
1364 }
1365 }
1366 }
1367
1368 // End of Communication: Logic 0 followed by Sequence Y
1369 if (last == 0) {
1370 // Sequence Z
1371 ToSend[++ToSendMax] = SEC_Z;
1372 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1373 } else {
1374 // Sequence Y
1375 ToSend[++ToSendMax] = SEC_Y;
1376 last = 0;
1377 }
1378 ToSend[++ToSendMax] = SEC_Y;
1379
1380 // Convert to length of command:
1381 ToSendMax++;
1382 }
1383
1384 //-----------------------------------------------------------------------------
1385 // Prepare reader command to send to FPGA
1386 //-----------------------------------------------------------------------------
1387 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1388 {
1389 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1390 }
1391
1392
1393 //-----------------------------------------------------------------------------
1394 // Wait for commands from reader
1395 // Stop when button is pressed (return 1) or field was gone (return 2)
1396 // Or return 0 when command is captured
1397 //-----------------------------------------------------------------------------
1398 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1399 {
1400 *len = 0;
1401
1402 uint32_t timer = 0, vtime = 0;
1403 int analogCnt = 0;
1404 int analogAVG = 0;
1405
1406 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1407 // only, since we are receiving, not transmitting).
1408 // Signal field is off with the appropriate LED
1409 LED_D_OFF();
1410 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1411
1412 // Set ADC to read field strength
1413 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1414 AT91C_BASE_ADC->ADC_MR =
1415 ADC_MODE_PRESCALE(63) |
1416 ADC_MODE_STARTUP_TIME(1) |
1417 ADC_MODE_SAMPLE_HOLD_TIME(15);
1418 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1419 // start ADC
1420 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1421
1422 // Now run a 'software UART' on the stream of incoming samples.
1423 UartInit(received, parity);
1424
1425 // Clear RXRDY:
1426 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1427
1428 for(;;) {
1429 WDT_HIT();
1430
1431 if (BUTTON_PRESS()) return 1;
1432
1433 // test if the field exists
1434 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1435 analogCnt++;
1436 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1437 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1438 if (analogCnt >= 32) {
1439 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1440 vtime = GetTickCount();
1441 if (!timer) timer = vtime;
1442 // 50ms no field --> card to idle state
1443 if (vtime - timer > 50) return 2;
1444 } else
1445 if (timer) timer = 0;
1446 analogCnt = 0;
1447 analogAVG = 0;
1448 }
1449 }
1450
1451 // receive and test the miller decoding
1452 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1453 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1454 if(MillerDecoding(b, 0)) {
1455 *len = Uart.len;
1456 return 0;
1457 }
1458 }
1459
1460 }
1461 }
1462
1463
1464 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1465 {
1466 uint8_t b;
1467 uint16_t i = 0;
1468 uint32_t ThisTransferTime;
1469
1470 // Modulate Manchester
1471 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1472
1473 // include correction bit if necessary
1474 if (Uart.parityBits & 0x01) {
1475 correctionNeeded = TRUE;
1476 }
1477 if(correctionNeeded) {
1478 // 1236, so correction bit needed
1479 i = 0;
1480 } else {
1481 i = 1;
1482 }
1483
1484 // clear receiving shift register and holding register
1485 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1486 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1487 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1488 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1489
1490 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1491 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1492 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1493 if (AT91C_BASE_SSC->SSC_RHR) break;
1494 }
1495
1496 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1497
1498 // Clear TXRDY:
1499 AT91C_BASE_SSC->SSC_THR = SEC_F;
1500
1501 // send cycle
1502 for(; i < respLen; ) {
1503 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1504 AT91C_BASE_SSC->SSC_THR = resp[i++];
1505 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1506 }
1507
1508 if(BUTTON_PRESS()) {
1509 break;
1510 }
1511 }
1512
1513 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1514 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1515 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1516 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1517 AT91C_BASE_SSC->SSC_THR = SEC_F;
1518 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1519 i++;
1520 }
1521 }
1522
1523 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1524
1525 return 0;
1526 }
1527
1528 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1529 Code4bitAnswerAsTag(resp);
1530 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1531 // do the tracing for the previous reader request and this tag answer:
1532 uint8_t par[1];
1533 GetParity(&resp, 1, par);
1534 EmLogTrace(Uart.output,
1535 Uart.len,
1536 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1537 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1538 Uart.parity,
1539 &resp,
1540 1,
1541 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1542 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1543 par);
1544 return res;
1545 }
1546
1547 int EmSend4bit(uint8_t resp){
1548 return EmSend4bitEx(resp, false);
1549 }
1550
1551 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1552 CodeIso14443aAsTagPar(resp, respLen, par);
1553 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1554 // do the tracing for the previous reader request and this tag answer:
1555 EmLogTrace(Uart.output,
1556 Uart.len,
1557 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1558 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1559 Uart.parity,
1560 resp,
1561 respLen,
1562 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1563 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1564 par);
1565 return res;
1566 }
1567
1568 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1569 uint8_t par[MAX_PARITY_SIZE];
1570 GetParity(resp, respLen, par);
1571 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1572 }
1573
1574 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1575 uint8_t par[MAX_PARITY_SIZE];
1576 GetParity(resp, respLen, par);
1577 return EmSendCmdExPar(resp, respLen, false, par);
1578 }
1579
1580 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1581 return EmSendCmdExPar(resp, respLen, false, par);
1582 }
1583
1584 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1585 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1586 {
1587 if (tracing) {
1588 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1589 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1590 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1591 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1592 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1593 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1594 reader_EndTime = tag_StartTime - exact_fdt;
1595 reader_StartTime = reader_EndTime - reader_modlen;
1596 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1597 return FALSE;
1598 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1599 } else {
1600 return TRUE;
1601 }
1602 }
1603
1604 //-----------------------------------------------------------------------------
1605 // Wait a certain time for tag response
1606 // If a response is captured return TRUE
1607 // If it takes too long return FALSE
1608 //-----------------------------------------------------------------------------
1609 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1610 {
1611 uint32_t c;
1612
1613 // Set FPGA mode to "reader listen mode", no modulation (listen
1614 // only, since we are receiving, not transmitting).
1615 // Signal field is on with the appropriate LED
1616 LED_D_ON();
1617 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1618
1619 // Now get the answer from the card
1620 DemodInit(receivedResponse, receivedResponsePar);
1621
1622 // clear RXRDY:
1623 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1624
1625 c = 0;
1626 for(;;) {
1627 WDT_HIT();
1628
1629 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1630 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1631 if(ManchesterDecoding(b, offset, 0)) {
1632 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1633 return TRUE;
1634 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1635 return FALSE;
1636 }
1637 }
1638 }
1639 }
1640
1641
1642 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1643 {
1644 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1645
1646 // Send command to tag
1647 TransmitFor14443a(ToSend, ToSendMax, timing);
1648 if(trigger)
1649 LED_A_ON();
1650
1651 // Log reader command in trace buffer
1652 if (tracing) {
1653 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1654 }
1655 }
1656
1657
1658 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1659 {
1660 ReaderTransmitBitsPar(frame, len*8, par, timing);
1661 }
1662
1663
1664 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1665 {
1666 // Generate parity and redirect
1667 uint8_t par[MAX_PARITY_SIZE];
1668 GetParity(frame, len/8, par);
1669 ReaderTransmitBitsPar(frame, len, par, timing);
1670 }
1671
1672
1673 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1674 {
1675 // Generate parity and redirect
1676 uint8_t par[MAX_PARITY_SIZE];
1677 GetParity(frame, len, par);
1678 ReaderTransmitBitsPar(frame, len*8, par, timing);
1679 }
1680
1681 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1682 {
1683 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1684 if (tracing) {
1685 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1686 }
1687 return Demod.len;
1688 }
1689
1690 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1691 {
1692 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1693 if (tracing) {
1694 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1695 }
1696 return Demod.len;
1697 }
1698
1699 /* performs iso14443a anticollision procedure
1700 * fills the uid pointer unless NULL
1701 * fills resp_data unless NULL */
1702 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1703 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1704 uint8_t sel_all[] = { 0x93,0x20 };
1705 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1706 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1707 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1708 uint8_t resp_par[MAX_PARITY_SIZE];
1709 byte_t uid_resp[4];
1710 size_t uid_resp_len;
1711
1712 uint8_t sak = 0x04; // cascade uid
1713 int cascade_level = 0;
1714 int len;
1715
1716 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1717 ReaderTransmitBitsPar(wupa,7,0, NULL);
1718
1719 // Receive the ATQA
1720 if(!ReaderReceive(resp, resp_par)) return 0;
1721
1722 if(p_hi14a_card) {
1723 memcpy(p_hi14a_card->atqa, resp, 2);
1724 p_hi14a_card->uidlen = 0;
1725 memset(p_hi14a_card->uid,0,10);
1726 }
1727
1728 // clear uid
1729 if (uid_ptr) {
1730 memset(uid_ptr,0,10);
1731 }
1732
1733 // check for proprietary anticollision:
1734 if ((resp[0] & 0x1F) == 0) {
1735 return 3;
1736 }
1737
1738 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1739 // which case we need to make a cascade 2 request and select - this is a long UID
1740 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1741 for(; sak & 0x04; cascade_level++) {
1742 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1743 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1744
1745 // SELECT_ALL
1746 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1747 if (!ReaderReceive(resp, resp_par)) return 0;
1748
1749 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1750 memset(uid_resp, 0, 4);
1751 uint16_t uid_resp_bits = 0;
1752 uint16_t collision_answer_offset = 0;
1753 // anti-collision-loop:
1754 while (Demod.collisionPos) {
1755 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1756 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1757 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1758 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1759 }
1760 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1761 uid_resp_bits++;
1762 // construct anticollosion command:
1763 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1764 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1765 sel_uid[2+i] = uid_resp[i];
1766 }
1767 collision_answer_offset = uid_resp_bits%8;
1768 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1769 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1770 }
1771 // finally, add the last bits and BCC of the UID
1772 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1773 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1774 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1775 }
1776
1777 } else { // no collision, use the response to SELECT_ALL as current uid
1778 memcpy(uid_resp, resp, 4);
1779 }
1780 uid_resp_len = 4;
1781
1782 // calculate crypto UID. Always use last 4 Bytes.
1783 if(cuid_ptr) {
1784 *cuid_ptr = bytes_to_num(uid_resp, 4);
1785 }
1786
1787 // Construct SELECT UID command
1788 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1789 memcpy(sel_uid+2, uid_resp, 4); // the UID
1790 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1791 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1792 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1793
1794 // Receive the SAK
1795 if (!ReaderReceive(resp, resp_par)) return 0;
1796 sak = resp[0];
1797
1798 // Test if more parts of the uid are coming
1799 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1800 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1801 // http://www.nxp.com/documents/application_note/AN10927.pdf
1802 uid_resp[0] = uid_resp[1];
1803 uid_resp[1] = uid_resp[2];
1804 uid_resp[2] = uid_resp[3];
1805
1806 uid_resp_len = 3;
1807 }
1808
1809 if(uid_ptr) {
1810 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1811 }
1812
1813 if(p_hi14a_card) {
1814 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1815 p_hi14a_card->uidlen += uid_resp_len;
1816 }
1817 }
1818
1819 if(p_hi14a_card) {
1820 p_hi14a_card->sak = sak;
1821 p_hi14a_card->ats_len = 0;
1822 }
1823
1824 // non iso14443a compliant tag
1825 if( (sak & 0x20) == 0) return 2;
1826
1827 // Request for answer to select
1828 AppendCrc14443a(rats, 2);
1829 ReaderTransmit(rats, sizeof(rats), NULL);
1830
1831 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1832
1833
1834 if(p_hi14a_card) {
1835 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1836 p_hi14a_card->ats_len = len;
1837 }
1838
1839 // reset the PCB block number
1840 iso14_pcb_blocknum = 0;
1841
1842 // set default timeout based on ATS
1843 iso14a_set_ATS_timeout(resp);
1844
1845 return 1;
1846 }
1847
1848 void iso14443a_setup(uint8_t fpga_minor_mode) {
1849 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1850 // Set up the synchronous serial port
1851 FpgaSetupSsc();
1852 // connect Demodulated Signal to ADC:
1853 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1854
1855 // Signal field is on with the appropriate LED
1856 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1857 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1858 LED_D_ON();
1859 } else {
1860 LED_D_OFF();
1861 }
1862 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1863
1864 // Start the timer
1865 StartCountSspClk();
1866
1867 DemodReset();
1868 UartReset();
1869 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1870 iso14a_set_timeout(1050); // 10ms default
1871 }
1872
1873 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1874 uint8_t parity[MAX_PARITY_SIZE];
1875 uint8_t real_cmd[cmd_len+4];
1876 real_cmd[0] = 0x0a; //I-Block
1877 // put block number into the PCB
1878 real_cmd[0] |= iso14_pcb_blocknum;
1879 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1880 memcpy(real_cmd+2, cmd, cmd_len);
1881 AppendCrc14443a(real_cmd,cmd_len+2);
1882
1883 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1884 size_t len = ReaderReceive(data, parity);
1885 uint8_t *data_bytes = (uint8_t *) data;
1886 if (!len)
1887 return 0; //DATA LINK ERROR
1888 // if we received an I- or R(ACK)-Block with a block number equal to the
1889 // current block number, toggle the current block number
1890 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1891 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1892 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1893 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1894 {
1895 iso14_pcb_blocknum ^= 1;
1896 }
1897
1898 return len;
1899 }
1900
1901 //-----------------------------------------------------------------------------
1902 // Read an ISO 14443a tag. Send out commands and store answers.
1903 //
1904 //-----------------------------------------------------------------------------
1905 void ReaderIso14443a(UsbCommand *c)
1906 {
1907 iso14a_command_t param = c->arg[0];
1908 uint8_t *cmd = c->d.asBytes;
1909 size_t len = c->arg[1] & 0xffff;
1910 size_t lenbits = c->arg[1] >> 16;
1911 uint32_t timeout = c->arg[2];
1912 uint32_t arg0 = 0;
1913 byte_t buf[USB_CMD_DATA_SIZE];
1914 uint8_t par[MAX_PARITY_SIZE];
1915
1916 if(param & ISO14A_CONNECT) {
1917 clear_trace();
1918 }
1919
1920 set_tracing(TRUE);
1921
1922 if(param & ISO14A_REQUEST_TRIGGER) {
1923 iso14a_set_trigger(TRUE);
1924 }
1925
1926 if(param & ISO14A_CONNECT) {
1927 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1928 if(!(param & ISO14A_NO_SELECT)) {
1929 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1930 arg0 = iso14443a_select_card(NULL,card,NULL);
1931 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1932 }
1933 }
1934
1935 if(param & ISO14A_SET_TIMEOUT) {
1936 iso14a_set_timeout(timeout);
1937 }
1938
1939 if(param & ISO14A_APDU) {
1940 arg0 = iso14_apdu(cmd, len, buf);
1941 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1942 }
1943
1944 if(param & ISO14A_RAW) {
1945 if(param & ISO14A_APPEND_CRC) {
1946 if(param & ISO14A_TOPAZMODE) {
1947 AppendCrc14443b(cmd,len);
1948 } else {
1949 AppendCrc14443a(cmd,len);
1950 }
1951 len += 2;
1952 if (lenbits) lenbits += 16;
1953 }
1954 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
1955 if(param & ISO14A_TOPAZMODE) {
1956 int bits_to_send = lenbits;
1957 uint16_t i = 0;
1958 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
1959 bits_to_send -= 7;
1960 while (bits_to_send > 0) {
1961 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
1962 bits_to_send -= 8;
1963 }
1964 } else {
1965 GetParity(cmd, lenbits/8, par);
1966 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
1967 }
1968 } else { // want to send complete bytes only
1969 if(param & ISO14A_TOPAZMODE) {
1970 uint16_t i = 0;
1971 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
1972 while (i < len) {
1973 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
1974 }
1975 } else {
1976 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
1977 }
1978 }
1979 arg0 = ReaderReceive(buf, par);
1980 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1981 }
1982
1983 if(param & ISO14A_REQUEST_TRIGGER) {
1984 iso14a_set_trigger(FALSE);
1985 }
1986
1987 if(param & ISO14A_NO_DISCONNECT) {
1988 return;
1989 }
1990
1991 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1992 LEDsoff();
1993 }
1994
1995
1996 // Determine the distance between two nonces.
1997 // Assume that the difference is small, but we don't know which is first.
1998 // Therefore try in alternating directions.
1999 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2000
2001 uint16_t i;
2002 uint32_t nttmp1, nttmp2;
2003
2004 if (nt1 == nt2) return 0;
2005
2006 nttmp1 = nt1;
2007 nttmp2 = nt2;
2008
2009 for (i = 1; i < 32768; i++) {
2010 nttmp1 = prng_successor(nttmp1, 1);
2011 if (nttmp1 == nt2) return i;
2012 nttmp2 = prng_successor(nttmp2, 1);
2013 if (nttmp2 == nt1) return -i;
2014 }
2015
2016 return(-99999); // either nt1 or nt2 are invalid nonces
2017 }
2018
2019
2020 //-----------------------------------------------------------------------------
2021 // Recover several bits of the cypher stream. This implements (first stages of)
2022 // the algorithm described in "The Dark Side of Security by Obscurity and
2023 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2024 // (article by Nicolas T. Courtois, 2009)
2025 //-----------------------------------------------------------------------------
2026 void ReaderMifare(bool first_try)
2027 {
2028 // Mifare AUTH
2029 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2030 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2031 static uint8_t mf_nr_ar3;
2032
2033 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2034 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
2035
2036 // free eventually allocated BigBuf memory. We want all for tracing.
2037 BigBuf_free();
2038
2039 clear_trace();
2040 set_tracing(TRUE);
2041
2042 byte_t nt_diff = 0;
2043 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2044 static byte_t par_low = 0;
2045 bool led_on = TRUE;
2046 uint8_t uid[10] ={0};
2047 uint32_t cuid;
2048
2049 uint32_t nt = 0;
2050 uint32_t previous_nt = 0;
2051 static uint32_t nt_attacked = 0;
2052 byte_t par_list[8] = {0x00};
2053 byte_t ks_list[8] = {0x00};
2054
2055 static uint32_t sync_time;
2056 static uint32_t sync_cycles;
2057 int catch_up_cycles = 0;
2058 int last_catch_up = 0;
2059 uint16_t consecutive_resyncs = 0;
2060 int isOK = 0;
2061
2062 if (first_try) {
2063 mf_nr_ar3 = 0;
2064 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2065 sync_time = GetCountSspClk() & 0xfffffff8;
2066 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2067 nt_attacked = 0;
2068 nt = 0;
2069 par[0] = 0;
2070 }
2071 else {
2072 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2073 mf_nr_ar3++;
2074 mf_nr_ar[3] = mf_nr_ar3;
2075 par[0] = par_low;
2076 }
2077
2078 LED_A_ON();
2079 LED_B_OFF();
2080 LED_C_OFF();
2081
2082
2083 for(uint16_t i = 0; TRUE; i++) {
2084
2085 WDT_HIT();
2086
2087 // Test if the action was cancelled
2088 if(BUTTON_PRESS()) {
2089 break;
2090 }
2091
2092 LED_C_ON();
2093
2094 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2095 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2096 continue;
2097 }
2098
2099 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2100 catch_up_cycles = 0;
2101
2102 // if we missed the sync time already, advance to the next nonce repeat
2103 while(GetCountSspClk() > sync_time) {
2104 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2105 }
2106
2107 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2108 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2109
2110 // Receive the (4 Byte) "random" nonce
2111 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2112 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2113 continue;
2114 }
2115
2116 previous_nt = nt;
2117 nt = bytes_to_num(receivedAnswer, 4);
2118
2119 // Transmit reader nonce with fake par
2120 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2121
2122 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2123 int nt_distance = dist_nt(previous_nt, nt);
2124 if (nt_distance == 0) {
2125 nt_attacked = nt;
2126 }
2127 else {
2128 if (nt_distance == -99999) { // invalid nonce received, try again
2129 continue;
2130 }
2131 sync_cycles = (sync_cycles - nt_distance);
2132 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2133 continue;
2134 }
2135 }
2136
2137 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2138 catch_up_cycles = -dist_nt(nt_attacked, nt);
2139 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2140 catch_up_cycles = 0;
2141 continue;
2142 }
2143 if (catch_up_cycles == last_catch_up) {
2144 consecutive_resyncs++;
2145 }
2146 else {
2147 last_catch_up = catch_up_cycles;
2148 consecutive_resyncs = 0;
2149 }
2150 if (consecutive_resyncs < 3) {
2151 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2152 }
2153 else {
2154 sync_cycles = sync_cycles + catch_up_cycles;
2155 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2156 }
2157 continue;
2158 }
2159
2160 consecutive_resyncs = 0;
2161
2162 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2163 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
2164 {
2165 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2166
2167 if (nt_diff == 0)
2168 {
2169 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2170 }
2171
2172 led_on = !led_on;
2173 if(led_on) LED_B_ON(); else LED_B_OFF();
2174
2175 par_list[nt_diff] = SwapBits(par[0], 8);
2176 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2177
2178 // Test if the information is complete
2179 if (nt_diff == 0x07) {
2180 isOK = 1;
2181 break;
2182 }
2183
2184 nt_diff = (nt_diff + 1) & 0x07;
2185 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2186 par[0] = par_low;
2187 } else {
2188 if (nt_diff == 0 && first_try)
2189 {
2190 par[0]++;
2191 } else {
2192 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2193 }
2194 }
2195 }
2196
2197
2198 mf_nr_ar[3] &= 0x1F;
2199
2200 byte_t buf[28];
2201 memcpy(buf + 0, uid, 4);
2202 num_to_bytes(nt, 4, buf + 4);
2203 memcpy(buf + 8, par_list, 8);
2204 memcpy(buf + 16, ks_list, 8);
2205 memcpy(buf + 24, mf_nr_ar, 4);
2206
2207 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2208
2209 // Thats it...
2210 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2211 LEDsoff();
2212
2213 set_tracing(FALSE);
2214 }
2215
2216 /**
2217 *MIFARE 1K simulate.
2218 *
2219 *@param flags :
2220 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2221 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2222 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2223 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2224 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2225 */
2226 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2227 {
2228 int cardSTATE = MFEMUL_NOFIELD;
2229 int _7BUID = 0;
2230 int vHf = 0; // in mV
2231 int res;
2232 uint32_t selTimer = 0;
2233 uint32_t authTimer = 0;
2234 uint16_t len = 0;
2235 uint8_t cardWRBL = 0;
2236 uint8_t cardAUTHSC = 0;
2237 uint8_t cardAUTHKEY = 0xff; // no authentication
2238 uint32_t cardRr = 0;
2239 uint32_t cuid = 0;
2240 //uint32_t rn_enc = 0;
2241 uint32_t ans = 0;
2242 uint32_t cardINTREG = 0;
2243 uint8_t cardINTBLOCK = 0;
2244 struct Crypto1State mpcs = {0, 0};
2245 struct Crypto1State *pcs;
2246 pcs = &mpcs;
2247 uint32_t numReads = 0;//Counts numer of times reader read a block
2248 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2249 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2250 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2251 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2252
2253 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2254 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2255 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2256 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2257 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2258
2259 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2260 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2261
2262 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2263 // This can be used in a reader-only attack.
2264 // (it can also be retrieved via 'hf 14a list', but hey...
2265 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2266 uint8_t ar_nr_collected = 0;
2267
2268 // free eventually allocated BigBuf memory but keep Emulator Memory
2269 BigBuf_free_keep_EM();
2270
2271 // clear trace
2272 clear_trace();
2273 set_tracing(TRUE);
2274
2275 // Authenticate response - nonce
2276 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2277
2278 //-- Determine the UID
2279 // Can be set from emulator memory, incoming data
2280 // and can be 7 or 4 bytes long
2281 if (flags & FLAG_4B_UID_IN_DATA)
2282 {
2283 // 4B uid comes from data-portion of packet
2284 memcpy(rUIDBCC1,datain,4);
2285 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2286
2287 } else if (flags & FLAG_7B_UID_IN_DATA) {
2288 // 7B uid comes from data-portion of packet
2289 memcpy(&rUIDBCC1[1],datain,3);
2290 memcpy(rUIDBCC2, datain+3, 4);
2291 _7BUID = true;
2292 } else {
2293 // get UID from emul memory
2294 emlGetMemBt(receivedCmd, 7, 1);
2295 _7BUID = !(receivedCmd[0] == 0x00);
2296 if (!_7BUID) { // ---------- 4BUID
2297 emlGetMemBt(rUIDBCC1, 0, 4);
2298 } else { // ---------- 7BUID
2299 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2300 emlGetMemBt(rUIDBCC2, 3, 4);
2301 }
2302 }
2303
2304 /*
2305 * Regardless of what method was used to set the UID, set fifth byte and modify
2306 * the ATQA for 4 or 7-byte UID
2307 */
2308 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2309 if (_7BUID) {
2310 rATQA[0] = 0x44;
2311 rUIDBCC1[0] = 0x88;
2312 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2313 }
2314
2315 // We need to listen to the high-frequency, peak-detected path.
2316 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2317
2318
2319 if (MF_DBGLEVEL >= 1) {
2320 if (!_7BUID) {
2321 Dbprintf("4B UID: %02x%02x%02x%02x",
2322 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2323 } else {
2324 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2325 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2326 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2327 }
2328 }
2329
2330 bool finished = FALSE;
2331 while (!BUTTON_PRESS() && !finished) {
2332 WDT_HIT();
2333
2334 // find reader field
2335 if (cardSTATE == MFEMUL_NOFIELD) {
2336 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2337 if (vHf > MF_MINFIELDV) {
2338 cardSTATE_TO_IDLE();
2339 LED_A_ON();
2340 }
2341 }
2342 if(cardSTATE == MFEMUL_NOFIELD) continue;
2343
2344 //Now, get data
2345
2346 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2347 if (res == 2) { //Field is off!
2348 cardSTATE = MFEMUL_NOFIELD;
2349 LEDsoff();
2350 continue;
2351 } else if (res == 1) {
2352 break; //return value 1 means button press
2353 }
2354
2355 // REQ or WUP request in ANY state and WUP in HALTED state
2356 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2357 selTimer = GetTickCount();
2358 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2359 cardSTATE = MFEMUL_SELECT1;
2360
2361 // init crypto block
2362 LED_B_OFF();
2363 LED_C_OFF();
2364 crypto1_destroy(pcs);
2365 cardAUTHKEY = 0xff;
2366 continue;
2367 }
2368
2369 switch (cardSTATE) {
2370 case MFEMUL_NOFIELD:
2371 case MFEMUL_HALTED:
2372 case MFEMUL_IDLE:{
2373 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2374 break;
2375 }
2376 case MFEMUL_SELECT1:{
2377 // select all
2378 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2379 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2380 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2381 break;
2382 }
2383
2384 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2385 {
2386 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2387 }
2388 // select card
2389 if (len == 9 &&
2390 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2391 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2392 cuid = bytes_to_num(rUIDBCC1, 4);
2393 if (!_7BUID) {
2394 cardSTATE = MFEMUL_WORK;
2395 LED_B_ON();
2396 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2397 break;
2398 } else {
2399 cardSTATE = MFEMUL_SELECT2;
2400 }
2401 }
2402 break;
2403 }
2404 case MFEMUL_AUTH1:{
2405 if( len != 8)
2406 {
2407 cardSTATE_TO_IDLE();
2408 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2409 break;
2410 }
2411
2412 uint32_t ar = bytes_to_num(receivedCmd, 4);
2413 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2414
2415 //Collect AR/NR
2416 if(ar_nr_collected < 2){
2417 if(ar_nr_responses[2] != ar)
2418 {// Avoid duplicates... probably not necessary, ar should vary.
2419 ar_nr_responses[ar_nr_collected*4] = cuid;
2420 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2421 ar_nr_responses[ar_nr_collected*4+2] = ar;
2422 ar_nr_responses[ar_nr_collected*4+3] = nr;
2423 ar_nr_collected++;
2424 }
2425 }
2426
2427 // --- crypto
2428 crypto1_word(pcs, ar , 1);
2429 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2430
2431 // test if auth OK
2432 if (cardRr != prng_successor(nonce, 64)){
2433 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2434 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2435 cardRr, prng_successor(nonce, 64));
2436 // Shouldn't we respond anything here?
2437 // Right now, we don't nack or anything, which causes the
2438 // reader to do a WUPA after a while. /Martin
2439 // -- which is the correct response. /piwi
2440 cardSTATE_TO_IDLE();
2441 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2442 break;
2443 }
2444
2445 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2446
2447 num_to_bytes(ans, 4, rAUTH_AT);
2448 // --- crypto
2449 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2450 LED_C_ON();
2451 cardSTATE = MFEMUL_WORK;
2452 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2453 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2454 GetTickCount() - authTimer);
2455 break;
2456 }
2457 case MFEMUL_SELECT2:{
2458 if (!len) {
2459 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2460 break;
2461 }
2462 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2463 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2464 break;
2465 }
2466
2467 // select 2 card
2468 if (len == 9 &&
2469 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2470 EmSendCmd(rSAK, sizeof(rSAK));
2471 cuid = bytes_to_num(rUIDBCC2, 4);
2472 cardSTATE = MFEMUL_WORK;
2473 LED_B_ON();
2474 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2475 break;
2476 }
2477
2478 // i guess there is a command). go into the work state.
2479 if (len != 4) {
2480 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2481 break;
2482 }
2483 cardSTATE = MFEMUL_WORK;
2484 //goto lbWORK;
2485 //intentional fall-through to the next case-stmt
2486 }
2487
2488 case MFEMUL_WORK:{
2489 if (len == 0) {
2490 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2491 break;
2492 }
2493
2494 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2495
2496 if(encrypted_data) {
2497 // decrypt seqence
2498 mf_crypto1_decrypt(pcs, receivedCmd, len);
2499 }
2500
2501 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2502 authTimer = GetTickCount();
2503 cardAUTHSC = receivedCmd[1] / 4; // received block num
2504 cardAUTHKEY = receivedCmd[0] - 0x60;
2505 crypto1_destroy(pcs);//Added by martin
2506 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2507
2508 if (!encrypted_data) { // first authentication
2509 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2510
2511 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2512 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2513 } else { // nested authentication
2514 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2515 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2516 num_to_bytes(ans, 4, rAUTH_AT);
2517 }
2518
2519 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2520 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2521 cardSTATE = MFEMUL_AUTH1;
2522 break;
2523 }
2524
2525 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2526 // BUT... ACK --> NACK
2527 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2528 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2529 break;
2530 }
2531
2532 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2533 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2534 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2535 break;
2536 }
2537
2538 if(len != 4) {
2539 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2540 break;
2541 }
2542
2543 if(receivedCmd[0] == 0x30 // read block
2544 || receivedCmd[0] == 0xA0 // write block
2545 || receivedCmd[0] == 0xC0 // inc
2546 || receivedCmd[0] == 0xC1 // dec
2547 || receivedCmd[0] == 0xC2 // restore
2548 || receivedCmd[0] == 0xB0) { // transfer
2549 if (receivedCmd[1] >= 16 * 4) {
2550 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2551 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2552 break;
2553 }
2554
2555 if (receivedCmd[1] / 4 != cardAUTHSC) {
2556 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2557 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2558 break;
2559 }
2560 }
2561 // read block
2562 if (receivedCmd[0] == 0x30) {
2563 if (MF_DBGLEVEL >= 4) {
2564 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2565 }
2566 emlGetMem(response, receivedCmd[1], 1);
2567 AppendCrc14443a(response, 16);
2568 mf_crypto1_encrypt(pcs, response, 18, response_par);
2569 EmSendCmdPar(response, 18, response_par);
2570 numReads++;
2571 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2572 Dbprintf("%d reads done, exiting", numReads);
2573 finished = true;
2574 }
2575 break;
2576 }
2577 // write block
2578 if (receivedCmd[0] == 0xA0) {
2579 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2580 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2581 cardSTATE = MFEMUL_WRITEBL2;
2582 cardWRBL = receivedCmd[1];
2583 break;
2584 }
2585 // increment, decrement, restore
2586 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2587 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2588 if (emlCheckValBl(receivedCmd[1])) {
2589 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2590 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2591 break;
2592 }
2593 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2594 if (receivedCmd[0] == 0xC1)
2595 cardSTATE = MFEMUL_INTREG_INC;
2596 if (receivedCmd[0] == 0xC0)
2597 cardSTATE = MFEMUL_INTREG_DEC;
2598 if (receivedCmd[0] == 0xC2)
2599 cardSTATE = MFEMUL_INTREG_REST;
2600 cardWRBL = receivedCmd[1];
2601 break;
2602 }
2603 // transfer
2604 if (receivedCmd[0] == 0xB0) {
2605 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2606 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2607 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2608 else
2609 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2610 break;
2611 }
2612 // halt
2613 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2614 LED_B_OFF();
2615 LED_C_OFF();
2616 cardSTATE = MFEMUL_HALTED;
2617 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2618 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2619 break;
2620 }
2621 // RATS
2622 if (receivedCmd[0] == 0xe0) {//RATS
2623 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2624 break;
2625 }
2626 // command not allowed
2627 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2628 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2629 break;
2630 }
2631 case MFEMUL_WRITEBL2:{
2632 if (len == 18){
2633 mf_crypto1_decrypt(pcs, receivedCmd, len);
2634 emlSetMem(receivedCmd, cardWRBL, 1);
2635 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2636 cardSTATE = MFEMUL_WORK;
2637 } else {
2638 cardSTATE_TO_IDLE();
2639 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2640 }
2641 break;
2642 }
2643
2644 case MFEMUL_INTREG_INC:{
2645 mf_crypto1_decrypt(pcs, receivedCmd, len);
2646 memcpy(&ans, receivedCmd, 4);
2647 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2648 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2649 cardSTATE_TO_IDLE();
2650 break;
2651 }
2652 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2653 cardINTREG = cardINTREG + ans;
2654 cardSTATE = MFEMUL_WORK;
2655 break;
2656 }
2657 case MFEMUL_INTREG_DEC:{
2658 mf_crypto1_decrypt(pcs, receivedCmd, len);
2659 memcpy(&ans, receivedCmd, 4);
2660 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2661 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2662 cardSTATE_TO_IDLE();
2663 break;
2664 }
2665 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2666 cardINTREG = cardINTREG - ans;
2667 cardSTATE = MFEMUL_WORK;
2668 break;
2669 }
2670 case MFEMUL_INTREG_REST:{
2671 mf_crypto1_decrypt(pcs, receivedCmd, len);
2672 memcpy(&ans, receivedCmd, 4);
2673 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2674 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2675 cardSTATE_TO_IDLE();
2676 break;
2677 }
2678 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2679 cardSTATE = MFEMUL_WORK;
2680 break;
2681 }
2682 }
2683 }
2684
2685 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2686 LEDsoff();
2687
2688 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2689 {
2690 //May just aswell send the collected ar_nr in the response aswell
2691 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2692 }
2693
2694 if(flags & FLAG_NR_AR_ATTACK)
2695 {
2696 if(ar_nr_collected > 1) {
2697 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2698 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2699 ar_nr_responses[0], // UID
2700 ar_nr_responses[1], //NT
2701 ar_nr_responses[2], //AR1
2702 ar_nr_responses[3], //NR1
2703 ar_nr_responses[6], //AR2
2704 ar_nr_responses[7] //NR2
2705 );
2706 } else {
2707 Dbprintf("Failed to obtain two AR/NR pairs!");
2708 if(ar_nr_collected >0) {
2709 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2710 ar_nr_responses[0], // UID
2711 ar_nr_responses[1], //NT
2712 ar_nr_responses[2], //AR1
2713 ar_nr_responses[3] //NR1
2714 );
2715 }
2716 }
2717 }
2718 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2719
2720 }
2721
2722
2723
2724 //-----------------------------------------------------------------------------
2725 // MIFARE sniffer.
2726 //
2727 //-----------------------------------------------------------------------------
2728 void RAMFUNC SniffMifare(uint8_t param) {
2729 // param:
2730 // bit 0 - trigger from first card answer
2731 // bit 1 - trigger from first reader 7-bit request
2732
2733 // C(red) A(yellow) B(green)
2734 LEDsoff();
2735 // init trace buffer
2736 clear_trace();
2737 set_tracing(TRUE);
2738
2739 // The command (reader -> tag) that we're receiving.
2740 // The length of a received command will in most cases be no more than 18 bytes.
2741 // So 32 should be enough!
2742 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2743 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2744 // The response (tag -> reader) that we're receiving.
2745 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2746 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2747
2748 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2749 // into trace, along with its length and other annotations.
2750 //uint8_t *trace = (uint8_t *)BigBuf;
2751
2752 // free eventually allocated BigBuf memory
2753 BigBuf_free();
2754 // allocate the DMA buffer, used to stream samples from the FPGA
2755 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2756 uint8_t *data = dmaBuf;
2757 uint8_t previous_data = 0;
2758 int maxDataLen = 0;
2759 int dataLen = 0;
2760 bool ReaderIsActive = FALSE;
2761 bool TagIsActive = FALSE;
2762
2763 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2764
2765 // Set up the demodulator for tag -> reader responses.
2766 DemodInit(receivedResponse, receivedResponsePar);
2767
2768 // Set up the demodulator for the reader -> tag commands
2769 UartInit(receivedCmd, receivedCmdPar);
2770
2771 // Setup for the DMA.
2772 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2773
2774 LED_D_OFF();
2775
2776 // init sniffer
2777 MfSniffInit();
2778
2779 // And now we loop, receiving samples.
2780 for(uint32_t sniffCounter = 0; TRUE; ) {
2781
2782 if(BUTTON_PRESS()) {
2783 DbpString("cancelled by button");
2784 break;
2785 }
2786
2787 LED_A_ON();
2788 WDT_HIT();
2789
2790 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2791 // check if a transaction is completed (timeout after 2000ms).
2792 // if yes, stop the DMA transfer and send what we have so far to the client
2793 if (MfSniffSend(2000)) {
2794 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2795 sniffCounter = 0;
2796 data = dmaBuf;
2797 maxDataLen = 0;
2798 ReaderIsActive = FALSE;
2799 TagIsActive = FALSE;
2800 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2801 }
2802 }
2803
2804 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2805 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2806 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2807 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2808 } else {
2809 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2810 }
2811 // test for length of buffer
2812 if(dataLen > maxDataLen) { // we are more behind than ever...
2813 maxDataLen = dataLen;
2814 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2815 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2816 break;
2817 }
2818 }
2819 if(dataLen < 1) continue;
2820
2821 // primary buffer was stopped ( <-- we lost data!
2822 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2823 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2824 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2825 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2826 }
2827 // secondary buffer sets as primary, secondary buffer was stopped
2828 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2829 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2830 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2831 }
2832
2833 LED_A_OFF();
2834
2835 if (sniffCounter & 0x01) {
2836
2837 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2838 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2839 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2840 LED_C_INV();
2841 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
2842
2843 /* And ready to receive another command. */
2844 UartInit(receivedCmd, receivedCmdPar);
2845
2846 /* And also reset the demod code */
2847 DemodReset();
2848 }
2849 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2850 }
2851
2852 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2853 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2854 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2855 LED_C_INV();
2856
2857 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
2858
2859 // And ready to receive another response.
2860 DemodReset();
2861 // And reset the Miller decoder including its (now outdated) input buffer
2862 UartInit(receivedCmd, receivedCmdPar);
2863 }
2864 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2865 }
2866 }
2867
2868 previous_data = *data;
2869 sniffCounter++;
2870 data++;
2871 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2872 data = dmaBuf;
2873 }
2874
2875 } // main cycle
2876
2877 DbpString("COMMAND FINISHED");
2878
2879 FpgaDisableSscDma();
2880 MfSniffEnd();
2881
2882 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2883 LEDsoff();
2884 }
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