1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
13 #include "iso14443a.h"
17 #include "proxmark3.h"
21 #include "iso14443crc.h"
22 #include "crapto1/crapto1.h"
23 #include "mifareutil.h"
24 #include "mifaresniff.h"
26 #include "protocols.h"
33 // DEMOD_MOD_FIRST_HALF,
34 // DEMOD_NOMOD_FIRST_HALF,
40 uint16_t collisionPos
;
47 uint32_t startTime
, endTime
;
62 STATE_START_OF_COMMUNICATION
,
78 uint32_t startTime
, endTime
;
83 static uint32_t iso14a_timeout
;
84 #define MAX_ISO14A_TIMEOUT 524288
88 // the block number for the ISO14443-4 PCB
89 static uint8_t iso14_pcb_blocknum
= 0;
94 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
95 #define REQUEST_GUARD_TIME (7000/16 + 1)
96 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
97 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
98 // bool LastCommandWasRequest = false;
101 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
103 // When the PM acts as reader and is receiving tag data, it takes
104 // 3 ticks delay in the AD converter
105 // 16 ticks until the modulation detector completes and sets curbit
106 // 8 ticks until bit_to_arm is assigned from curbit
107 // 8*16 ticks for the transfer from FPGA to ARM
108 // 4*16 ticks until we measure the time
109 // - 8*16 ticks because we measure the time of the previous transfer
110 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
112 // When the PM acts as a reader and is sending, it takes
113 // 4*16 ticks until we can write data to the sending hold register
114 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
115 // 8 ticks until the first transfer starts
116 // 8 ticks later the FPGA samples the data
117 // 1 tick to assign mod_sig_coil
118 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
120 // When the PM acts as tag and is receiving it takes
121 // 2 ticks delay in the RF part (for the first falling edge),
122 // 3 ticks for the A/D conversion,
123 // 8 ticks on average until the start of the SSC transfer,
124 // 8 ticks until the SSC samples the first data
125 // 7*16 ticks to complete the transfer from FPGA to ARM
126 // 8 ticks until the next ssp_clk rising edge
127 // 4*16 ticks until we measure the time
128 // - 8*16 ticks because we measure the time of the previous transfer
129 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
131 // The FPGA will report its internal sending delay in
132 uint16_t FpgaSendQueueDelay
;
133 // the 5 first bits are the number of bits buffered in mod_sig_buf
134 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
135 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
137 // When the PM acts as tag and is sending, it takes
138 // 4*16 + 8 ticks until we can write data to the sending hold register
139 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
140 // 8 ticks later the FPGA samples the first data
141 // + 16 ticks until assigned to mod_sig
142 // + 1 tick to assign mod_sig_coil
143 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
144 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE)
146 // When the PM acts as sniffer and is receiving tag data, it takes
147 // 3 ticks A/D conversion
148 // 14 ticks to complete the modulation detection
149 // 8 ticks (on average) until the result is stored in to_arm
150 // + the delays in transferring data - which is the same for
151 // sniffing reader and tag data and therefore not relevant
152 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
154 // When the PM acts as sniffer and is receiving reader data, it takes
155 // 2 ticks delay in analogue RF receiver (for the falling edge of the
156 // start bit, which marks the start of the communication)
157 // 3 ticks A/D conversion
158 // 8 ticks on average until the data is stored in to_arm.
159 // + the delays in transferring data - which is the same for
160 // sniffing reader and tag data and therefore not relevant
161 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
163 //variables used for timing purposes:
164 //these are in ssp_clk cycles:
165 static uint32_t NextTransferTime
;
166 static uint32_t LastTimeProxToAirStart
;
167 static uint32_t LastProxToAirDuration
;
171 // CARD TO READER - manchester
172 // Sequence D: 11110000 modulation with subcarrier during first half
173 // Sequence E: 00001111 modulation with subcarrier during second half
174 // Sequence F: 00000000 no modulation with subcarrier
175 // READER TO CARD - miller
176 // Sequence X: 00001100 drop after half a period
177 // Sequence Y: 00000000 no drop
178 // Sequence Z: 11000000 drop at start
186 void iso14a_set_trigger(bool enable
) {
191 void iso14a_set_timeout(uint32_t timeout
) {
192 iso14a_timeout
= timeout
;
193 if(MF_DBGLEVEL
>= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout
, iso14a_timeout
/ 106);
197 static void iso14a_set_ATS_timeout(uint8_t *ats
) {
203 if (ats
[0] > 1) { // there is a format byte T0
204 if ((ats
[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
205 if ((ats
[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
210 fwi
= (tb1
& 0xf0) >> 4; // frame waiting indicator (FWI)
211 fwt
= 256 * 16 * (1 << fwi
); // frame waiting time (FWT) in 1/fc
213 iso14a_set_timeout(fwt
/(8*16));
219 //-----------------------------------------------------------------------------
220 // Generate the parity value for a byte sequence
222 //-----------------------------------------------------------------------------
223 void GetParity(const uint8_t *pbtCmd
, uint16_t iLen
, uint8_t *par
)
225 uint16_t paritybit_cnt
= 0;
226 uint16_t paritybyte_cnt
= 0;
227 uint8_t parityBits
= 0;
229 for (uint16_t i
= 0; i
< iLen
; i
++) {
230 // Generate the parity bits
231 parityBits
|= ((oddparity8(pbtCmd
[i
])) << (7-paritybit_cnt
));
232 if (paritybit_cnt
== 7) {
233 par
[paritybyte_cnt
] = parityBits
; // save 8 Bits parity
234 parityBits
= 0; // and advance to next Parity Byte
242 // save remaining parity bits
243 par
[paritybyte_cnt
] = parityBits
;
247 void AppendCrc14443a(uint8_t* data
, int len
)
249 ComputeCrc14443(CRC_14443_A
,data
,len
,data
+len
,data
+len
+1);
252 static void AppendCrc14443b(uint8_t* data
, int len
)
254 ComputeCrc14443(CRC_14443_B
,data
,len
,data
+len
,data
+len
+1);
258 //=============================================================================
259 // ISO 14443 Type A - Miller decoder
260 //=============================================================================
262 // This decoder is used when the PM3 acts as a tag.
263 // The reader will generate "pauses" by temporarily switching of the field.
264 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
265 // The FPGA does a comparison with a threshold and would deliver e.g.:
266 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
267 // The Miller decoder needs to identify the following sequences:
268 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
269 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
270 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
271 // Note 1: the bitstream may start at any time. We therefore need to sync.
272 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
273 //-----------------------------------------------------------------------------
276 // Lookup-Table to decide if 4 raw bits are a modulation.
277 // We accept the following:
278 // 0001 - a 3 tick wide pause
279 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
280 // 0111 - a 2 tick wide pause shifted left
281 // 1001 - a 2 tick wide pause shifted right
282 const bool Mod_Miller_LUT
[] = {
283 false, true, false, true, false, false, false, true,
284 false, true, false, false, false, false, false, false
286 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
287 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
289 static void UartReset()
291 Uart
.state
= STATE_UNSYNCD
;
293 Uart
.len
= 0; // number of decoded data bytes
294 Uart
.parityLen
= 0; // number of decoded parity bytes
295 Uart
.shiftReg
= 0; // shiftreg to hold decoded data bits
296 Uart
.parityBits
= 0; // holds 8 parity bits
301 static void UartInit(uint8_t *data
, uint8_t *parity
)
304 Uart
.parity
= parity
;
305 Uart
.fourBits
= 0x00000000; // clear the buffer for 4 Bits
309 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
310 static RAMFUNC
bool MillerDecoding(uint8_t bit
, uint32_t non_real_time
)
313 Uart
.fourBits
= (Uart
.fourBits
<< 8) | bit
;
315 if (Uart
.state
== STATE_UNSYNCD
) { // not yet synced
317 Uart
.syncBit
= 9999; // not set
318 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
319 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
320 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
321 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
322 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
323 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
324 if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 0)) == ISO14443A_STARTBIT_PATTERN
>> 0) Uart
.syncBit
= 7;
325 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 1)) == ISO14443A_STARTBIT_PATTERN
>> 1) Uart
.syncBit
= 6;
326 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 2)) == ISO14443A_STARTBIT_PATTERN
>> 2) Uart
.syncBit
= 5;
327 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 3)) == ISO14443A_STARTBIT_PATTERN
>> 3) Uart
.syncBit
= 4;
328 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 4)) == ISO14443A_STARTBIT_PATTERN
>> 4) Uart
.syncBit
= 3;
329 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 5)) == ISO14443A_STARTBIT_PATTERN
>> 5) Uart
.syncBit
= 2;
330 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 6)) == ISO14443A_STARTBIT_PATTERN
>> 6) Uart
.syncBit
= 1;
331 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 7)) == ISO14443A_STARTBIT_PATTERN
>> 7) Uart
.syncBit
= 0;
333 if (Uart
.syncBit
!= 9999) { // found a sync bit
334 Uart
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
335 Uart
.startTime
-= Uart
.syncBit
;
336 Uart
.endTime
= Uart
.startTime
;
337 Uart
.state
= STATE_START_OF_COMMUNICATION
;
342 if (IsMillerModulationNibble1(Uart
.fourBits
>> Uart
.syncBit
)) {
343 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation in both halves - error
345 } else { // Modulation in first half = Sequence Z = logic "0"
346 if (Uart
.state
== STATE_MILLER_X
) { // error - must not follow after X
350 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
351 Uart
.state
= STATE_MILLER_Z
;
352 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 6;
353 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
354 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
355 Uart
.parityBits
<<= 1; // make room for the parity bit
356 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
359 if((Uart
.len
&0x0007) == 0) { // every 8 data bytes
360 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
367 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation second half = Sequence X = logic "1"
369 Uart
.shiftReg
= (Uart
.shiftReg
>> 1) | 0x100; // add a 1 to the shiftreg
370 Uart
.state
= STATE_MILLER_X
;
371 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 2;
372 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
373 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
374 Uart
.parityBits
<<= 1; // make room for the new parity bit
375 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
378 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
379 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
383 } else { // no modulation in both halves - Sequence Y
384 if (Uart
.state
== STATE_MILLER_Z
|| Uart
.state
== STATE_MILLER_Y
) { // Y after logic "0" - End of Communication
385 Uart
.state
= STATE_UNSYNCD
;
386 Uart
.bitCount
--; // last "0" was part of EOC sequence
387 Uart
.shiftReg
<<= 1; // drop it
388 if(Uart
.bitCount
> 0) { // if we decoded some bits
389 Uart
.shiftReg
>>= (9 - Uart
.bitCount
); // right align them
390 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff); // add last byte to the output
391 Uart
.parityBits
<<= 1; // add a (void) parity bit
392 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align parity bits
393 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store it
395 } else if (Uart
.len
& 0x0007) { // there are some parity bits to store
396 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align remaining parity bits
397 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store them
400 return true; // we are finished with decoding the raw data sequence
402 UartReset(); // Nothing received - start over
405 if (Uart
.state
== STATE_START_OF_COMMUNICATION
) { // error - must not follow directly after SOC
407 } else { // a logic "0"
409 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
410 Uart
.state
= STATE_MILLER_Y
;
411 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
412 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
413 Uart
.parityBits
<<= 1; // make room for the parity bit
414 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
417 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
418 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
428 return false; // not finished yet, need more data
433 //=============================================================================
434 // ISO 14443 Type A - Manchester decoder
435 //=============================================================================
437 // This decoder is used when the PM3 acts as a reader.
438 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
439 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
440 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
441 // The Manchester decoder needs to identify the following sequences:
442 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
443 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
444 // 8 ticks unmodulated: Sequence F = end of communication
445 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
446 // Note 1: the bitstream may start at any time. We therefore need to sync.
447 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
450 // Lookup-Table to decide if 4 raw bits are a modulation.
451 // We accept three or four "1" in any position
452 const bool Mod_Manchester_LUT
[] = {
453 false, false, false, false, false, false, false, true,
454 false, false, false, true, false, true, true, true
457 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
458 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
461 static void DemodReset()
463 Demod
.state
= DEMOD_UNSYNCD
;
464 Demod
.len
= 0; // number of decoded data bytes
466 Demod
.shiftReg
= 0; // shiftreg to hold decoded data bits
467 Demod
.parityBits
= 0; //
468 Demod
.collisionPos
= 0; // Position of collision bit
469 Demod
.twoBits
= 0xffff; // buffer for 2 Bits
475 static void DemodInit(uint8_t *data
, uint8_t *parity
)
478 Demod
.parity
= parity
;
482 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
483 static RAMFUNC
int ManchesterDecoding(uint8_t bit
, uint16_t offset
, uint32_t non_real_time
)
486 Demod
.twoBits
= (Demod
.twoBits
<< 8) | bit
;
488 if (Demod
.state
== DEMOD_UNSYNCD
) {
490 if (Demod
.highCnt
< 2) { // wait for a stable unmodulated signal
491 if (Demod
.twoBits
== 0x0000) {
497 Demod
.syncBit
= 0xFFFF; // not set
498 if ((Demod
.twoBits
& 0x7700) == 0x7000) Demod
.syncBit
= 7;
499 else if ((Demod
.twoBits
& 0x3B80) == 0x3800) Demod
.syncBit
= 6;
500 else if ((Demod
.twoBits
& 0x1DC0) == 0x1C00) Demod
.syncBit
= 5;
501 else if ((Demod
.twoBits
& 0x0EE0) == 0x0E00) Demod
.syncBit
= 4;
502 else if ((Demod
.twoBits
& 0x0770) == 0x0700) Demod
.syncBit
= 3;
503 else if ((Demod
.twoBits
& 0x03B8) == 0x0380) Demod
.syncBit
= 2;
504 else if ((Demod
.twoBits
& 0x01DC) == 0x01C0) Demod
.syncBit
= 1;
505 else if ((Demod
.twoBits
& 0x00EE) == 0x00E0) Demod
.syncBit
= 0;
506 if (Demod
.syncBit
!= 0xFFFF) {
507 Demod
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
508 Demod
.startTime
-= Demod
.syncBit
;
509 Demod
.bitCount
= offset
; // number of decoded data bits
510 Demod
.state
= DEMOD_MANCHESTER_DATA
;
516 if (IsManchesterModulationNibble1(Demod
.twoBits
>> Demod
.syncBit
)) { // modulation in first half
517 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // ... and in second half = collision
518 if (!Demod
.collisionPos
) {
519 Demod
.collisionPos
= (Demod
.len
<< 3) + Demod
.bitCount
;
521 } // modulation in first half only - Sequence D = 1
523 Demod
.shiftReg
= (Demod
.shiftReg
>> 1) | 0x100; // in both cases, add a 1 to the shiftreg
524 if(Demod
.bitCount
== 9) { // if we decoded a full byte (including parity)
525 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
526 Demod
.parityBits
<<= 1; // make room for the parity bit
527 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
530 if((Demod
.len
&0x0007) == 0) { // every 8 data bytes
531 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits
532 Demod
.parityBits
= 0;
535 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1) - 4;
536 } else { // no modulation in first half
537 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // and modulation in second half = Sequence E = 0
539 Demod
.shiftReg
= (Demod
.shiftReg
>> 1); // add a 0 to the shiftreg
540 if(Demod
.bitCount
>= 9) { // if we decoded a full byte (including parity)
541 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
542 Demod
.parityBits
<<= 1; // make room for the new parity bit
543 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
546 if ((Demod
.len
&0x0007) == 0) { // every 8 data bytes
547 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits1
548 Demod
.parityBits
= 0;
551 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1);
552 } else { // no modulation in both halves - End of communication
553 if(Demod
.bitCount
> 0) { // there are some remaining data bits
554 Demod
.shiftReg
>>= (9 - Demod
.bitCount
); // right align the decoded bits
555 Demod
.output
[Demod
.len
++] = Demod
.shiftReg
& 0xff; // and add them to the output
556 Demod
.parityBits
<<= 1; // add a (void) parity bit
557 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
558 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
560 } else if (Demod
.len
& 0x0007) { // there are some parity bits to store
561 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
562 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
565 return true; // we are finished with decoding the raw data sequence
566 } else { // nothing received. Start over
574 return false; // not finished yet, need more data
577 //=============================================================================
578 // Finally, a `sniffer' for ISO 14443 Type A
579 // Both sides of communication!
580 //=============================================================================
582 //-----------------------------------------------------------------------------
583 // Record the sequence of commands sent by the reader to the tag, with
584 // triggering so that we start recording at the point that the tag is moved
586 //-----------------------------------------------------------------------------
587 void RAMFUNC
SnoopIso14443a(uint8_t param
) {
589 // bit 0 - trigger from first card answer
590 // bit 1 - trigger from first reader 7-bit request
594 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
596 // Allocate memory from BigBuf for some buffers
597 // free all previous allocations first
600 // The command (reader -> tag) that we're receiving.
601 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
602 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
604 // The response (tag -> reader) that we're receiving.
605 uint8_t *receivedResponse
= BigBuf_malloc(MAX_FRAME_SIZE
);
606 uint8_t *receivedResponsePar
= BigBuf_malloc(MAX_PARITY_SIZE
);
608 // The DMA buffer, used to stream samples from the FPGA
609 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
615 uint8_t *data
= dmaBuf
;
616 uint8_t previous_data
= 0;
619 bool TagIsActive
= false;
620 bool ReaderIsActive
= false;
622 // Set up the demodulator for tag -> reader responses.
623 DemodInit(receivedResponse
, receivedResponsePar
);
625 // Set up the demodulator for the reader -> tag commands
626 UartInit(receivedCmd
, receivedCmdPar
);
628 // Setup and start DMA.
629 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
);
631 // We won't start recording the frames that we acquire until we trigger;
632 // a good trigger condition to get started is probably when we see a
633 // response from the tag.
634 // triggered == false -- to wait first for card
635 bool triggered
= !(param
& 0x03);
637 // And now we loop, receiving samples.
638 for(uint32_t rsamples
= 0; true; ) {
641 DbpString("cancelled by button");
648 int register readBufDataP
= data
- dmaBuf
;
649 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
;
650 if (readBufDataP
<= dmaBufDataP
){
651 dataLen
= dmaBufDataP
- readBufDataP
;
653 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
;
655 // test for length of buffer
656 if(dataLen
> maxDataLen
) {
657 maxDataLen
= dataLen
;
658 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
659 Dbprintf("blew circular buffer! dataLen=%d", dataLen
);
663 if(dataLen
< 1) continue;
665 // primary buffer was stopped( <-- we lost data!
666 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
667 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
668 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
669 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
671 // secondary buffer sets as primary, secondary buffer was stopped
672 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
673 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
674 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
679 if (rsamples
& 0x01) { // Need two samples to feed Miller and Manchester-Decoder
681 if(!TagIsActive
) { // no need to try decoding reader data if the tag is sending
682 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
683 if (MillerDecoding(readerdata
, (rsamples
-1)*4)) {
686 // check - if there is a short 7bit request from reader
687 if ((!triggered
) && (param
& 0x02) && (Uart
.len
== 1) && (Uart
.bitCount
== 7)) triggered
= true;
690 if (!LogTrace(receivedCmd
,
692 Uart
.startTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
693 Uart
.endTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
697 /* And ready to receive another command. */
699 /* And also reset the demod code, which might have been */
700 /* false-triggered by the commands from the reader. */
704 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
707 if(!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
708 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
709 if(ManchesterDecoding(tagdata
, 0, (rsamples
-1)*4)) {
712 if (!LogTrace(receivedResponse
,
714 Demod
.startTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
715 Demod
.endTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
719 if ((!triggered
) && (param
& 0x01)) triggered
= true;
721 // And ready to receive another response.
723 // And reset the Miller decoder including itS (now outdated) input buffer
724 UartInit(receivedCmd
, receivedCmdPar
);
728 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
732 previous_data
= *data
;
735 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
740 DbpString("COMMAND FINISHED");
743 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen
, Uart
.state
, Uart
.len
);
744 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart
.output
[0]);
748 //-----------------------------------------------------------------------------
749 // Prepare tag messages
750 //-----------------------------------------------------------------------------
751 static void CodeIso14443aAsTagPar(const uint8_t *cmd
, uint16_t len
, uint8_t *parity
)
755 // Correction bit, might be removed when not needed
760 ToSendStuffBit(1); // 1
766 ToSend
[++ToSendMax
] = SEC_D
;
767 LastProxToAirDuration
= 8 * ToSendMax
- 4;
769 for(uint16_t i
= 0; i
< len
; i
++) {
773 for(uint16_t j
= 0; j
< 8; j
++) {
775 ToSend
[++ToSendMax
] = SEC_D
;
777 ToSend
[++ToSendMax
] = SEC_E
;
782 // Get the parity bit
783 if (parity
[i
>>3] & (0x80>>(i
&0x0007))) {
784 ToSend
[++ToSendMax
] = SEC_D
;
785 LastProxToAirDuration
= 8 * ToSendMax
- 4;
787 ToSend
[++ToSendMax
] = SEC_E
;
788 LastProxToAirDuration
= 8 * ToSendMax
;
793 ToSend
[++ToSendMax
] = SEC_F
;
795 // Convert from last byte pos to length
800 static void Code4bitAnswerAsTag(uint8_t cmd
)
806 // Correction bit, might be removed when not needed
811 ToSendStuffBit(1); // 1
817 ToSend
[++ToSendMax
] = SEC_D
;
820 for(i
= 0; i
< 4; i
++) {
822 ToSend
[++ToSendMax
] = SEC_D
;
823 LastProxToAirDuration
= 8 * ToSendMax
- 4;
825 ToSend
[++ToSendMax
] = SEC_E
;
826 LastProxToAirDuration
= 8 * ToSendMax
;
832 ToSend
[++ToSendMax
] = SEC_F
;
834 // Convert from last byte pos to length
839 static uint8_t *LastReaderTraceTime
= NULL
;
841 static void EmLogTraceReader(void) {
842 // remember last reader trace start to fix timing info later
843 LastReaderTraceTime
= BigBuf_get_addr() + BigBuf_get_traceLen();
844 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, true);
848 static void FixLastReaderTraceTime(uint32_t tag_StartTime
) {
849 uint32_t reader_EndTime
= Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
;
850 uint32_t reader_StartTime
= Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
;
851 uint16_t reader_modlen
= reader_EndTime
- reader_StartTime
;
852 uint16_t approx_fdt
= tag_StartTime
- reader_EndTime
;
853 uint16_t exact_fdt
= (approx_fdt
- 20 + 32)/64 * 64 + 20;
854 reader_StartTime
= tag_StartTime
- exact_fdt
- reader_modlen
;
855 LastReaderTraceTime
[0] = (reader_StartTime
>> 0) & 0xff;
856 LastReaderTraceTime
[1] = (reader_StartTime
>> 8) & 0xff;
857 LastReaderTraceTime
[2] = (reader_StartTime
>> 16) & 0xff;
858 LastReaderTraceTime
[3] = (reader_StartTime
>> 24) & 0xff;
862 static void EmLogTraceTag(uint8_t *tag_data
, uint16_t tag_len
, uint8_t *tag_Parity
, uint32_t ProxToAirDuration
) {
863 uint32_t tag_StartTime
= LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_TAG
;
864 uint32_t tag_EndTime
= (LastTimeProxToAirStart
+ ProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_TAG
;
865 LogTrace(tag_data
, tag_len
, tag_StartTime
, tag_EndTime
, tag_Parity
, false);
866 FixLastReaderTraceTime(tag_StartTime
);
870 //-----------------------------------------------------------------------------
871 // Wait for commands from reader
872 // Stop when button is pressed
873 // Or return true when command is captured
874 //-----------------------------------------------------------------------------
875 static int GetIso14443aCommandFromReader(uint8_t *received
, uint8_t *parity
, int *len
)
877 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
878 // only, since we are receiving, not transmitting).
879 // Signal field is off with the appropriate LED
881 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
883 // Now run a `software UART' on the stream of incoming samples.
884 UartInit(received
, parity
);
887 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
892 if(BUTTON_PRESS()) return false;
894 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
895 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
896 if(MillerDecoding(b
, 0)) {
906 static int EmSend4bitEx(uint8_t resp
);
907 int EmSend4bit(uint8_t resp
);
908 static int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
);
909 int EmSendCmdEx(uint8_t *resp
, uint16_t respLen
);
910 int EmSendPrecompiledCmd(tag_response_info_t
*response_info
);
913 static bool prepare_tag_modulation(tag_response_info_t
* response_info
, size_t max_buffer_size
) {
914 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
915 // This will need the following byte array for a modulation sequence
916 // 144 data bits (18 * 8)
919 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
920 // 1 just for the case
922 // 166 bytes, since every bit that needs to be send costs us a byte
926 // Prepare the tag modulation bits from the message
927 GetParity(response_info
->response
, response_info
->response_n
, &(response_info
->par
));
928 CodeIso14443aAsTagPar(response_info
->response
,response_info
->response_n
, &(response_info
->par
));
930 // Make sure we do not exceed the free buffer space
931 if (ToSendMax
> max_buffer_size
) {
932 Dbprintf("Out of memory, when modulating bits for tag answer:");
933 Dbhexdump(response_info
->response_n
, response_info
->response
, false);
937 // Copy the byte array, used for this modulation to the buffer position
938 memcpy(response_info
->modulation
, ToSend
, ToSendMax
);
940 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
941 response_info
->modulation_n
= ToSendMax
;
942 response_info
->ProxToAirDuration
= LastProxToAirDuration
;
948 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
949 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
950 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation
951 // -> need 273 bytes buffer
952 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
954 bool prepare_allocated_tag_modulation(tag_response_info_t
* response_info
, uint8_t **buffer
, size_t *max_buffer_size
) {
956 // Retrieve and store the current buffer index
957 response_info
->modulation
= *buffer
;
959 // Forward the prepare tag modulation function to the inner function
960 if (prepare_tag_modulation(response_info
, *max_buffer_size
)) {
961 // Update the free buffer offset and the remaining buffer size
962 *buffer
+= ToSendMax
;
963 *max_buffer_size
-= ToSendMax
;
970 //-----------------------------------------------------------------------------
971 // Main loop of simulated tag: receive commands from reader, decide what
972 // response to send, and send it.
973 //-----------------------------------------------------------------------------
974 void SimulateIso14443aTag(int tagType
, int uid_1st
, int uid_2nd
, byte_t
* data
)
978 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
979 uint8_t response1
[2];
982 case 1: { // MIFARE Classic
983 // Says: I am Mifare 1k - original line
988 case 2: { // MIFARE Ultralight
989 // Says: I am a stupid memory tag, no crypto
994 case 3: { // MIFARE DESFire
995 // Says: I am a DESFire tag, ph33r me
1000 case 4: { // ISO/IEC 14443-4
1001 // Says: I am a javacard (JCOP)
1002 response1
[0] = 0x04;
1003 response1
[1] = 0x00;
1006 case 5: { // MIFARE TNP3XXX
1008 response1
[0] = 0x01;
1009 response1
[1] = 0x0f;
1013 Dbprintf("Error: unkown tagtype (%d)",tagType
);
1018 // The second response contains the (mandatory) first 24 bits of the UID
1019 uint8_t response2
[5] = {0x00};
1021 // Check if the uid uses the (optional) part
1022 uint8_t response2a
[5] = {0x00};
1025 response2
[0] = 0x88;
1026 num_to_bytes(uid_1st
,3,response2
+1);
1027 num_to_bytes(uid_2nd
,4,response2a
);
1028 response2a
[4] = response2a
[0] ^ response2a
[1] ^ response2a
[2] ^ response2a
[3];
1030 // Configure the ATQA and SAK accordingly
1031 response1
[0] |= 0x40;
1034 num_to_bytes(uid_1st
,4,response2
);
1035 // Configure the ATQA and SAK accordingly
1036 response1
[0] &= 0xBF;
1040 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1041 response2
[4] = response2
[0] ^ response2
[1] ^ response2
[2] ^ response2
[3];
1043 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1044 uint8_t response3
[3] = {0x00};
1046 ComputeCrc14443(CRC_14443_A
, response3
, 1, &response3
[1], &response3
[2]);
1048 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1049 uint8_t response3a
[3] = {0x00};
1050 response3a
[0] = sak
& 0xFB;
1051 ComputeCrc14443(CRC_14443_A
, response3a
, 1, &response3a
[1], &response3a
[2]);
1053 uint8_t response5
[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1054 uint8_t response6
[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1055 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1056 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1057 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1058 // TC(1) = 0x02: CID supported, NAD not supported
1059 ComputeCrc14443(CRC_14443_A
, response6
, 4, &response6
[4], &response6
[5]);
1061 #define TAG_RESPONSE_COUNT 7
1062 tag_response_info_t responses
[TAG_RESPONSE_COUNT
] = {
1063 { .response
= response1
, .response_n
= sizeof(response1
) }, // Answer to request - respond with card type
1064 { .response
= response2
, .response_n
= sizeof(response2
) }, // Anticollision cascade1 - respond with uid
1065 { .response
= response2a
, .response_n
= sizeof(response2a
) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1066 { .response
= response3
, .response_n
= sizeof(response3
) }, // Acknowledge select - cascade 1
1067 { .response
= response3a
, .response_n
= sizeof(response3a
) }, // Acknowledge select - cascade 2
1068 { .response
= response5
, .response_n
= sizeof(response5
) }, // Authentication answer (random nonce)
1069 { .response
= response6
, .response_n
= sizeof(response6
) }, // dummy ATS (pseudo-ATR), answer to RATS
1072 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1073 // Such a response is less time critical, so we can prepare them on the fly
1074 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1075 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1076 uint8_t dynamic_response_buffer
[DYNAMIC_RESPONSE_BUFFER_SIZE
];
1077 uint8_t dynamic_modulation_buffer
[DYNAMIC_MODULATION_BUFFER_SIZE
];
1078 tag_response_info_t dynamic_response_info
= {
1079 .response
= dynamic_response_buffer
,
1081 .modulation
= dynamic_modulation_buffer
,
1085 // We need to listen to the high-frequency, peak-detected path.
1086 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1088 BigBuf_free_keep_EM();
1090 // allocate buffers:
1091 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
1092 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
1093 uint8_t *free_buffer_pointer
= BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE
);
1094 size_t free_buffer_size
= ALLOCATED_TAG_MODULATION_BUFFER_SIZE
;
1099 // Prepare the responses of the anticollision phase
1100 // there will be not enough time to do this at the moment the reader sends it REQA
1101 for (size_t i
=0; i
<TAG_RESPONSE_COUNT
; i
++) {
1102 prepare_allocated_tag_modulation(&responses
[i
], &free_buffer_pointer
, &free_buffer_size
);
1107 // To control where we are in the protocol
1111 // Just to allow some checks
1117 tag_response_info_t
* p_response
;
1121 // Clean receive command buffer
1122 if(!GetIso14443aCommandFromReader(receivedCmd
, receivedCmdPar
, &len
)) {
1123 DbpString("Button press");
1129 // Okay, look at the command now.
1131 if(receivedCmd
[0] == 0x26) { // Received a REQUEST
1132 p_response
= &responses
[0]; order
= 1;
1133 } else if(receivedCmd
[0] == 0x52) { // Received a WAKEUP
1134 p_response
= &responses
[0]; order
= 6;
1135 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x93) { // Received request for UID (cascade 1)
1136 p_response
= &responses
[1]; order
= 2;
1137 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x95) { // Received request for UID (cascade 2)
1138 p_response
= &responses
[2]; order
= 20;
1139 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x93) { // Received a SELECT (cascade 1)
1140 p_response
= &responses
[3]; order
= 3;
1141 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x95) { // Received a SELECT (cascade 2)
1142 p_response
= &responses
[4]; order
= 30;
1143 } else if(receivedCmd
[0] == 0x30) { // Received a (plain) READ
1144 EmSendCmdEx(data
+(4*receivedCmd
[1]),16);
1145 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1146 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1148 } else if(receivedCmd
[0] == 0x50) { // Received a HALT
1150 } else if(receivedCmd
[0] == 0x60 || receivedCmd
[0] == 0x61) { // Received an authentication request
1151 p_response
= &responses
[5]; order
= 7;
1152 } else if(receivedCmd
[0] == 0xE0) { // Received a RATS request
1153 if (tagType
== 1 || tagType
== 2) { // RATS not supported
1154 EmSend4bit(CARD_NACK_NA
);
1157 p_response
= &responses
[6]; order
= 70;
1159 } else if (order
== 7 && len
== 8) { // Received {nr] and {ar} (part of authentication)
1160 uint32_t nr
= bytes_to_num(receivedCmd
,4);
1161 uint32_t ar
= bytes_to_num(receivedCmd
+4,4);
1162 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr
,ar
);
1164 // Check for ISO 14443A-4 compliant commands, look at left nibble
1165 switch (receivedCmd
[0]) {
1168 case 0x0A: { // IBlock (command)
1169 dynamic_response_info
.response
[0] = receivedCmd
[0];
1170 dynamic_response_info
.response
[1] = 0x00;
1171 dynamic_response_info
.response
[2] = 0x90;
1172 dynamic_response_info
.response
[3] = 0x00;
1173 dynamic_response_info
.response_n
= 4;
1177 case 0x1B: { // Chaining command
1178 dynamic_response_info
.response
[0] = 0xaa | ((receivedCmd
[0]) & 1);
1179 dynamic_response_info
.response_n
= 2;
1184 dynamic_response_info
.response
[0] = receivedCmd
[0] ^ 0x11;
1185 dynamic_response_info
.response_n
= 2;
1189 memcpy(dynamic_response_info
.response
,"\xAB\x00",2);
1190 dynamic_response_info
.response_n
= 2;
1194 case 0xC2: { // Readers sends deselect command
1195 memcpy(dynamic_response_info
.response
,"\xCA\x00",2);
1196 dynamic_response_info
.response_n
= 2;
1200 // Never seen this command before
1201 Dbprintf("Received unknown command (len=%d):",len
);
1202 Dbhexdump(len
,receivedCmd
,false);
1204 dynamic_response_info
.response_n
= 0;
1208 if (dynamic_response_info
.response_n
> 0) {
1209 // Copy the CID from the reader query
1210 dynamic_response_info
.response
[1] = receivedCmd
[1];
1212 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1213 AppendCrc14443a(dynamic_response_info
.response
,dynamic_response_info
.response_n
);
1214 dynamic_response_info
.response_n
+= 2;
1216 if (prepare_tag_modulation(&dynamic_response_info
,DYNAMIC_MODULATION_BUFFER_SIZE
) == false) {
1217 Dbprintf("Error preparing tag response");
1220 p_response
= &dynamic_response_info
;
1224 // Count number of wakeups received after a halt
1225 if(order
== 6 && lastorder
== 5) { happened
++; }
1227 // Count number of other messages after a halt
1228 if(order
!= 6 && lastorder
== 5) { happened2
++; }
1230 if(cmdsRecvd
> 999) {
1231 DbpString("1000 commands later...");
1236 if (p_response
!= NULL
) {
1237 EmSendPrecompiledCmd(p_response
);
1241 Dbprintf("Trace Full. Simulation stopped.");
1246 Dbprintf("%x %x %x", happened
, happened2
, cmdsRecvd
);
1248 BigBuf_free_keep_EM();
1252 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1253 // of bits specified in the delay parameter.
1254 static void PrepareDelayedTransfer(uint16_t delay
)
1256 uint8_t bitmask
= 0;
1257 uint8_t bits_to_shift
= 0;
1258 uint8_t bits_shifted
= 0;
1262 for (uint16_t i
= 0; i
< delay
; i
++) {
1263 bitmask
|= (0x01 << i
);
1265 ToSend
[ToSendMax
++] = 0x00;
1266 for (uint16_t i
= 0; i
< ToSendMax
; i
++) {
1267 bits_to_shift
= ToSend
[i
] & bitmask
;
1268 ToSend
[i
] = ToSend
[i
] >> delay
;
1269 ToSend
[i
] = ToSend
[i
] | (bits_shifted
<< (8 - delay
));
1270 bits_shifted
= bits_to_shift
;
1276 //-------------------------------------------------------------------------------------
1277 // Transmit the command (to the tag) that was placed in ToSend[].
1278 // Parameter timing:
1279 // if NULL: transfer at next possible time, taking into account
1280 // request guard time and frame delay time
1281 // if == 0: transfer immediately and return time of transfer
1282 // if != 0: delay transfer until time specified
1283 //-------------------------------------------------------------------------------------
1284 static void TransmitFor14443a(const uint8_t *cmd
, uint16_t len
, uint32_t *timing
)
1287 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_MOD
);
1289 uint32_t ThisTransferTime
= 0;
1292 if(*timing
== 0) { // Measure time
1293 *timing
= (GetCountSspClk() + 8) & 0xfffffff8;
1295 PrepareDelayedTransfer(*timing
& 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1297 if(MF_DBGLEVEL
>= 4 && GetCountSspClk() >= (*timing
& 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1298 while(GetCountSspClk() < (*timing
& 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1299 LastTimeProxToAirStart
= *timing
;
1301 ThisTransferTime
= ((MAX(NextTransferTime
, GetCountSspClk()) & 0xfffffff8) + 8);
1302 while(GetCountSspClk() < ThisTransferTime
);
1303 LastTimeProxToAirStart
= ThisTransferTime
;
1307 AT91C_BASE_SSC
->SSC_THR
= SEC_Y
;
1311 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1312 AT91C_BASE_SSC
->SSC_THR
= cmd
[c
];
1320 NextTransferTime
= MAX(NextTransferTime
, LastTimeProxToAirStart
+ REQUEST_GUARD_TIME
);
1324 //-----------------------------------------------------------------------------
1325 // Prepare reader command (in bits, support short frames) to send to FPGA
1326 //-----------------------------------------------------------------------------
1327 static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd
, uint16_t bits
, const uint8_t *parity
)
1335 // Start of Communication (Seq. Z)
1336 ToSend
[++ToSendMax
] = SEC_Z
;
1337 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1340 size_t bytecount
= nbytes(bits
);
1341 // Generate send structure for the data bits
1342 for (i
= 0; i
< bytecount
; i
++) {
1343 // Get the current byte to send
1345 size_t bitsleft
= MIN((bits
-(i
*8)),8);
1347 for (j
= 0; j
< bitsleft
; j
++) {
1350 ToSend
[++ToSendMax
] = SEC_X
;
1351 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1356 ToSend
[++ToSendMax
] = SEC_Z
;
1357 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1360 ToSend
[++ToSendMax
] = SEC_Y
;
1367 // Only transmit parity bit if we transmitted a complete byte
1368 if (j
== 8 && parity
!= NULL
) {
1369 // Get the parity bit
1370 if (parity
[i
>>3] & (0x80 >> (i
&0x0007))) {
1372 ToSend
[++ToSendMax
] = SEC_X
;
1373 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1378 ToSend
[++ToSendMax
] = SEC_Z
;
1379 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1382 ToSend
[++ToSendMax
] = SEC_Y
;
1389 // End of Communication: Logic 0 followed by Sequence Y
1392 ToSend
[++ToSendMax
] = SEC_Z
;
1393 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1396 ToSend
[++ToSendMax
] = SEC_Y
;
1399 ToSend
[++ToSendMax
] = SEC_Y
;
1401 // Convert to length of command:
1406 //-----------------------------------------------------------------------------
1407 // Wait for commands from reader
1408 // Stop when button is pressed (return 1) or field was gone (return 2)
1409 // Or return 0 when command is captured
1410 //-----------------------------------------------------------------------------
1411 int EmGetCmd(uint8_t *received
, uint16_t *len
, uint8_t *parity
)
1415 uint32_t timer
= 0, vtime
= 0;
1419 // Set ADC to read field strength
1420 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_SWRST
;
1421 AT91C_BASE_ADC
->ADC_MR
=
1422 ADC_MODE_PRESCALE(63) |
1423 ADC_MODE_STARTUP_TIME(1) |
1424 ADC_MODE_SAMPLE_HOLD_TIME(15);
1425 AT91C_BASE_ADC
->ADC_CHER
= ADC_CHANNEL(ADC_CHAN_HF
);
1427 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
;
1429 // Run a 'software UART' on the stream of incoming samples.
1430 UartInit(received
, parity
);
1432 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN
1434 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1435 AT91C_BASE_SSC
->SSC_THR
= SEC_F
;
1436 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1438 } while (GetCountSspClk() < LastTimeProxToAirStart
+ LastProxToAirDuration
+ (FpgaSendQueueDelay
>>3));
1440 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1441 // only, since we are receiving, not transmitting).
1442 // Signal field is off with the appropriate LED
1444 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1449 if (BUTTON_PRESS()) return 1;
1451 // test if the field exists
1452 if (AT91C_BASE_ADC
->ADC_SR
& ADC_END_OF_CONVERSION(ADC_CHAN_HF
)) {
1454 analogAVG
+= AT91C_BASE_ADC
->ADC_CDR
[ADC_CHAN_HF
];
1455 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
;
1456 if (analogCnt
>= 32) {
1457 if ((MAX_ADC_HF_VOLTAGE
* (analogAVG
/ analogCnt
) >> 10) < MF_MINFIELDV
) {
1458 vtime
= GetTickCount();
1459 if (!timer
) timer
= vtime
;
1460 // 50ms no field --> card to idle state
1461 if (vtime
- timer
> 50) return 2;
1463 if (timer
) timer
= 0;
1469 // receive and test the miller decoding
1470 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1471 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1472 if(MillerDecoding(b
, 0)) {
1483 static int EmSendCmd14443aRaw(uint8_t *resp
, uint16_t respLen
)
1487 bool correctionNeeded
;
1489 // Modulate Manchester
1490 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_MOD
);
1492 // include correction bit if necessary
1493 if (Uart
.bitCount
== 7)
1495 // Short tags (7 bits) don't have parity, determine the correct value from MSB
1496 correctionNeeded
= Uart
.output
[0] & 0x40;
1500 // Look at the last parity bit
1501 correctionNeeded
= Uart
.parity
[(Uart
.len
-1)/8] & (0x80 >> ((Uart
.len
-1) & 7));
1504 if(correctionNeeded
) {
1505 // 1236, so correction bit needed
1511 // clear receiving shift register and holding register
1512 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1513 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1514 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1515 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1517 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1518 for (uint16_t j
= 0; j
< 5; j
++) { // allow timeout - better late than never
1519 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1520 if (AT91C_BASE_SSC
->SSC_RHR
) break;
1523 LastTimeProxToAirStart
= (GetCountSspClk() & 0xfffffff8) + (correctionNeeded
?8:0);
1526 for(; i
< respLen
; ) {
1527 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1528 AT91C_BASE_SSC
->SSC_THR
= resp
[i
++];
1529 FpgaSendQueueDelay
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1532 if(BUTTON_PRESS()) {
1541 static int EmSend4bitEx(uint8_t resp
){
1542 Code4bitAnswerAsTag(resp
);
1543 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
);
1544 // do the tracing for the previous reader request and this tag answer:
1545 EmLogTraceTag(&resp
, 1, NULL
, LastProxToAirDuration
);
1550 int EmSend4bit(uint8_t resp
){
1551 return EmSend4bitEx(resp
);
1555 static int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
){
1556 CodeIso14443aAsTagPar(resp
, respLen
, par
);
1557 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
);
1558 // do the tracing for the previous reader request and this tag answer:
1559 EmLogTraceTag(resp
, respLen
, par
, LastProxToAirDuration
);
1564 int EmSendCmdEx(uint8_t *resp
, uint16_t respLen
){
1565 uint8_t par
[MAX_PARITY_SIZE
];
1566 GetParity(resp
, respLen
, par
);
1567 return EmSendCmdExPar(resp
, respLen
, par
);
1571 int EmSendCmd(uint8_t *resp
, uint16_t respLen
){
1572 uint8_t par
[MAX_PARITY_SIZE
];
1573 GetParity(resp
, respLen
, par
);
1574 return EmSendCmdExPar(resp
, respLen
, par
);
1578 int EmSendCmdPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
){
1579 return EmSendCmdExPar(resp
, respLen
, par
);
1583 int EmSendPrecompiledCmd(tag_response_info_t
*response_info
) {
1584 int ret
= EmSendCmd14443aRaw(response_info
->modulation
, response_info
->modulation_n
);
1585 // do the tracing for the previous reader request and this tag answer:
1586 EmLogTraceTag(response_info
->response
, response_info
->response_n
, &(response_info
->par
), response_info
->ProxToAirDuration
);
1591 //-----------------------------------------------------------------------------
1592 // Wait a certain time for tag response
1593 // If a response is captured return true
1594 // If it takes too long return false
1595 //-----------------------------------------------------------------------------
1596 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse
, uint8_t *receivedResponsePar
, uint16_t offset
)
1600 // Set FPGA mode to "reader listen mode", no modulation (listen
1601 // only, since we are receiving, not transmitting).
1602 // Signal field is on with the appropriate LED
1604 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_LISTEN
);
1606 // Now get the answer from the card
1607 DemodInit(receivedResponse
, receivedResponsePar
);
1610 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1616 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1617 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1618 if(ManchesterDecoding(b
, offset
, 0)) {
1619 NextTransferTime
= MAX(NextTransferTime
, Demod
.endTime
- (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/16 + FRAME_DELAY_TIME_PICC_TO_PCD
);
1621 } else if (c
++ > iso14a_timeout
&& Demod
.state
== DEMOD_UNSYNCD
) {
1629 void ReaderTransmitBitsPar(uint8_t* frame
, uint16_t bits
, uint8_t *par
, uint32_t *timing
)
1631 CodeIso14443aBitsAsReaderPar(frame
, bits
, par
);
1633 // Send command to tag
1634 TransmitFor14443a(ToSend
, ToSendMax
, timing
);
1638 // Log reader command in trace buffer
1640 LogTrace(frame
, nbytes(bits
), LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_READER
, (LastTimeProxToAirStart
+ LastProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_READER
, par
, true);
1645 void ReaderTransmitPar(uint8_t* frame
, uint16_t len
, uint8_t *par
, uint32_t *timing
)
1647 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1651 static void ReaderTransmitBits(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1653 // Generate parity and redirect
1654 uint8_t par
[MAX_PARITY_SIZE
];
1655 GetParity(frame
, len
/8, par
);
1656 ReaderTransmitBitsPar(frame
, len
, par
, timing
);
1660 void ReaderTransmit(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1662 // Generate parity and redirect
1663 uint8_t par
[MAX_PARITY_SIZE
];
1664 GetParity(frame
, len
, par
);
1665 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1669 static int ReaderReceiveOffset(uint8_t* receivedAnswer
, uint16_t offset
, uint8_t *parity
)
1671 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, offset
)) return false;
1673 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, false);
1679 int ReaderReceive(uint8_t *receivedAnswer
, uint8_t *parity
)
1681 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, 0)) return false;
1683 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, false);
1688 // performs iso14443a anticollision (optional) and card select procedure
1689 // fills the uid and cuid pointer unless NULL
1690 // fills the card info record unless NULL
1691 // if anticollision is false, then the UID must be provided in uid_ptr[]
1692 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1693 // requests ATS unless no_rats is true
1694 int iso14443a_select_card(byte_t
*uid_ptr
, iso14a_card_select_t
*p_hi14a_card
, uint32_t *cuid_ptr
, bool anticollision
, uint8_t num_cascades
, bool no_rats
) {
1695 uint8_t wupa
[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1696 uint8_t sel_all
[] = { 0x93,0x20 };
1697 uint8_t sel_uid
[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1698 uint8_t rats
[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1699 uint8_t resp
[MAX_FRAME_SIZE
]; // theoretically. A usual RATS will be much smaller
1700 uint8_t resp_par
[MAX_PARITY_SIZE
];
1702 size_t uid_resp_len
;
1704 uint8_t sak
= 0x04; // cascade uid
1705 int cascade_level
= 0;
1710 p_hi14a_card
->uidlen
= 0;
1711 memset(p_hi14a_card
->uid
, 0, 10);
1712 p_hi14a_card
->ats_len
= 0;
1715 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1716 ReaderTransmitBitsPar(wupa
, 7, NULL
, NULL
);
1719 if(!ReaderReceive(resp
, resp_par
)) return 0;
1722 memcpy(p_hi14a_card
->atqa
, resp
, 2);
1725 if (anticollision
) {
1728 memset(uid_ptr
,0,10);
1732 // check for proprietary anticollision:
1733 if ((resp
[0] & 0x1F) == 0) {
1737 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1738 // which case we need to make a cascade 2 request and select - this is a long UID
1739 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1740 for(; sak
& 0x04; cascade_level
++) {
1741 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1742 sel_uid
[0] = sel_all
[0] = 0x93 + cascade_level
* 2;
1744 if (anticollision
) {
1746 ReaderTransmit(sel_all
, sizeof(sel_all
), NULL
);
1747 if (!ReaderReceive(resp
, resp_par
)) return 0;
1749 if (Demod
.collisionPos
) { // we had a collision and need to construct the UID bit by bit
1750 memset(uid_resp
, 0, 4);
1751 uint16_t uid_resp_bits
= 0;
1752 uint16_t collision_answer_offset
= 0;
1753 // anti-collision-loop:
1754 while (Demod
.collisionPos
) {
1755 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod
.collisionPos
);
1756 for (uint16_t i
= collision_answer_offset
; i
< Demod
.collisionPos
; i
++, uid_resp_bits
++) { // add valid UID bits before collision point
1757 uint16_t UIDbit
= (resp
[i
/8] >> (i
% 8)) & 0x01;
1758 uid_resp
[uid_resp_bits
/ 8] |= UIDbit
<< (uid_resp_bits
% 8);
1760 uid_resp
[uid_resp_bits
/8] |= 1 << (uid_resp_bits
% 8); // next time select the card(s) with a 1 in the collision position
1762 // construct anticollosion command:
1763 sel_uid
[1] = ((2 + uid_resp_bits
/8) << 4) | (uid_resp_bits
& 0x07); // length of data in bytes and bits
1764 for (uint16_t i
= 0; i
<= uid_resp_bits
/8; i
++) {
1765 sel_uid
[2+i
] = uid_resp
[i
];
1767 collision_answer_offset
= uid_resp_bits
%8;
1768 ReaderTransmitBits(sel_uid
, 16 + uid_resp_bits
, NULL
);
1769 if (!ReaderReceiveOffset(resp
, collision_answer_offset
, resp_par
)) return 0;
1771 // finally, add the last bits and BCC of the UID
1772 for (uint16_t i
= collision_answer_offset
; i
< (Demod
.len
-1)*8; i
++, uid_resp_bits
++) {
1773 uint16_t UIDbit
= (resp
[i
/8] >> (i
%8)) & 0x01;
1774 uid_resp
[uid_resp_bits
/8] |= UIDbit
<< (uid_resp_bits
% 8);
1777 } else { // no collision, use the response to SELECT_ALL as current uid
1778 memcpy(uid_resp
, resp
, 4);
1781 if (cascade_level
< num_cascades
- 1) {
1783 memcpy(uid_resp
+1, uid_ptr
+cascade_level
*3, 3);
1785 memcpy(uid_resp
, uid_ptr
+cascade_level
*3, 4);
1790 // calculate crypto UID. Always use last 4 Bytes.
1792 *cuid_ptr
= bytes_to_num(uid_resp
, 4);
1795 // Construct SELECT UID command
1796 sel_uid
[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1797 memcpy(sel_uid
+2, uid_resp
, 4); // the UID received during anticollision, or the provided UID
1798 sel_uid
[6] = sel_uid
[2] ^ sel_uid
[3] ^ sel_uid
[4] ^ sel_uid
[5]; // calculate and add BCC
1799 AppendCrc14443a(sel_uid
, 7); // calculate and add CRC
1800 ReaderTransmit(sel_uid
, sizeof(sel_uid
), NULL
);
1803 if (!ReaderReceive(resp
, resp_par
)) return 0;
1806 // Test if more parts of the uid are coming
1807 if ((sak
& 0x04) /* && uid_resp[0] == 0x88 */) {
1808 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1809 // http://www.nxp.com/documents/application_note/AN10927.pdf
1810 uid_resp
[0] = uid_resp
[1];
1811 uid_resp
[1] = uid_resp
[2];
1812 uid_resp
[2] = uid_resp
[3];
1816 if(uid_ptr
&& anticollision
) {
1817 memcpy(uid_ptr
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1821 memcpy(p_hi14a_card
->uid
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1822 p_hi14a_card
->uidlen
+= uid_resp_len
;
1827 p_hi14a_card
->sak
= sak
;
1830 // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0)
1831 if( (sak
& 0x20) == 0) return 2;
1834 // Request for answer to select
1835 AppendCrc14443a(rats
, 2);
1836 ReaderTransmit(rats
, sizeof(rats
), NULL
);
1838 if (!(len
= ReaderReceive(resp
, resp_par
))) return 0;
1841 memcpy(p_hi14a_card
->ats
, resp
, len
);
1842 p_hi14a_card
->ats_len
= len
;
1845 // reset the PCB block number
1846 iso14_pcb_blocknum
= 0;
1848 // set default timeout based on ATS
1849 iso14a_set_ATS_timeout(resp
);
1855 void iso14443a_setup(uint8_t fpga_minor_mode
) {
1856 FpgaDownloadAndGo(FPGA_BITSTREAM_HF
);
1857 // Set up the synchronous serial port
1859 // connect Demodulated Signal to ADC:
1860 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
1862 // Signal field is on with the appropriate LED
1863 if (fpga_minor_mode
== FPGA_HF_ISO14443A_READER_MOD
1864 || fpga_minor_mode
== FPGA_HF_ISO14443A_READER_LISTEN
) {
1869 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| fpga_minor_mode
);
1876 NextTransferTime
= 2*DELAY_ARM2AIR_AS_READER
;
1877 iso14a_set_timeout(1060); // 10ms default
1880 /* Peter Fillmore 2015
1881 Added card id field to the function
1882 info from ISO14443A standard
1885 b3 = depends on block
1886 b4 = Card ID following if set to 1
1887 b5 = depends on block type
1888 b6 = depends on block type
1891 b8 b7 b6 b5 b4 b3 b2 b1
1895 b8 b7 b6 b5 b4 b3 b2 b1
1899 b8 b7 b6 b5 b4 b3 b2 b1
1901 b5,b6 = 00 - DESELECT
1904 int iso14_apdu(uint8_t *cmd
, uint16_t cmd_len
, void *data
) {
1905 uint8_t parity
[MAX_PARITY_SIZE
];
1906 uint8_t real_cmd
[cmd_len
+ 4];
1908 // ISO 14443 APDU frame: PCB [CID] [NAD] APDU CRC PCB=0x02
1909 real_cmd
[0] = 0x02; // bnr,nad,cid,chn=0; i-block(0x00)
1910 // put block number into the PCB
1911 real_cmd
[0] |= iso14_pcb_blocknum
;
1912 memcpy(real_cmd
+ 1, cmd
, cmd_len
);
1913 AppendCrc14443a(real_cmd
, cmd_len
+ 1);
1915 ReaderTransmit(real_cmd
, cmd_len
+ 3, NULL
);
1917 size_t len
= ReaderReceive(data
, parity
);
1918 uint8_t *data_bytes
= (uint8_t *) data
;
1921 return 0; //DATA LINK ERROR
1924 while((data_bytes
[0] & 0xF2) == 0xF2) {
1925 uint32_t save_iso14a_timeout
= iso14a_timeout
;
1926 // temporarily increase timeout
1927 iso14a_timeout
= MAX((data_bytes
[1] & 0x3f) * iso14a_timeout
, MAX_ISO14A_TIMEOUT
);
1928 // Transmit WTX back
1929 // byte1 - WTXM [1..59]. command FWT=FWT*WTXM
1930 data_bytes
[1] = data_bytes
[1] & 0x3f; // 2 high bits mandatory set to 0b
1931 // now need to fix CRC.
1932 AppendCrc14443a(data_bytes
, len
- 2);
1934 ReaderTransmit(data_bytes
, len
, NULL
);
1935 // retrieve the result again (with increased timeout)
1936 len
= ReaderReceive(data
, parity
);
1939 iso14a_timeout
= save_iso14a_timeout
;
1942 // if we received an I- or R(ACK)-Block with a block number equal to the
1943 // current block number, toggle the current block number
1944 if (len
>= 3 // PCB+CRC = 3 bytes
1945 && ((data_bytes
[0] & 0xC0) == 0 // I-Block
1946 || (data_bytes
[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1947 && (data_bytes
[0] & 0x01) == iso14_pcb_blocknum
) // equal block numbers
1949 iso14_pcb_blocknum
^= 1;
1953 if (len
>=3 && !CheckCrc14443(CRC_14443_A
, data_bytes
, len
)) {
1961 // memmove(data_bytes, data_bytes + 1, len);
1962 for (int i
= 0; i
< len
; i
++)
1963 data_bytes
[i
] = data_bytes
[i
+ 1];
1969 //-----------------------------------------------------------------------------
1970 // Read an ISO 14443a tag. Send out commands and store answers.
1972 //-----------------------------------------------------------------------------
1973 void ReaderIso14443a(UsbCommand
*c
)
1975 iso14a_command_t param
= c
->arg
[0];
1976 uint8_t *cmd
= c
->d
.asBytes
;
1977 size_t len
= c
->arg
[1] & 0xffff;
1978 size_t lenbits
= c
->arg
[1] >> 16;
1979 uint32_t timeout
= c
->arg
[2];
1981 byte_t buf
[USB_CMD_DATA_SIZE
] = {0};
1982 uint8_t par
[MAX_PARITY_SIZE
];
1983 bool cantSELECT
= false;
1987 if(param
& ISO14A_CLEAR_TRACE
) {
1991 if(param
& ISO14A_REQUEST_TRIGGER
) {
1992 iso14a_set_trigger(true);
1995 if(param
& ISO14A_CONNECT
) {
1997 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN
);
1998 if(!(param
& ISO14A_NO_SELECT
)) {
1999 iso14a_card_select_t
*card
= (iso14a_card_select_t
*)buf
;
2000 arg0
= iso14443a_select_card(NULL
, card
, NULL
, true, 0, param
& ISO14A_NO_RATS
);
2002 // if we cant select then we cant send data
2003 if (arg0
!= 1 && arg0
!= 2) {
2004 // 1 - all is OK with ATS, 2 - without ATS
2009 cmd_send(CMD_ACK
,arg0
,card
->uidlen
,0,buf
,sizeof(iso14a_card_select_t
));
2014 if(param
& ISO14A_SET_TIMEOUT
) {
2015 iso14a_set_timeout(timeout
);
2018 if(param
& ISO14A_APDU
&& !cantSELECT
) {
2019 arg0
= iso14_apdu(cmd
, len
, buf
);
2021 cmd_send(CMD_ACK
, arg0
, 0, 0, buf
, sizeof(buf
));
2025 if(param
& ISO14A_RAW
&& !cantSELECT
) {
2026 if(param
& ISO14A_APPEND_CRC
) {
2027 if(param
& ISO14A_TOPAZMODE
) {
2028 AppendCrc14443b(cmd
,len
);
2030 AppendCrc14443a(cmd
,len
);
2033 if (lenbits
) lenbits
+= 16;
2035 if(lenbits
>0) { // want to send a specific number of bits (e.g. short commands)
2036 if(param
& ISO14A_TOPAZMODE
) {
2037 int bits_to_send
= lenbits
;
2039 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 7), NULL
, NULL
); // first byte is always short (7bits) and no parity
2041 while (bits_to_send
> 0) {
2042 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 8), NULL
, NULL
); // following bytes are 8 bit and no parity
2046 GetParity(cmd
, lenbits
/8, par
);
2047 ReaderTransmitBitsPar(cmd
, lenbits
, par
, NULL
); // bytes are 8 bit with odd parity
2049 } else { // want to send complete bytes only
2050 if(param
& ISO14A_TOPAZMODE
) {
2052 ReaderTransmitBitsPar(&cmd
[i
++], 7, NULL
, NULL
); // first byte: 7 bits, no paritiy
2054 ReaderTransmitBitsPar(&cmd
[i
++], 8, NULL
, NULL
); // following bytes: 8 bits, no paritiy
2057 ReaderTransmit(cmd
,len
, NULL
); // 8 bits, odd parity
2060 arg0
= ReaderReceive(buf
, par
);
2063 cmd_send(CMD_ACK
,arg0
,0,0,buf
,sizeof(buf
));
2067 if(param
& ISO14A_REQUEST_TRIGGER
) {
2068 iso14a_set_trigger(false);
2071 if(param
& ISO14A_NO_DISCONNECT
) {
2075 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2080 // Determine the distance between two nonces.
2081 // Assume that the difference is small, but we don't know which is first.
2082 // Therefore try in alternating directions.
2083 static int32_t dist_nt(uint32_t nt1
, uint32_t nt2
) {
2086 uint32_t nttmp1
, nttmp2
;
2088 if (nt1
== nt2
) return 0;
2093 for (i
= 1; i
< 32768; i
++) {
2094 nttmp1
= prng_successor(nttmp1
, 1);
2095 if (nttmp1
== nt2
) return i
;
2096 nttmp2
= prng_successor(nttmp2
, 1);
2097 if (nttmp2
== nt1
) return -i
;
2100 return(-99999); // either nt1 or nt2 are invalid nonces
2104 //-----------------------------------------------------------------------------
2105 // Recover several bits of the cypher stream. This implements (first stages of)
2106 // the algorithm described in "The Dark Side of Security by Obscurity and
2107 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2108 // (article by Nicolas T. Courtois, 2009)
2109 //-----------------------------------------------------------------------------
2110 void ReaderMifare(bool first_try
)
2113 uint8_t mf_auth
[] = { 0x60,0x00,0xf5,0x7b };
2114 uint8_t mf_nr_ar
[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2115 static uint8_t mf_nr_ar3
;
2117 uint8_t receivedAnswer
[MAX_MIFARE_FRAME_SIZE
];
2118 uint8_t receivedAnswerPar
[MAX_MIFARE_PARITY_SIZE
];
2121 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2124 // free eventually allocated BigBuf memory. We want all for tracing.
2131 uint8_t par
[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2132 static byte_t par_low
= 0;
2134 uint8_t uid
[10] ={0};
2138 uint32_t previous_nt
= 0;
2139 static uint32_t nt_attacked
= 0;
2140 byte_t par_list
[8] = {0x00};
2141 byte_t ks_list
[8] = {0x00};
2143 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2144 static uint32_t sync_time
;
2145 static int32_t sync_cycles
;
2146 int catch_up_cycles
= 0;
2147 int last_catch_up
= 0;
2148 uint16_t elapsed_prng_sequences
;
2149 uint16_t consecutive_resyncs
= 0;
2154 sync_time
= GetCountSspClk() & 0xfffffff8;
2155 sync_cycles
= PRNG_SEQUENCE_LENGTH
; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2160 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2162 mf_nr_ar
[3] = mf_nr_ar3
;
2171 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2172 #define MAX_SYNC_TRIES 32
2173 #define NUM_DEBUG_INFOS 8 // per strategy
2174 #define MAX_STRATEGY 3
2175 uint16_t unexpected_random
= 0;
2176 uint16_t sync_tries
= 0;
2177 int16_t debug_info_nr
= -1;
2178 uint16_t strategy
= 0;
2179 int32_t debug_info
[MAX_STRATEGY
][NUM_DEBUG_INFOS
];
2180 uint32_t select_time
;
2183 for(uint16_t i
= 0; true; i
++) {
2188 // Test if the action was cancelled
2189 if(BUTTON_PRESS()) {
2194 if (strategy
== 2) {
2195 // test with additional hlt command
2197 int len
= mifare_sendcmd_short(NULL
, false, 0x50, 0x00, receivedAnswer
, receivedAnswerPar
, &halt_time
);
2198 if (len
&& MF_DBGLEVEL
>= 3) {
2199 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len
);
2203 if (strategy
== 3) {
2204 // test with FPGA power off/on
2205 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2207 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2211 if(!iso14443a_select_card(uid
, NULL
, &cuid
, true, 0, true)) {
2212 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Can't select card");
2215 select_time
= GetCountSspClk();
2217 elapsed_prng_sequences
= 1;
2218 if (debug_info_nr
== -1) {
2219 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
+ catch_up_cycles
;
2220 catch_up_cycles
= 0;
2222 // if we missed the sync time already, advance to the next nonce repeat
2223 while(GetCountSspClk() > sync_time
) {
2224 elapsed_prng_sequences
++;
2225 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
;
2228 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2229 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2231 // collect some information on tag nonces for debugging:
2232 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2233 if (strategy
== 0) {
2234 // nonce distances at fixed time after card select:
2235 sync_time
= select_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2236 } else if (strategy
== 1) {
2237 // nonce distances at fixed time between authentications:
2238 sync_time
= sync_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2239 } else if (strategy
== 2) {
2240 // nonce distances at fixed time after halt:
2241 sync_time
= halt_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2243 // nonce_distances at fixed time after power on
2244 sync_time
= DEBUG_FIXED_SYNC_CYCLES
;
2246 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2249 // Receive the (4 Byte) "random" nonce
2250 if (!ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2251 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2256 nt
= bytes_to_num(receivedAnswer
, 4);
2258 // Transmit reader nonce with fake par
2259 ReaderTransmitPar(mf_nr_ar
, sizeof(mf_nr_ar
), par
, NULL
);
2261 if (first_try
&& previous_nt
&& !nt_attacked
) { // we didn't calibrate our clock yet
2262 int nt_distance
= dist_nt(previous_nt
, nt
);
2263 if (nt_distance
== 0) {
2266 if (nt_distance
== -99999) { // invalid nonce received
2267 unexpected_random
++;
2268 if (unexpected_random
> MAX_UNEXPECTED_RANDOM
) {
2269 isOK
= -3; // Card has an unpredictable PRNG. Give up
2272 continue; // continue trying...
2275 if (++sync_tries
> MAX_SYNC_TRIES
) {
2276 if (strategy
> MAX_STRATEGY
|| MF_DBGLEVEL
< 3) {
2277 isOK
= -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2279 } else { // continue for a while, just to collect some debug info
2280 debug_info
[strategy
][debug_info_nr
] = nt_distance
;
2282 if (debug_info_nr
== NUM_DEBUG_INFOS
) {
2289 sync_cycles
= (sync_cycles
- nt_distance
/elapsed_prng_sequences
);
2290 if (sync_cycles
<= 0) {
2291 sync_cycles
+= PRNG_SEQUENCE_LENGTH
;
2293 if (MF_DBGLEVEL
>= 3) {
2294 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i
, nt_distance
, elapsed_prng_sequences
, sync_cycles
);
2300 if ((nt
!= nt_attacked
) && nt_attacked
) { // we somehow lost sync. Try to catch up again...
2301 catch_up_cycles
= -dist_nt(nt_attacked
, nt
);
2302 if (catch_up_cycles
== 99999) { // invalid nonce received. Don't resync on that one.
2303 catch_up_cycles
= 0;
2306 catch_up_cycles
/= elapsed_prng_sequences
;
2307 if (catch_up_cycles
== last_catch_up
) {
2308 consecutive_resyncs
++;
2311 last_catch_up
= catch_up_cycles
;
2312 consecutive_resyncs
= 0;
2314 if (consecutive_resyncs
< 3) {
2315 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i
, -catch_up_cycles
, consecutive_resyncs
);
2318 sync_cycles
= sync_cycles
+ catch_up_cycles
;
2319 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i
, -catch_up_cycles
, sync_cycles
);
2321 catch_up_cycles
= 0;
2322 consecutive_resyncs
= 0;
2327 consecutive_resyncs
= 0;
2329 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2330 if (ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2331 catch_up_cycles
= 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2334 par_low
= par
[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2338 if(led_on
) LED_B_ON(); else LED_B_OFF();
2340 par_list
[nt_diff
] = SwapBits(par
[0], 8);
2341 ks_list
[nt_diff
] = receivedAnswer
[0] ^ 0x05;
2343 // Test if the information is complete
2344 if (nt_diff
== 0x07) {
2349 nt_diff
= (nt_diff
+ 1) & 0x07;
2350 mf_nr_ar
[3] = (mf_nr_ar
[3] & 0x1F) | (nt_diff
<< 5);
2353 if (nt_diff
== 0 && first_try
)
2356 if (par
[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2361 par
[0] = ((par
[0] & 0x1F) + 1) | par_low
;
2367 mf_nr_ar
[3] &= 0x1F;
2370 if (MF_DBGLEVEL
>= 3) {
2371 for (uint16_t i
= 0; i
<= MAX_STRATEGY
; i
++) {
2372 for(uint16_t j
= 0; j
< NUM_DEBUG_INFOS
; j
++) {
2373 Dbprintf("collected debug info[%d][%d] = %d", i
, j
, debug_info
[i
][j
]);
2380 memcpy(buf
+ 0, uid
, 4);
2381 num_to_bytes(nt
, 4, buf
+ 4);
2382 memcpy(buf
+ 8, par_list
, 8);
2383 memcpy(buf
+ 16, ks_list
, 8);
2384 memcpy(buf
+ 24, mf_nr_ar
, 4);
2386 cmd_send(CMD_ACK
, isOK
, 0, 0, buf
, 28);
2389 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2396 //-----------------------------------------------------------------------------
2399 //-----------------------------------------------------------------------------
2400 void RAMFUNC
SniffMifare(uint8_t param
) {
2402 // bit 0 - trigger from first card answer
2403 // bit 1 - trigger from first reader 7-bit request
2405 // C(red) A(yellow) B(green)
2407 // init trace buffer
2411 // The command (reader -> tag) that we're receiving.
2412 // The length of a received command will in most cases be no more than 18 bytes.
2413 // So 32 should be enough!
2414 uint8_t receivedCmd
[MAX_MIFARE_FRAME_SIZE
];
2415 uint8_t receivedCmdPar
[MAX_MIFARE_PARITY_SIZE
];
2416 // The response (tag -> reader) that we're receiving.
2417 uint8_t receivedResponse
[MAX_MIFARE_FRAME_SIZE
];
2418 uint8_t receivedResponsePar
[MAX_MIFARE_PARITY_SIZE
];
2420 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
2422 // free eventually allocated BigBuf memory
2424 // allocate the DMA buffer, used to stream samples from the FPGA
2425 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
2426 uint8_t *data
= dmaBuf
;
2427 uint8_t previous_data
= 0;
2430 bool ReaderIsActive
= false;
2431 bool TagIsActive
= false;
2433 // Set up the demodulator for tag -> reader responses.
2434 DemodInit(receivedResponse
, receivedResponsePar
);
2436 // Set up the demodulator for the reader -> tag commands
2437 UartInit(receivedCmd
, receivedCmdPar
);
2439 // Setup for the DMA.
2440 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2447 // And now we loop, receiving samples.
2448 for(uint32_t sniffCounter
= 0; true; ) {
2450 if(BUTTON_PRESS()) {
2451 DbpString("cancelled by button");
2458 if ((sniffCounter
& 0x0000FFFF) == 0) { // from time to time
2459 // check if a transaction is completed (timeout after 2000ms).
2460 // if yes, stop the DMA transfer and send what we have so far to the client
2461 if (MfSniffSend(2000)) {
2462 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2466 ReaderIsActive
= false;
2467 TagIsActive
= false;
2468 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2472 int register readBufDataP
= data
- dmaBuf
; // number of bytes we have processed so far
2473 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
; // number of bytes already transferred
2474 if (readBufDataP
<= dmaBufDataP
){ // we are processing the same block of data which is currently being transferred
2475 dataLen
= dmaBufDataP
- readBufDataP
; // number of bytes still to be processed
2477 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
; // number of bytes still to be processed
2479 // test for length of buffer
2480 if(dataLen
> maxDataLen
) { // we are more behind than ever...
2481 maxDataLen
= dataLen
;
2482 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
2483 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen
);
2487 if(dataLen
< 1) continue;
2489 // primary buffer was stopped ( <-- we lost data!
2490 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
2491 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
2492 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
2493 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
2495 // secondary buffer sets as primary, secondary buffer was stopped
2496 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
2497 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
2498 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
2503 if (sniffCounter
& 0x01) {
2505 if(!TagIsActive
) { // no need to try decoding tag data if the reader is sending
2506 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
2507 if(MillerDecoding(readerdata
, (sniffCounter
-1)*4)) {
2509 if (MfSniffLogic(receivedCmd
, Uart
.len
, Uart
.parity
, Uart
.bitCount
, true)) break;
2511 /* And ready to receive another command. */
2512 UartInit(receivedCmd
, receivedCmdPar
);
2514 /* And also reset the demod code */
2517 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
2520 if(!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending
2521 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
2522 if(ManchesterDecoding(tagdata
, 0, (sniffCounter
-1)*4)) {
2525 if (MfSniffLogic(receivedResponse
, Demod
.len
, Demod
.parity
, Demod
.bitCount
, false)) break;
2527 // And ready to receive another response.
2529 // And reset the Miller decoder including its (now outdated) input buffer
2530 UartInit(receivedCmd
, receivedCmdPar
);
2532 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
2536 previous_data
= *data
;
2539 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
2545 DbpString("COMMAND FINISHED");
2547 FpgaDisableSscDma();
2550 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen
, Uart
.state
, Uart
.len
);