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FIX: lf hitag : Mea culpa, simulation should not have reader_field on. thanks to...
[proxmark3-svn] / armsrc / iso14443b.c
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to support ISO 14443B. This includes both the reader software and
9 // the `fake tag' modes.
10 //-----------------------------------------------------------------------------
11 #include "iso14443b.h"
12
13 #ifndef FWT_TIMEOUT_14B
14 // defaults to 2000ms
15 # define FWT_TIMEOUT_14B 35312
16 #endif
17 #ifndef ISO14443B_DMA_BUFFER_SIZE
18 # define ISO14443B_DMA_BUFFER_SIZE 256
19 #endif
20 #ifndef RECEIVE_MASK
21 # define RECEIVE_MASK (ISO14443B_DMA_BUFFER_SIZE-1)
22 #endif
23
24 // Guard Time (per 14443-2)
25 #ifndef TR0
26 # define TR0 0
27 #endif
28
29 // Synchronization time (per 14443-2)
30 #ifndef TR1
31 # define TR1 0
32 #endif
33 // Frame Delay Time PICC to PCD (per 14443-3 Amendment 1)
34 #ifndef TR2
35 # define TR2 0
36 #endif
37
38 // 4sample
39 #define SEND4STUFFBIT(x) ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);
40 //#define SEND4STUFFBIT(x) ToSendStuffBit(x);
41 // iceman, this threshold value, what makes 8 a good amplituted for this IQ values?
42 #ifndef SUBCARRIER_DETECT_THRESHOLD
43 # define SUBCARRIER_DETECT_THRESHOLD 8
44 #endif
45
46 static void iso14b_set_timeout(uint32_t timeout);
47 static void iso14b_set_maxframesize(uint16_t size);
48 static void switch_off(void);
49
50 // the block number for the ISO14443-4 PCB (used with APDUs)
51 static uint8_t pcb_blocknum = 0;
52 static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
53
54
55 //=============================================================================
56 // An ISO 14443 Type B tag. We listen for commands from the reader, using
57 // a UART kind of thing that's implemented in software. When we get a
58 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
59 // If it's good, then we can do something appropriate with it, and send
60 // a response.
61 //=============================================================================
62
63
64 //-----------------------------------------------------------------------------
65 // The software UART that receives commands from the reader, and its state variables.
66 //-----------------------------------------------------------------------------
67 static struct {
68 enum {
69 STATE_UNSYNCD,
70 STATE_GOT_FALLING_EDGE_OF_SOF,
71 STATE_AWAITING_START_BIT,
72 STATE_RECEIVING_DATA
73 } state;
74 uint16_t shiftReg;
75 int bitCnt;
76 int byteCnt;
77 int byteCntMax;
78 int posCnt;
79 uint8_t *output;
80 } Uart;
81
82 static void UartReset() {
83 Uart.state = STATE_UNSYNCD;
84 Uart.shiftReg = 0;
85 Uart.bitCnt = 0;
86 Uart.byteCnt = 0;
87 Uart.byteCntMax = MAX_FRAME_SIZE;
88 Uart.posCnt = 0;
89 }
90
91 static void UartInit(uint8_t *data) {
92 Uart.output = data;
93 UartReset();
94 // memset(Uart.output, 0x00, MAX_FRAME_SIZE);
95 }
96
97 //-----------------------------------------------------------------------------
98 // The software Demod that receives commands from the tag, and its state variables.
99 //-----------------------------------------------------------------------------
100 static struct {
101 enum {
102 DEMOD_UNSYNCD,
103 DEMOD_PHASE_REF_TRAINING,
104 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
105 DEMOD_GOT_FALLING_EDGE_OF_SOF,
106 DEMOD_AWAITING_START_BIT,
107 DEMOD_RECEIVING_DATA
108 } state;
109 uint16_t bitCount;
110 int posCount;
111 int thisBit;
112 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
113 int metric;
114 int metricN;
115 */
116 uint16_t shiftReg;
117 uint8_t *output;
118 uint16_t len;
119 int sumI;
120 int sumQ;
121 uint32_t startTime, endTime;
122 } Demod;
123
124 // Clear out the state of the "UART" that receives from the tag.
125 static void DemodReset() {
126 Demod.state = DEMOD_UNSYNCD;
127 Demod.bitCount = 0;
128 Demod.posCount = 0;
129 Demod.thisBit = 0;
130 Demod.shiftReg = 0;
131 Demod.len = 0;
132 Demod.sumI = 0;
133 Demod.sumQ = 0;
134 Demod.startTime = 0;
135 Demod.endTime = 0;
136 }
137
138 static void DemodInit(uint8_t *data) {
139 Demod.output = data;
140 DemodReset();
141 // memset(Demod.output, 0x00, MAX_FRAME_SIZE);
142 }
143
144
145 /*
146 * 9.4395 us = 1 ETU and clock is about 1.5 us
147 * 13560000Hz
148 * 1000ms/s
149 * timeout in ETUs (time to transfer 1 bit, 9.4395 us)
150 *
151 * Formula to calculate FWT (in ETUs) by timeout (in ms):
152 * fwt = 13560000 * 1000 / (8*16) * timeout;
153 * Sample: 3sec == 3000ms
154 * 13560000 * 1000 / (8*16) * 3000 ==
155 * 13560000000 / 384000 = 35312 FWT
156 * @param timeout is in frame wait time, fwt, measured in ETUs
157 */
158 static void iso14b_set_timeout(uint32_t timeout) {
159 #define MAX_TIMEOUT 40542464 // 13560000Hz * 1000ms / (2^32-1) * (8*16)
160 if(timeout > MAX_TIMEOUT)
161 timeout = MAX_TIMEOUT;
162
163 iso14b_timeout = timeout;
164 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443B Timeout set to %ld fwt", iso14b_timeout);
165 }
166 static void iso14b_set_maxframesize(uint16_t size) {
167 if (size > 256)
168 size = MAX_FRAME_SIZE;
169
170 Uart.byteCntMax = size;
171 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443B Max frame size set to %d bytes", Uart.byteCntMax);
172 }
173 static void switch_off(void){
174 if (MF_DBGLEVEL > 3) Dbprintf("switch_off");
175 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
176 SpinDelay(100);
177 FpgaDisableSscDma();
178 set_tracing(FALSE);
179 LEDsoff();
180 }
181
182 void AppendCrc14443b(uint8_t* data, int len) {
183 ComputeCrc14443(CRC_14443_B, data, len, data+len, data+len+1);
184 }
185
186 //-----------------------------------------------------------------------------
187 // Code up a string of octets at layer 2 (including CRC, we don't generate
188 // that here) so that they can be transmitted to the reader. Doesn't transmit
189 // them yet, just leaves them ready to send in ToSend[].
190 //-----------------------------------------------------------------------------
191 static void CodeIso14443bAsTag(const uint8_t *cmd, int len) {
192 /* ISO 14443 B
193 *
194 * Reader to card | ASK - Amplitude Shift Keying Modulation (PCD to PICC for Type B) (NRZ-L encodig)
195 * Card to reader | BPSK - Binary Phase Shift Keying Modulation, (PICC to PCD for Type B)
196 *
197 * fc - carrier frequency 13.56mHz
198 * TR0 - Guard Time per 14443-2
199 * TR1 - Synchronization Time per 14443-2
200 * TR2 - PICC to PCD Frame Delay Time (per 14443-3 Amendment 1)
201 *
202 * Elementary Time Unit (ETU) is
203 * - 128 Carrier Cycles (9.4395 µS) = 8 Subcarrier Units
204 * - 1 ETU = 1 bit
205 * - 10 ETU = 1 startbit, 8 databits, 1 stopbit (10bits length)
206 * - startbit is a 0
207 * - stopbit is a 1
208 *
209 * Start of frame (SOF) is
210 * - [10-11] ETU of ZEROS, unmodulated time
211 * - [2-3] ETU of ONES,
212 *
213 * End of frame (EOF) is
214 * - [10-11] ETU of ZEROS, unmodulated time
215 *
216 * -TO VERIFY THIS BELOW-
217 * The mode FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK which we use to simulate tag
218 * works like this:
219 * - A 1-bit input to the FPGA becomes 8 pulses at 847.5kHz (1.18µS / pulse) == 9.44us
220 * - A 0-bit input to the FPGA becomes an unmodulated time of 1.18µS or does it become 8 nonpulses for 9.44us
221 *
222 * FPGA doesn't seem to work with ETU. It seems to work with pulse / duration instead.
223 *
224 * Card sends data ub 847.e kHz subcarrier
225 * subcar |duration| FC division
226 * -------+--------+------------
227 * 106kHz | 9.44µS | FC/128
228 * 212kHz | 4.72µS | FC/64
229 * 424kHz | 2.36µS | FC/32
230 * 848kHz | 1.18µS | FC/16
231 * -------+--------+------------
232 *
233 * Reader data transmission:
234 * - no modulation ONES
235 * - SOF
236 * - Command, data and CRC_B
237 * - EOF
238 * - no modulation ONES
239 *
240 * Card data transmission
241 * - TR1
242 * - SOF
243 * - data (each bytes is: 1startbit, 8bits, 1stopbit)
244 * - CRC_B
245 * - EOF
246 *
247 * FPGA implementation :
248 * At this point only Type A is implemented. This means that we are using a
249 * bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
250 * things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
251 *
252 */
253
254 int i,j;
255 uint8_t b;
256
257 ToSendReset();
258
259 // Transmit a burst of ones, as the initial thing that lets the
260 // reader get phase sync.
261 // This loop is TR1, per specification
262 // TR1 minimum must be > 80/fs
263 // TR1 maximum 200/fs
264 // 80/fs < TR1 < 200/fs
265 // 10 ETU < TR1 < 24 ETU
266
267 // Send SOF.
268 // 10-11 ETU * 4times samples ZEROS
269 for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
270 //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
271
272 // 2-3 ETU * 4times samples ONES
273 for(i = 0; i < 3; i++) { SEND4STUFFBIT(1); }
274 //for(i = 0; i < 3; i++) { ToSendStuffBit(1); }
275
276 // data
277 for(i = 0; i < len; ++i) {
278
279 // Start bit
280 SEND4STUFFBIT(0);
281 //ToSendStuffBit(0);
282
283 // Data bits
284 b = cmd[i];
285 for(j = 0; j < 8; ++j) {
286 // if(b & 1) {
287 // SEND4STUFFBIT(1);
288 // //ToSendStuffBit(1);
289 // } else {
290 // SEND4STUFFBIT(0);
291 // //ToSendStuffBit(0);
292 // }
293 SEND4STUFFBIT( b & 1 );
294 b >>= 1;
295 }
296
297 // Stop bit
298 SEND4STUFFBIT(1);
299 //ToSendStuffBit(1);
300
301 // Extra Guard bit
302 // For PICC it ranges 0-18us (1etu = 9us)
303 SEND4STUFFBIT(1);
304 //ToSendStuffBit(1);
305 }
306
307 // Send EOF.
308 // 10-11 ETU * 4 sample rate = ZEROS
309 for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
310 //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
311
312 // why this?
313 for(i = 0; i < 40; i++) { SEND4STUFFBIT(1); }
314 //for(i = 0; i < 40; i++) { ToSendStuffBit(1); }
315
316 // Convert from last byte pos to length
317 ++ToSendMax;
318 }
319
320
321 /* Receive & handle a bit coming from the reader.
322 *
323 * This function is called 4 times per bit (every 2 subcarrier cycles).
324 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
325 *
326 * LED handling:
327 * LED A -> ON once we have received the SOF and are expecting the rest.
328 * LED A -> OFF once we have received EOF or are in error state or unsynced
329 *
330 * Returns: true if we received a EOF
331 * false if we are still waiting for some more
332 */
333 static RAMFUNC int Handle14443bReaderUartBit(uint8_t bit) {
334 switch (Uart.state) {
335 case STATE_UNSYNCD:
336 if (!bit) {
337 // we went low, so this could be the beginning of an SOF
338 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
339 Uart.posCnt = 0;
340 Uart.bitCnt = 0;
341 }
342 break;
343
344 case STATE_GOT_FALLING_EDGE_OF_SOF:
345 Uart.posCnt++;
346 if (Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
347 if (bit) {
348 if (Uart.bitCnt > 9) {
349 // we've seen enough consecutive
350 // zeros that it's a valid SOF
351 Uart.posCnt = 0;
352 Uart.byteCnt = 0;
353 Uart.state = STATE_AWAITING_START_BIT;
354 LED_A_ON(); // Indicate we got a valid SOF
355 } else {
356 // didn't stay down long enough before going high, error
357 Uart.state = STATE_UNSYNCD;
358 }
359 } else {
360 // do nothing, keep waiting
361 }
362 Uart.bitCnt++;
363 }
364 if (Uart.posCnt >= 4) Uart.posCnt = 0;
365 if (Uart.bitCnt > 12) {
366 // Give up if we see too many zeros without a one, too.
367 LED_A_OFF();
368 Uart.state = STATE_UNSYNCD;
369 }
370 break;
371
372 case STATE_AWAITING_START_BIT:
373 Uart.posCnt++;
374 if (bit) {
375 if (Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
376 // stayed high for too long between characters, error
377 Uart.state = STATE_UNSYNCD;
378 }
379 } else {
380 // falling edge, this starts the data byte
381 Uart.posCnt = 0;
382 Uart.bitCnt = 0;
383 Uart.shiftReg = 0;
384 Uart.state = STATE_RECEIVING_DATA;
385 }
386 break;
387
388 case STATE_RECEIVING_DATA:
389 Uart.posCnt++;
390 if (Uart.posCnt == 2) {
391 // time to sample a bit
392 Uart.shiftReg >>= 1;
393 if (bit) {
394 Uart.shiftReg |= 0x200;
395 }
396 Uart.bitCnt++;
397 }
398 if (Uart.posCnt >= 4) {
399 Uart.posCnt = 0;
400 }
401 if (Uart.bitCnt == 10) {
402 if ((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
403 {
404 // this is a data byte, with correct
405 // start and stop bits
406 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
407 Uart.byteCnt++;
408
409 if (Uart.byteCnt >= Uart.byteCntMax) {
410 // Buffer overflowed, give up
411 LED_A_OFF();
412 Uart.state = STATE_UNSYNCD;
413 } else {
414 // so get the next byte now
415 Uart.posCnt = 0;
416 Uart.state = STATE_AWAITING_START_BIT;
417 }
418 } else if (Uart.shiftReg == 0x000) {
419 // this is an EOF byte
420 LED_A_OFF(); // Finished receiving
421 Uart.state = STATE_UNSYNCD;
422 if (Uart.byteCnt != 0)
423 return TRUE;
424
425 } else {
426 // this is an error
427 LED_A_OFF();
428 Uart.state = STATE_UNSYNCD;
429 }
430 }
431 break;
432
433 default:
434 LED_A_OFF();
435 Uart.state = STATE_UNSYNCD;
436 break;
437 }
438 return FALSE;
439 }
440
441 //-----------------------------------------------------------------------------
442 // Receive a command (from the reader to us, where we are the simulated tag),
443 // and store it in the given buffer, up to the given maximum length. Keeps
444 // spinning, waiting for a well-framed command, until either we get one
445 // (returns TRUE) or someone presses the pushbutton on the board (FALSE).
446 //
447 // Assume that we're called with the SSC (to the FPGA) and ADC path set
448 // correctly.
449 //-----------------------------------------------------------------------------
450 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len) {
451 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
452 // only, since we are receiving, not transmitting).
453 // Signal field is off with the appropriate LED
454 LED_D_OFF();
455 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
456
457 StartCountSspClk();
458
459 volatile uint8_t b = 0;
460
461 // clear receiving shift register and holding register
462 // What does this loop do? Is it TR1?
463 for(uint8_t c = 0; c < 10;) {
464 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
465 AT91C_BASE_SSC->SSC_THR = 0xFF;
466 ++c;
467 }
468 }
469
470 // Now run a `software UART' on the stream of incoming samples.
471 UartInit(received);
472
473 uint8_t mask;
474 while( !BUTTON_PRESS() ) {
475 WDT_HIT();
476
477 if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) {
478 b = (uint8_t) AT91C_BASE_SSC->SSC_RHR;
479 for ( mask = 0x80; mask != 0; mask >>= 1) {
480 if ( Handle14443bReaderUartBit(b & mask)) {
481 *len = Uart.byteCnt;
482 return TRUE;
483 }
484 }
485 }
486 }
487 return FALSE;
488 }
489
490 void ClearFpgaShiftingRegisters(void){
491
492 volatile uint8_t b;
493
494 // clear receiving shift register and holding register
495 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
496
497 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
498
499 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
500
501 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
502
503 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
504 for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
505 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
506 if (AT91C_BASE_SSC->SSC_RHR) break;
507 }
508
509 // Clear TXRDY:
510 //AT91C_BASE_SSC->SSC_THR = 0xFF;
511 }
512
513 void WaitForFpgaDelayQueueIsEmpty( uint16_t delay ){
514 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
515 uint8_t fpga_queued_bits = delay >> 3; // twich /8 ?? >>3,
516 for (uint8_t i = 0; i <= fpga_queued_bits/8 + 1; ) {
517 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
518 AT91C_BASE_SSC->SSC_THR = 0xFF;
519 i++;
520 }
521 }
522 }
523
524 static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
525
526 volatile uint32_t b;
527
528 // Signal field is off with the appropriate LED
529 LED_D_OFF();
530 //uint16_t fpgasendQueueDelay = 0;
531
532 // Modulate BPSK
533 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
534 SpinDelay(40);
535
536 ClearFpgaShiftingRegisters();
537
538 FpgaSetupSsc();
539
540 // Transmit the response.
541 for(uint16_t i = 0; i < len;) {
542 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
543 AT91C_BASE_SSC->SSC_THR = response[++i];
544 }
545 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
546 b = AT91C_BASE_SSC->SSC_RHR;
547 (void)b;
548 }
549 }
550
551 //WaitForFpgaDelayQueueIsEmpty(fpgasendQueueDelay);
552 AT91C_BASE_SSC->SSC_THR = 0xFF;
553 }
554 //-----------------------------------------------------------------------------
555 // Main loop of simulated tag: receive commands from reader, decide what
556 // response to send, and send it.
557 //-----------------------------------------------------------------------------
558 void SimulateIso14443bTag(uint32_t pupi) {
559
560 ///////////// setup device.
561 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
562
563 // allocate command receive buffer
564 BigBuf_free();
565 BigBuf_Clear_ext(false);
566 clear_trace(); //sim
567 set_tracing(TRUE);
568
569 // connect Demodulated Signal to ADC:
570 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
571
572 // Set up the synchronous serial port
573 FpgaSetupSsc();
574 /////////////
575
576 uint16_t len, cmdsReceived = 0;
577 int cardSTATE = SIM_NOFIELD;
578 int vHf = 0; // in mV
579 // uint32_t time_0 = 0;
580 // uint32_t t2r_time = 0;
581 // uint32_t r2t_time = 0;
582 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
583
584 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
585 // static const uint8_t cmdWUPB[] = { ISO14443B_REQB, 0x00, 0x08, 0x39, 0x73 }; // WUPB
586 // ... and REQB, AFI=0, Normal Request, N=1:
587 // static const uint8_t cmdREQB[] = { ISO14443B_REQB, 0x00, 0x00, 0x71, 0xFF }; // REQB
588 // ... and ATTRIB
589 // static const uint8_t cmdATTRIB[] = { ISO14443B_ATTRIB, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
590
591 // ... if not PUPI/UID is supplied we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
592 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
593 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
594 uint8_t respATQB[] = { 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19,
595 0x22, 0x00, 0x21, 0x85, 0x5e, 0xd7 };
596
597 // response to HLTB and ATTRIB
598 static const uint8_t respOK[] = {0x00, 0x78, 0xF0};
599
600 // ...PUPI/UID supplied from user. Adjust ATQB response accordingly
601 if ( pupi > 0 ) {
602 uint8_t len = sizeof(respATQB);
603 num_to_bytes(pupi, 4, respATQB+1);
604 ComputeCrc14443(CRC_14443_B, respATQB, 12, &respATQB[len-2], &respATQB[len-1]);
605 }
606
607 // prepare "ATQB" tag answer (encoded):
608 CodeIso14443bAsTag(respATQB, sizeof(respATQB));
609 uint8_t *encodedATQB = BigBuf_malloc(ToSendMax);
610 uint16_t encodedATQBLen = ToSendMax;
611 memcpy(encodedATQB, ToSend, ToSendMax);
612
613
614 // prepare "OK" tag answer (encoded):
615 CodeIso14443bAsTag(respOK, sizeof(respOK));
616 uint8_t *encodedOK = BigBuf_malloc(ToSendMax);
617 uint16_t encodedOKLen = ToSendMax;
618 memcpy(encodedOK, ToSend, ToSendMax);
619
620 // Simulation loop
621 while (!BUTTON_PRESS() && !usb_poll_validate_length()) {
622 WDT_HIT();
623
624 // find reader field
625 if (cardSTATE == SIM_NOFIELD) {
626 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
627 if ( vHf > MF_MINFIELDV ) {
628 cardSTATE = SIM_IDLE;
629 LED_A_ON();
630 }
631 }
632 if (cardSTATE == SIM_NOFIELD) continue;
633
634 // Get reader command
635 if (!GetIso14443bCommandFromReader(receivedCmd, &len)) {
636 Dbprintf("button pressed, received %d commands", cmdsReceived);
637 break;
638 }
639
640 // ISO14443-B protocol states:
641 // REQ or WUP request in ANY state
642 // WUP in HALTED state
643 if (len == 5 ) {
644 if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE == SIM_HALTED) ||
645 receivedCmd[0] == ISO14443B_REQB ){
646 LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
647 cardSTATE = SIM_SELECTING;
648 }
649 }
650
651 /*
652 * How should this flow go?
653 * REQB or WUPB
654 * send response ( waiting for Attrib)
655 * ATTRIB
656 * send response ( waiting for commands 7816)
657 * HALT
658 send halt response ( waiting for wupb )
659 */
660
661 switch (cardSTATE) {
662 //case SIM_NOFIELD:
663 case SIM_HALTED:
664 case SIM_IDLE: {
665 LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
666 break;
667 }
668 case SIM_SELECTING: {
669 TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
670 LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
671 cardSTATE = SIM_WORK;
672 break;
673 }
674 case SIM_HALTING: {
675 TransmitFor14443b_AsTag( encodedOK, encodedOKLen );
676 LogTrace(respOK, sizeof(respOK), 0, 0, NULL, FALSE);
677 cardSTATE = SIM_HALTED;
678 break;
679 }
680 case SIM_ACKNOWLEDGE: {
681 TransmitFor14443b_AsTag( encodedOK, encodedOKLen );
682 LogTrace(respOK, sizeof(respOK), 0, 0, NULL, FALSE);
683 cardSTATE = SIM_IDLE;
684 break;
685 }
686 case SIM_WORK: {
687 if ( len == 7 && receivedCmd[0] == ISO14443B_HALT ) {
688 cardSTATE = SIM_HALTED;
689 } else if ( len == 11 && receivedCmd[0] == ISO14443B_ATTRIB ) {
690 cardSTATE = SIM_ACKNOWLEDGE;
691 } else {
692 // Todo:
693 // - SLOT MARKER
694 // - ISO7816
695 // - emulate with a memory dump
696 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsReceived);
697
698 // CRC Check
699 uint8_t b1, b2;
700 if (len >= 3){ // if crc exists
701 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
702 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1])
703 DbpString("+++CRC fail");
704 else
705 DbpString("CRC passes");
706 }
707 cardSTATE = SIM_IDLE;
708 }
709 break;
710 }
711 default: break;
712 }
713
714 ++cmdsReceived;
715 // iceman, could add a switch to turn this on/off (if off, no logging?)
716 if(cmdsReceived > 1000) {
717 DbpString("14B Simulate, 1000 commands later...");
718 break;
719 }
720 }
721 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
722 switch_off(); //simulate
723 }
724
725 //=============================================================================
726 // An ISO 14443 Type B reader. We take layer two commands, code them
727 // appropriately, and then send them to the tag. We then listen for the
728 // tag's response, which we leave in the buffer to be demodulated on the
729 // PC side.
730 //=============================================================================
731
732 /*
733 * Handles reception of a bit from the tag
734 *
735 * This function is called 2 times per bit (every 4 subcarrier cycles).
736 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
737 *
738 * LED handling:
739 * LED C -> ON once we have received the SOF and are expecting the rest.
740 * LED C -> OFF once we have received EOF or are unsynced
741 *
742 * Returns: true if we received a EOF
743 * false if we are still waiting for some more
744 *
745 */
746 static RAMFUNC int Handle14443bTagSamplesDemod(int ci, int cq) {
747 int v = 0, myI = ABS(ci), myQ = ABS(cq);
748
749 // The soft decision on the bit uses an estimate of just the
750 // quadrant of the reference angle, not the exact angle.
751 #define MAKE_SOFT_DECISION() { \
752 if(Demod.sumI > 0) { \
753 v = ci; \
754 } else { \
755 v = -ci; \
756 } \
757 if(Demod.sumQ > 0) { \
758 v += cq; \
759 } else { \
760 v -= cq; \
761 } \
762 }
763
764 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
765 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
766 #define CHECK_FOR_SUBCARRIER_old() { \
767 if(ci < 0) { \
768 if(cq < 0) { /* ci < 0, cq < 0 */ \
769 if (cq < ci) { \
770 v = -cq - (ci >> 1); \
771 } else { \
772 v = -ci - (cq >> 1); \
773 } \
774 } else { /* ci < 0, cq >= 0 */ \
775 if (cq < -ci) { \
776 v = -ci + (cq >> 1); \
777 } else { \
778 v = cq - (ci >> 1); \
779 } \
780 } \
781 } else { \
782 if(cq < 0) { /* ci >= 0, cq < 0 */ \
783 if (-cq < ci) { \
784 v = ci - (cq >> 1); \
785 } else { \
786 v = -cq + (ci >> 1); \
787 } \
788 } else { /* ci >= 0, cq >= 0 */ \
789 if (cq < ci) { \
790 v = ci + (cq >> 1); \
791 } else { \
792 v = cq + (ci >> 1); \
793 } \
794 } \
795 } \
796 }
797
798 //note: couldn't we just use MAX(ABS(ci),ABS(cq)) + (MIN(ABS(ci),ABS(cq))/2) from common.h - marshmellow
799 #define CHECK_FOR_SUBCARRIER() { \
800 v = MAX(myI, myQ) + (MIN(myI, myQ) >> 1); \
801 }
802
803 switch(Demod.state) {
804 case DEMOD_UNSYNCD:
805
806 CHECK_FOR_SUBCARRIER();
807
808 // subcarrier detected
809 if (v > SUBCARRIER_DETECT_THRESHOLD) {
810 Demod.state = DEMOD_PHASE_REF_TRAINING;
811 Demod.sumI = ci;
812 Demod.sumQ = cq;
813 Demod.posCount = 1;
814 }
815 break;
816
817 case DEMOD_PHASE_REF_TRAINING:
818 if (Demod.posCount < 8) {
819
820 CHECK_FOR_SUBCARRIER();
821
822 if (v > SUBCARRIER_DETECT_THRESHOLD) {
823 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
824 // note: synchronization time > 80 1/fs
825 Demod.sumI += ci;
826 Demod.sumQ += cq;
827 ++Demod.posCount;
828 } else {
829 // subcarrier lost
830 Demod.state = DEMOD_UNSYNCD;
831 }
832 } else {
833 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
834 }
835 break;
836
837 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
838
839 MAKE_SOFT_DECISION();
840
841 if (v < 0) { // logic '0' detected
842 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
843 Demod.posCount = 0; // start of SOF sequence
844 } else {
845 // maximum length of TR1 = 200 1/fs
846 if(Demod.posCount > 26*2) Demod.state = DEMOD_UNSYNCD;
847 }
848 ++Demod.posCount;
849 break;
850
851 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
852 ++Demod.posCount;
853
854 MAKE_SOFT_DECISION();
855
856 if (v > 0) {
857 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
858 if (Demod.posCount < 8*2) {
859 Demod.state = DEMOD_UNSYNCD;
860 } else {
861 LED_C_ON(); // Got SOF
862 //Demod.startTime = GetCountSspClk();
863 Demod.state = DEMOD_AWAITING_START_BIT;
864 Demod.posCount = 0;
865 Demod.len = 0;
866 }
867 } else {
868 // low phase of SOF too long (> 12 etu)
869 if (Demod.posCount > 14*2) {
870 Demod.state = DEMOD_UNSYNCD;
871 LED_C_OFF();
872 }
873 }
874 break;
875
876 case DEMOD_AWAITING_START_BIT:
877 ++Demod.posCount;
878
879 MAKE_SOFT_DECISION();
880
881 if (v > 0) {
882 if(Demod.posCount > 2*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
883 Demod.state = DEMOD_UNSYNCD;
884 LED_C_OFF();
885 }
886 } else { // start bit detected
887 Demod.bitCount = 0;
888 Demod.posCount = 1; // this was the first half
889 Demod.thisBit = v;
890 Demod.shiftReg = 0;
891 Demod.state = DEMOD_RECEIVING_DATA;
892 }
893 break;
894
895 case DEMOD_RECEIVING_DATA:
896
897 MAKE_SOFT_DECISION();
898
899 if (Demod.posCount == 0) {
900 // first half of bit
901 Demod.thisBit = v;
902 Demod.posCount = 1;
903 } else {
904 // second half of bit
905 Demod.thisBit += v;
906 Demod.shiftReg >>= 1;
907
908 // OR in a logic '1'
909 if (Demod.thisBit > 0) Demod.shiftReg |= 0x200;
910
911 ++Demod.bitCount;
912
913 // 1 start 8 data 1 stop = 10
914 if (Demod.bitCount == 10) {
915
916 uint16_t s = Demod.shiftReg;
917
918 // stop bit == '1', start bit == '0'
919 if ((s & 0x200) && (s & 0x001) == 0 ) {
920 // left shift to drop the startbit
921 Demod.output[Demod.len] = (s >> 1) & 0xFF;
922 ++Demod.len;
923 Demod.state = DEMOD_AWAITING_START_BIT;
924 } else {
925 // this one is a bit hard, either its a correc byte or its unsynced.
926 Demod.state = DEMOD_UNSYNCD;
927 //Demod.endTime = GetCountSspClk();
928 LED_C_OFF();
929
930 // This is EOF (start, stop and all data bits == '0'
931 if (s == 0) return TRUE;
932 }
933 }
934 Demod.posCount = 0;
935 }
936 break;
937
938 default:
939 Demod.state = DEMOD_UNSYNCD;
940 LED_C_OFF();
941 break;
942 }
943 return FALSE;
944 }
945
946
947 /*
948 * Demodulate the samples we received from the tag, also log to tracebuffer
949 * quiet: set to 'TRUE' to disable debug output
950 */
951 static void GetTagSamplesFor14443bDemod() {
952 bool gotFrame = FALSE, finished = FALSE;
953 int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
954 int ci = 0, cq = 0;
955 uint32_t time_0 = 0, time_stop = 0;
956
957 BigBuf_free();
958
959 // Set up the demodulator for tag -> reader responses.
960 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
961
962 // The DMA buffer, used to stream samples from the FPGA
963 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
964 int8_t *upTo = dmaBuf;
965
966 // Setup and start DMA.
967 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE) ){
968 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
969 return;
970 }
971
972 // And put the FPGA in the appropriate mode
973 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
974
975 // get current clock
976 time_0 = GetCountSspClk();
977
978 // rx counter - dma counter? (how much?) & (mod) mask > 2. (since 2bytes at the time is read)
979 while ( !finished ) {
980
981 LED_A_INV();
982 WDT_HIT();
983
984 // LSB is a fpga signal bit.
985 ci = upTo[0] >> 1;
986 cq = upTo[1] >> 1;
987 upTo += 2;
988 lastRxCounter -= 2;
989
990 // restart DMA buffer to receive again.
991 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
992 upTo = dmaBuf;
993 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
994 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
995 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
996 }
997
998 // https://github.com/Proxmark/proxmark3/issues/103
999 gotFrame = Handle14443bTagSamplesDemod(ci, cq);
1000 time_stop = GetCountSspClk() - time_0;
1001
1002 finished = (time_stop > iso14b_timeout || gotFrame);
1003 }
1004
1005 FpgaDisableSscDma();
1006
1007 if ( upTo ) upTo = NULL;
1008
1009 if (MF_DBGLEVEL >= 3) {
1010 Dbprintf("Demod.state = %d, Demod.len = %u, PDC_RCR = %u",
1011 Demod.state,
1012 Demod.len,
1013 AT91C_BASE_PDC_SSC->PDC_RCR
1014 );
1015 }
1016
1017 // print the last batch of IQ values from FPGA
1018 if (MF_DBGLEVEL == 4)
1019 Dbhexdump(ISO14443B_DMA_BUFFER_SIZE, (uint8_t *)dmaBuf, FALSE);
1020
1021 if ( Demod.len > 0 )
1022 LogTrace(Demod.output, Demod.len, time_0, time_stop, NULL, FALSE);
1023 }
1024
1025
1026 //-----------------------------------------------------------------------------
1027 // Transmit the command (to the tag) that was placed in ToSend[].
1028 //-----------------------------------------------------------------------------
1029 static void TransmitFor14443b_AsReader(void) {
1030
1031 // we could been in following mode:
1032 // FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ
1033 // if its second call or more
1034
1035 // while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1036 // AT91C_BASE_SSC->SSC_THR = 0XFF;
1037 // }
1038
1039 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1040 SpinDelay(40);
1041
1042 int c;
1043 volatile uint32_t b;
1044
1045 // What does this loop do? Is it TR1?
1046 // 0xFF = 8 bits of 1. 1 bit == 1Etu,..
1047 // loop 10 * 8 = 80 ETU of delay, with a non modulated signal. why?
1048 // 80*9 = 720us.
1049 for(c = 0; c < 50;) {
1050 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1051 AT91C_BASE_SSC->SSC_THR = 0xFF;
1052 ++c;
1053 }
1054 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1055 b = AT91C_BASE_SSC->SSC_RHR;
1056 (void)b;
1057 }
1058 }
1059
1060 // Send frame loop
1061 for(c = 0; c < ToSendMax;) {
1062 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1063 AT91C_BASE_SSC->SSC_THR = ToSend[c++];
1064 }
1065 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1066 b = AT91C_BASE_SSC->SSC_RHR;
1067 (void)b;
1068 }
1069 }
1070 //WaitForFpgaDelayQueueIsEmpty(delay);
1071 // We should wait here for the FPGA to send all bits.
1072 WDT_HIT();
1073 }
1074
1075 //-----------------------------------------------------------------------------
1076 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1077 // so that it is ready to transmit to the tag using TransmitFor14443b().
1078 //-----------------------------------------------------------------------------
1079 static void CodeIso14443bAsReader(const uint8_t *cmd, int len) {
1080 /*
1081 * Reader data transmission:
1082 * - no modulation ONES
1083 * - SOF
1084 * - Command, data and CRC_B
1085 * - EOF
1086 * - no modulation ONES
1087 *
1088 * 1 ETU == 1 BIT!
1089 * TR0 - 8 ETUS minimum.
1090 *
1091 * QUESTION: how long is a 1 or 0 in pulses in the xcorr_848 mode?
1092 * 1 "stuffbit" = 1ETU (9us)
1093 */
1094 int i;
1095 uint8_t b;
1096
1097 ToSendReset();
1098
1099 // Send SOF
1100 // 10-11 ETUs of ZERO
1101 for(i = 0; i < 10; ++i) ToSendStuffBit(0);
1102
1103 // 2-3 ETUs of ONE
1104 ToSendStuffBit(1);
1105 ToSendStuffBit(1);
1106 ToSendStuffBit(1);
1107
1108 // Sending cmd, LSB
1109 // from here we add BITS
1110 for(i = 0; i < len; ++i) {
1111 // Start bit
1112 ToSendStuffBit(0);
1113 // Data bits
1114 b = cmd[i];
1115 // if ( b & 1 ) ToSendStuffBit(1); else ToSendStuffBit(0);
1116 // if ( (b>>1) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1117 // if ( (b>>2) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1118 // if ( (b>>3) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1119 // if ( (b>>4) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1120 // if ( (b>>5) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1121 // if ( (b>>6) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1122 // if ( (b>>7) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
1123
1124 ToSendStuffBit( b & 1);
1125 ToSendStuffBit( (b>>1) & 1);
1126 ToSendStuffBit( (b>>2) & 1);
1127 ToSendStuffBit( (b>>3) & 1);
1128 ToSendStuffBit( (b>>4) & 1);
1129 ToSendStuffBit( (b>>5) & 1);
1130 ToSendStuffBit( (b>>6) & 1);
1131 ToSendStuffBit( (b>>7) & 1);
1132
1133 // Stop bit
1134 ToSendStuffBit(1);
1135 // EGT extra guard time
1136 // For PCD it ranges 0-57us (1etu = 9us)
1137 ToSendStuffBit(1);
1138 ToSendStuffBit(1);
1139 ToSendStuffBit(1);
1140 }
1141
1142 // Send EOF
1143 // 10-11 ETUs of ZERO
1144 for(i = 0; i < 10; ++i) ToSendStuffBit(0);
1145
1146 // Transition time. TR0 - guard time
1147 // 8ETUS minum?
1148 // Per specification, Subcarrier must be stopped no later than 2 ETUs after EOF.
1149 // I'm guessing this is for the FPGA to be able to send all bits before we switch to listening mode
1150 for(i = 0; i < 32 ; ++i) ToSendStuffBit(1);
1151
1152 // TR1 - Synchronization time
1153 // Convert from last character reference to length
1154 ++ToSendMax;
1155 }
1156
1157
1158 /*
1159 * Convenience function to encode, transmit and trace iso 14443b comms
1160 */
1161 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len) {
1162
1163 uint32_t time_start = GetCountSspClk();
1164
1165 CodeIso14443bAsReader(cmd, len);
1166
1167 TransmitFor14443b_AsReader();
1168
1169 if(trigger) LED_A_ON();
1170
1171 LogTrace(cmd, len, time_start, GetCountSspClk()-time_start, NULL, TRUE);
1172 }
1173
1174 /* Sends an APDU to the tag
1175 * TODO: check CRC and preamble
1176 */
1177 uint8_t iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
1178 {
1179 uint8_t crc[2] = {0x00, 0x00};
1180 uint8_t message_frame[message_length + 4];
1181 // PCB
1182 message_frame[0] = 0x0A | pcb_blocknum;
1183 pcb_blocknum ^= 1;
1184 // CID
1185 message_frame[1] = 0;
1186 // INF
1187 memcpy(message_frame + 2, message, message_length);
1188 // EDC (CRC)
1189 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
1190 // send
1191 CodeAndTransmit14443bAsReader(message_frame, message_length + 4); //no
1192 // get response
1193 GetTagSamplesFor14443bDemod(); //no
1194 if(Demod.len < 3)
1195 return 0;
1196
1197 // VALIDATE CRC
1198 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1199 if ( crc[0] != Demod.output[Demod.len-2] || crc[1] != Demod.output[Demod.len-1] )
1200 return 0;
1201
1202 // copy response contents
1203 if(response != NULL)
1204 memcpy(response, Demod.output, Demod.len);
1205
1206 return Demod.len;
1207 }
1208
1209 /**
1210 * SRx Initialise.
1211 */
1212 uint8_t iso14443b_select_srx_card(iso14b_card_select_t *card )
1213 {
1214 // INITIATE command: wake up the tag using the INITIATE
1215 static const uint8_t init_srx[] = { ISO14443B_INITIATE, 0x00, 0x97, 0x5b };
1216 // SELECT command (with space for CRC)
1217 uint8_t select_srx[] = { ISO14443B_SELECT, 0x00, 0x00, 0x00};
1218 // temp to calc crc.
1219 uint8_t crc[2] = {0x00, 0x00};
1220
1221 CodeAndTransmit14443bAsReader(init_srx, sizeof(init_srx));
1222 GetTagSamplesFor14443bDemod(); //no
1223
1224 if (Demod.len == 0) return 2;
1225
1226 // Randomly generated Chip ID
1227 if (card) card->chipid = Demod.output[0];
1228
1229 select_srx[1] = Demod.output[0];
1230
1231 ComputeCrc14443(CRC_14443_B, select_srx, 2, &select_srx[2], &select_srx[3]);
1232 CodeAndTransmit14443bAsReader(select_srx, sizeof(select_srx));
1233 GetTagSamplesFor14443bDemod(); //no
1234
1235 if (Demod.len != 3) return 2;
1236
1237 // Check the CRC of the answer:
1238 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2 , &crc[0], &crc[1]);
1239 if(crc[0] != Demod.output[1] || crc[1] != Demod.output[2]) return 3;
1240
1241 // Check response from the tag: should be the same UID as the command we just sent:
1242 if (select_srx[1] != Demod.output[0]) return 1;
1243
1244 // First get the tag's UID:
1245 select_srx[0] = ISO14443B_GET_UID;
1246
1247 ComputeCrc14443(CRC_14443_B, select_srx, 1 , &select_srx[1], &select_srx[2]);
1248 CodeAndTransmit14443bAsReader(select_srx, 3); // Only first three bytes for this one
1249 GetTagSamplesFor14443bDemod(); //no
1250
1251 if (Demod.len != 10) return 2;
1252
1253 // The check the CRC of the answer
1254 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1255 if(crc[0] != Demod.output[8] || crc[1] != Demod.output[9]) return 3;
1256
1257 if (card) {
1258 card->uidlen = 8;
1259 memcpy(card->uid, Demod.output, 8);
1260 }
1261
1262 return 0;
1263 }
1264 /* Perform the ISO 14443 B Card Selection procedure
1265 * Currently does NOT do any collision handling.
1266 * It expects 0-1 cards in the device's range.
1267 * TODO: Support multiple cards (perform anticollision)
1268 * TODO: Verify CRC checksums
1269 */
1270 uint8_t iso14443b_select_card(iso14b_card_select_t *card )
1271 {
1272 // WUPB command (including CRC)
1273 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
1274 static const uint8_t wupb[] = { ISO14443B_REQB, 0x00, 0x08, 0x39, 0x73 };
1275 // ATTRIB command (with space for CRC)
1276 uint8_t attrib[] = { ISO14443B_ATTRIB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
1277
1278 // temp to calc crc.
1279 uint8_t crc[2] = {0x00, 0x00};
1280
1281 // first, wake up the tag
1282 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
1283 GetTagSamplesFor14443bDemod(); //select_card
1284
1285 // ATQB too short?
1286 if (Demod.len < 14) return 2;
1287
1288 // VALIDATE CRC
1289 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1290 if ( crc[0] != Demod.output[12] || crc[1] != Demod.output[13] )
1291 return 3;
1292
1293 if (card) {
1294 card->uidlen = 4;
1295 memcpy(card->uid, Demod.output+1, 4);
1296 memcpy(card->atqb, Demod.output+5, 7);
1297 }
1298
1299 // copy the PUPI to ATTRIB ( PUPI == UID )
1300 memcpy(attrib + 1, Demod.output + 1, 4);
1301
1302 // copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into ATTRIB (Param 3)
1303 attrib[7] = Demod.output[10] & 0x0F;
1304 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
1305
1306 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
1307 GetTagSamplesFor14443bDemod();//select_card
1308
1309 // Answer to ATTRIB too short?
1310 if(Demod.len < 3) return 2;
1311
1312 // VALIDATE CRC
1313 ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
1314 if ( crc[0] != Demod.output[1] || crc[1] != Demod.output[2] )
1315 return 3;
1316
1317 if (card) {
1318
1319 // CID
1320 card->cid = Demod.output[0];
1321
1322 // MAX FRAME
1323 uint16_t maxFrame = card->atqb[5] >> 4;
1324 if (maxFrame < 5) maxFrame = 8 * maxFrame + 16;
1325 else if (maxFrame == 5) maxFrame = 64;
1326 else if (maxFrame == 6) maxFrame = 96;
1327 else if (maxFrame == 7) maxFrame = 128;
1328 else if (maxFrame == 8) maxFrame = 256;
1329 else maxFrame = 257;
1330 iso14b_set_maxframesize(maxFrame);
1331
1332 // FWT
1333 uint8_t fwt = card->atqb[6] >> 4;
1334 if ( fwt < 16 ){
1335 uint32_t fwt_time = (302 << fwt);
1336 iso14b_set_timeout( fwt_time);
1337 }
1338 }
1339 // reset PCB block number
1340 pcb_blocknum = 0;
1341 return 0;
1342 }
1343
1344 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
1345 // field is setup for "Sending as Reader"
1346 void iso14443b_setup() {
1347 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup Enter");
1348 LEDsoff();
1349 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1350 //BigBuf_free();
1351 //BigBuf_Clear_ext(false);
1352
1353 // Initialize Demod and Uart structs
1354 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1355 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1356
1357 // connect Demodulated Signal to ADC:
1358 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1359
1360 // Set up the synchronous serial port
1361 FpgaSetupSsc();
1362
1363 // Signal field is on with the appropriate LED
1364 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1365 SpinDelay(100);
1366
1367 // Start the timer
1368 StartCountSspClk();
1369
1370 LED_D_ON();
1371 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup Exit");
1372 }
1373
1374 //-----------------------------------------------------------------------------
1375 // Read a SRI512 ISO 14443B tag.
1376 //
1377 // SRI512 tags are just simple memory tags, here we're looking at making a dump
1378 // of the contents of the memory. No anticollision algorithm is done, we assume
1379 // we have a single tag in the field.
1380 //
1381 // I tried to be systematic and check every answer of the tag, every CRC, etc...
1382 //-----------------------------------------------------------------------------
1383 void ReadSTMemoryIso14443b(uint8_t numofblocks)
1384 {
1385 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1386
1387 // Make sure that we start from off, since the tags are stateful;
1388 // confusing things will happen if we don't reset them between reads.
1389 switch_off(); // before ReadStMemory
1390
1391 set_tracing(TRUE);
1392
1393 uint8_t i = 0x00;
1394
1395 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1396 FpgaSetupSsc();
1397
1398 // Now give it time to spin up.
1399 // Signal field is on with the appropriate LED
1400 LED_D_ON();
1401 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
1402 SpinDelay(20);
1403
1404 // First command: wake up the tag using the INITIATE command
1405 uint8_t cmd1[] = {ISO14443B_INITIATE, 0x00, 0x97, 0x5b};
1406 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1)); //no
1407 GetTagSamplesFor14443bDemod(); // no
1408
1409 if (Demod.len == 0) {
1410 DbpString("No response from tag");
1411 set_tracing(FALSE);
1412 return;
1413 } else {
1414 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1415 Demod.output[0], Demod.output[1], Demod.output[2]);
1416 }
1417
1418 // There is a response, SELECT the uid
1419 DbpString("Now SELECT tag:");
1420 cmd1[0] = ISO14443B_SELECT; // 0x0E is SELECT
1421 cmd1[1] = Demod.output[0];
1422 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1423 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1)); //no
1424 GetTagSamplesFor14443bDemod(); //no
1425 if (Demod.len != 3) {
1426 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1427 set_tracing(FALSE);
1428 return;
1429 }
1430 // Check the CRC of the answer:
1431 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1432 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1433 DbpString("CRC Error reading select response.");
1434 set_tracing(FALSE);
1435 return;
1436 }
1437 // Check response from the tag: should be the same UID as the command we just sent:
1438 if (cmd1[1] != Demod.output[0]) {
1439 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1440 set_tracing(FALSE);
1441 return;
1442 }
1443
1444 // Tag is now selected,
1445 // First get the tag's UID:
1446 cmd1[0] = ISO14443B_GET_UID;
1447 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1448 CodeAndTransmit14443bAsReader(cmd1, 3); // no -- Only first three bytes for this one
1449 GetTagSamplesFor14443bDemod(); //no
1450 if (Demod.len != 10) {
1451 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1452 set_tracing(FALSE);
1453 return;
1454 }
1455 // The check the CRC of the answer (use cmd1 as temporary variable):
1456 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1457 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1458 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1459 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1460 // Do not return;, let's go on... (we should retry, maybe ?)
1461 }
1462 Dbprintf("Tag UID (64 bits): %08x %08x",
1463 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1464 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1465
1466 // Now loop to read all 16 blocks, address from 0 to last block
1467 Dbprintf("Tag memory dump, block 0 to %d", numofblocks);
1468 cmd1[0] = 0x08;
1469 i = 0x00;
1470 ++numofblocks;
1471
1472 for (;;) {
1473 if (i == numofblocks) {
1474 DbpString("System area block (0xff):");
1475 i = 0xff;
1476 }
1477 cmd1[1] = i;
1478 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1479 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1)); //no
1480 GetTagSamplesFor14443bDemod(); //no
1481
1482 if (Demod.len != 6) { // Check if we got an answer from the tag
1483 DbpString("Expected 6 bytes from tag, got less...");
1484 return;
1485 }
1486 // The check the CRC of the answer (use cmd1 as temporary variable):
1487 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1488 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1489 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1490 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1491 // Do not return;, let's go on... (we should retry, maybe ?)
1492 }
1493 // Now print out the memory location:
1494 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1495 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1496 (Demod.output[4]<<8)+Demod.output[5]);
1497
1498 if (i == 0xff) break;
1499 ++i;
1500 }
1501
1502 set_tracing(FALSE);
1503 }
1504
1505
1506 static void iso1444b_setup_snoop(void){
1507 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup_snoop Enter");
1508 LEDsoff();
1509 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1510 BigBuf_free();
1511 BigBuf_Clear_ext(false);
1512 clear_trace();//setup snoop
1513 set_tracing(TRUE);
1514
1515 // Initialize Demod and Uart structs
1516 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1517 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1518
1519 if (MF_DBGLEVEL > 1) {
1520 // Print debug information about the buffer sizes
1521 Dbprintf("Snooping buffers initialized:");
1522 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1523 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1524 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1525 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1526 }
1527
1528 // connect Demodulated Signal to ADC:
1529 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1530
1531 // Setup for the DMA.
1532 FpgaSetupSsc();
1533
1534 // Set FPGA in the appropriate mode
1535 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1536 SpinDelay(20);
1537
1538 // Start the SSP timer
1539 StartCountSspClk();
1540 if (MF_DBGLEVEL > 3) Dbprintf("iso1443b_setup_snoop Exit");
1541 }
1542
1543 //=============================================================================
1544 // Finally, the `sniffer' combines elements from both the reader and
1545 // simulated tag, to show both sides of the conversation.
1546 //=============================================================================
1547
1548 //-----------------------------------------------------------------------------
1549 // Record the sequence of commands sent by the reader to the tag, with
1550 // triggering so that we start recording at the point that the tag is moved
1551 // near the reader.
1552 //-----------------------------------------------------------------------------
1553 /*
1554 * Memory usage for this function, (within BigBuf)
1555 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1556 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1557 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1558 * Demodulated samples received - all the rest
1559 */
1560 void RAMFUNC SnoopIso14443b(void) {
1561
1562 uint32_t time_0 = 0, time_start = 0, time_stop = 0;
1563 int ci = 0, cq = 0;
1564 int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1565
1566 // We won't start recording the frames that we acquire until we trigger;
1567 // a good trigger condition to get started is probably when we see a
1568 // response from the tag.
1569 bool triggered = TRUE; // TODO: set and evaluate trigger condition
1570 bool TagIsActive = FALSE;
1571 bool ReaderIsActive = FALSE;
1572
1573 iso1444b_setup_snoop();
1574
1575 // The DMA buffer, used to stream samples from the FPGA
1576 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
1577 int8_t *upTo = dmaBuf;
1578
1579 // Setup and start DMA.
1580 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE) ){
1581 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1582 BigBuf_free();
1583 return;
1584 }
1585
1586 time_0 = GetCountSspClk();
1587
1588 // And now we loop, receiving samples.
1589 for(;;) {
1590
1591 WDT_HIT();
1592
1593 ci = upTo[0];
1594 cq = upTo[1];
1595 upTo += 2;
1596 lastRxCounter -= 2;
1597
1598 if (upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
1599 upTo = dmaBuf;
1600 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1601 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
1602 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
1603
1604 if (!tracing) {
1605 if (MF_DBGLEVEL >= 2) DbpString("Trace full");
1606 break;
1607 }
1608
1609 if (BUTTON_PRESS()) {
1610 if (MF_DBGLEVEL >= 2) DbpString("cancelled");
1611 break;
1612 }
1613 }
1614
1615 if (!TagIsActive) {
1616
1617 LED_A_ON();
1618
1619 // no need to try decoding reader data if the tag is sending
1620 if (Handle14443bReaderUartBit(ci & 0x01)) {
1621
1622 time_stop = GetCountSspClk() - time_0;
1623
1624 if (triggered)
1625 LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
1626
1627 /* And ready to receive another command. */
1628 UartReset();
1629 /* And also reset the demod code, which might have been */
1630 /* false-triggered by the commands from the reader. */
1631 DemodReset();
1632 } else {
1633 time_start = GetCountSspClk() - time_0;
1634 }
1635
1636 if (Handle14443bReaderUartBit(cq & 0x01)) {
1637
1638 time_stop = GetCountSspClk() - time_0;
1639
1640 if (triggered)
1641 LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
1642
1643 /* And ready to receive another command. */
1644 UartReset();
1645 /* And also reset the demod code, which might have been */
1646 /* false-triggered by the commands from the reader. */
1647 DemodReset();
1648 } else {
1649 time_start = GetCountSspClk() - time_0;
1650 }
1651 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1652 LED_A_OFF();
1653 }
1654
1655 if (!ReaderIsActive) {
1656 // no need to try decoding tag data if the reader is sending - and we cannot afford the time
1657 // is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
1658 // LSB is a fpga signal bit.
1659 if (Handle14443bTagSamplesDemod(ci >> 1, cq >> 1)) {
1660
1661 time_stop = GetCountSspClk() - time_0;
1662
1663 LogTrace(Demod.output, Demod.len, time_start, time_stop, NULL, FALSE);
1664
1665 triggered = TRUE;
1666
1667 // And ready to receive another response.
1668 DemodReset();
1669 } else {
1670 time_start = GetCountSspClk() - time_0;
1671 }
1672 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1673 }
1674 }
1675
1676 switch_off(); // Snoop
1677
1678 DbpString("Snoop statistics:");
1679 Dbprintf(" Uart State: %x ByteCount: %i ByteCountMax: %i", Uart.state, Uart.byteCnt, Uart.byteCntMax);
1680 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1681
1682 // free mem refs.
1683 if ( upTo ) upTo = NULL;
1684
1685 // Uart.byteCntMax should be set with ATQB value..
1686 }
1687
1688 void iso14b_set_trigger(bool enable) {
1689 trigger = enable;
1690 }
1691
1692 /*
1693 * Send raw command to tag ISO14443B
1694 * @Input
1695 * param flags enum ISO14B_COMMAND. (mifare.h)
1696 * len len of buffer data
1697 * data buffer with bytes to send
1698 *
1699 * @Output
1700 * none
1701 *
1702 */
1703 void SendRawCommand14443B_Ex(UsbCommand *c)
1704 {
1705 iso14b_command_t param = c->arg[0];
1706 size_t len = c->arg[1] & 0xffff;
1707 uint8_t *cmd = c->d.asBytes;
1708 uint8_t status = 0;
1709 uint32_t sendlen = sizeof(iso14b_card_select_t);
1710 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
1711
1712 if (MF_DBGLEVEL > 3) Dbprintf("14b raw: param, %04x", param );
1713
1714 // turn on trigger (LED_A)
1715 if ((param & ISO14B_REQUEST_TRIGGER) == ISO14B_REQUEST_TRIGGER)
1716 iso14b_set_trigger(TRUE);
1717
1718 if ((param & ISO14B_CONNECT) == ISO14B_CONNECT) {
1719 // Make sure that we start from off, since the tags are stateful;
1720 // confusing things will happen if we don't reset them between reads.
1721 //switch_off(); // before connect in raw
1722 iso14443b_setup();
1723 }
1724
1725 set_tracing(TRUE);
1726
1727 if ((param & ISO14B_SELECT_STD) == ISO14B_SELECT_STD) {
1728 iso14b_card_select_t *card = (iso14b_card_select_t*)buf;
1729 status = iso14443b_select_card(card);
1730 cmd_send(CMD_ACK, status, sendlen, 0, buf, sendlen);
1731 // 0: OK 2: attrib fail, 3:crc fail,
1732 if ( status > 0 ) return;
1733 }
1734
1735 if ((param & ISO14B_SELECT_SR) == ISO14B_SELECT_SR) {
1736 iso14b_card_select_t *card = (iso14b_card_select_t*)buf;
1737 status = iso14443b_select_srx_card(card);
1738 cmd_send(CMD_ACK, status, sendlen, 0, buf, sendlen);
1739 // 0: OK 2: attrib fail, 3:crc fail,
1740 if ( status > 0 ) return;
1741 }
1742
1743 if ((param & ISO14B_APDU) == ISO14B_APDU) {
1744 status = iso14443b_apdu(cmd, len, buf);
1745 cmd_send(CMD_ACK, status, status, 0, buf, status);
1746 }
1747
1748 if ((param & ISO14B_RAW) == ISO14B_RAW) {
1749 if((param & ISO14B_APPEND_CRC) == ISO14B_APPEND_CRC) {
1750 AppendCrc14443b(cmd, len);
1751 len += 2;
1752 }
1753
1754 CodeAndTransmit14443bAsReader(cmd, len); // raw
1755 GetTagSamplesFor14443bDemod(); // raw
1756
1757 sendlen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1758 status = (Demod.len > 0) ? 0 : 1;
1759 cmd_send(CMD_ACK, status, sendlen, 0, Demod.output, sendlen);
1760 }
1761
1762 // turn off trigger (LED_A)
1763 if ((param & ISO14B_REQUEST_TRIGGER) == ISO14B_REQUEST_TRIGGER)
1764 iso14b_set_trigger(FALSE);
1765
1766 // turn off antenna et al
1767 // we don't send a HALT command.
1768 if ((param & ISO14B_DISCONNECT) == ISO14B_DISCONNECT) {
1769 if (MF_DBGLEVEL > 3) Dbprintf("disconnect");
1770 switch_off(); // disconnect raw
1771 } else {
1772 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1773 }
1774
1775 }
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