]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
CHG: mental note to self, capslock is bad.
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 #ifndef SHORT_COIL
23 # define SHORT_COIL() LOW(GPIO_SSC_DOUT)
24 #endif
25 #ifndef OPEN_COIL
26 # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
27 #endif
28
29 /**
30 * Function to do a modulation and then get samples.
31 * @param delay_off
32 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
33 * @param useHighFreg
34 * @param command
35 */
36 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
37 {
38 /* Make sure the tag is reset */
39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
41 SpinDelay(200);
42
43 uint16_t period_0 = periods >> 16;
44 uint16_t period_1 = periods & 0xFFFF;
45
46 // 95 == 125 KHz 88 == 124.8 KHz
47 int divisor_used = (useHighFreq) ? 88 : 95;
48 sample_config sc = { 0,0,1, divisor_used, 0};
49 setSamplingConfig(&sc);
50
51 //clear read buffer
52 BigBuf_Clear_keep_EM();
53
54 LFSetupFPGAForADC(sc.divisor, 1);
55
56 // And a little more time for the tag to fully power up
57 SpinDelay(50);
58
59 // now modulate the reader field
60 while(*command != '\0' && *command != ' ') {
61 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
62 LED_D_OFF();
63 WaitUS(delay_off);
64 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
65
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
67 LED_D_ON();
68 if(*(command++) == '0')
69 WaitUS(period_0);
70 else
71 WaitUS(period_1);
72 }
73 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
74 LED_D_OFF();
75 WaitUS(delay_off);
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
78
79 // now do the read
80 DoAcquisition_config(false);
81 }
82
83 /* blank r/w tag data stream
84 ...0000000000000000 01111111
85 1010101010101010101010101010101010101010101010101010101010101010
86 0011010010100001
87 01111111
88 101010101010101[0]000...
89
90 [5555fe852c5555555555555555fe0000]
91 */
92 void ReadTItag(void)
93 {
94 StartTicks();
95 // some hardcoded initial params
96 // when we read a TI tag we sample the zerocross line at 2Mhz
97 // TI tags modulate a 1 as 16 cycles of 123.2Khz
98 // TI tags modulate a 0 as 16 cycles of 134.2Khz
99 #define FSAMPLE 2000000
100 #define FREQLO 123200
101 #define FREQHI 134200
102
103 signed char *dest = (signed char *)BigBuf_get_addr();
104 uint16_t n = BigBuf_max_traceLen();
105 // 128 bit shift register [shift3:shift2:shift1:shift0]
106 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
107
108 int i, cycles=0, samples=0;
109 // how many sample points fit in 16 cycles of each frequency
110 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
111 // when to tell if we're close enough to one freq or another
112 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
113
114 // TI tags charge at 134.2Khz
115 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
117
118 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
119 // connects to SSP_DIN and the SSP_DOUT logic level controls
120 // whether we're modulating the antenna (high)
121 // or listening to the antenna (low)
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
123
124 // get TI tag data into the buffer
125 AcquireTiType();
126
127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
128
129 for (i=0; i<n-1; i++) {
130 // count cycles by looking for lo to hi zero crossings
131 if ( (dest[i]<0) && (dest[i+1]>0) ) {
132 cycles++;
133 // after 16 cycles, measure the frequency
134 if (cycles>15) {
135 cycles=0;
136 samples=i-samples; // number of samples in these 16 cycles
137
138 // TI bits are coming to us lsb first so shift them
139 // right through our 128 bit right shift register
140 shift0 = (shift0>>1) | (shift1 << 31);
141 shift1 = (shift1>>1) | (shift2 << 31);
142 shift2 = (shift2>>1) | (shift3 << 31);
143 shift3 >>= 1;
144
145 // check if the cycles fall close to the number
146 // expected for either the low or high frequency
147 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
148 // low frequency represents a 1
149 shift3 |= (1<<31);
150 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
151 // high frequency represents a 0
152 } else {
153 // probably detected a gay waveform or noise
154 // use this as gaydar or discard shift register and start again
155 shift3 = shift2 = shift1 = shift0 = 0;
156 }
157 samples = i;
158
159 // for each bit we receive, test if we've detected a valid tag
160
161 // if we see 17 zeroes followed by 6 ones, we might have a tag
162 // remember the bits are backwards
163 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
164 // if start and end bytes match, we have a tag so break out of the loop
165 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
166 cycles = 0xF0B; //use this as a flag (ugly but whatever)
167 break;
168 }
169 }
170 }
171 }
172 }
173
174 // if flag is set we have a tag
175 if (cycles!=0xF0B) {
176 DbpString("Info: No valid tag detected.");
177 } else {
178 // put 64 bit data into shift1 and shift0
179 shift0 = (shift0>>24) | (shift1 << 8);
180 shift1 = (shift1>>24) | (shift2 << 8);
181
182 // align 16 bit crc into lower half of shift2
183 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
184
185 // if r/w tag, check ident match
186 if (shift3 & (1<<15) ) {
187 DbpString("Info: TI tag is rewriteable");
188 // only 15 bits compare, last bit of ident is not valid
189 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
190 DbpString("Error: Ident mismatch!");
191 } else {
192 DbpString("Info: TI tag ident is valid");
193 }
194 } else {
195 DbpString("Info: TI tag is readonly");
196 }
197
198 // WARNING the order of the bytes in which we calc crc below needs checking
199 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
200 // bytes in reverse or something
201 // calculate CRC
202 uint32_t crc=0;
203
204 crc = update_crc16(crc, (shift0)&0xff);
205 crc = update_crc16(crc, (shift0>>8)&0xff);
206 crc = update_crc16(crc, (shift0>>16)&0xff);
207 crc = update_crc16(crc, (shift0>>24)&0xff);
208 crc = update_crc16(crc, (shift1)&0xff);
209 crc = update_crc16(crc, (shift1>>8)&0xff);
210 crc = update_crc16(crc, (shift1>>16)&0xff);
211 crc = update_crc16(crc, (shift1>>24)&0xff);
212
213 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
214 if (crc != (shift2&0xffff)) {
215 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
216 } else {
217 DbpString("Info: CRC is good");
218 }
219 }
220 StopTicks();
221 }
222
223 void WriteTIbyte(uint8_t b)
224 {
225 int i = 0;
226
227 // modulate 8 bits out to the antenna
228 for (i=0; i<8; i++)
229 {
230 if ( b & ( 1 << i ) ) {
231 // stop modulating antenna 1ms
232 LOW(GPIO_SSC_DOUT);
233 WaitUS(1000);
234 // modulate antenna 1ms
235 HIGH(GPIO_SSC_DOUT);
236 WaitUS(1000);
237 } else {
238 // stop modulating antenna 1ms
239 LOW(GPIO_SSC_DOUT);
240 WaitUS(300);
241 // modulate antenna 1m
242 HIGH(GPIO_SSC_DOUT);
243 WaitUS(1700);
244 }
245 }
246 }
247
248 void AcquireTiType(void)
249 {
250 int i, j, n;
251 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
252 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
253 #define TIBUFLEN 1250
254
255 // clear buffer
256 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
257
258 //clear buffer now so it does not interfere with timing later
259 BigBuf_Clear_ext(false);
260
261 // Set up the synchronous serial port
262 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
263 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
264
265 // steal this pin from the SSP and use it to control the modulation
266 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
267 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
268
269 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
270 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
271
272 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
273 // 48/2 = 24 MHz clock must be divided by 12
274 AT91C_BASE_SSC->SSC_CMR = 12;
275
276 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
277 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
278 AT91C_BASE_SSC->SSC_TCMR = 0;
279 AT91C_BASE_SSC->SSC_TFMR = 0;
280 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
281 LED_D_ON();
282
283 // modulate antenna
284 HIGH(GPIO_SSC_DOUT);
285
286 // Charge TI tag for 50ms.
287 WaitMS(50);
288
289 // stop modulating antenna and listen
290 LOW(GPIO_SSC_DOUT);
291
292 LED_D_OFF();
293
294 i = 0;
295 for(;;) {
296 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
297 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
298 i++; if(i >= TIBUFLEN) break;
299 }
300 WDT_HIT();
301 }
302
303 // return stolen pin to SSP
304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
306
307 char *dest = (char *)BigBuf_get_addr();
308 n = TIBUFLEN * 32;
309
310 // unpack buffer
311 for (i = TIBUFLEN-1; i >= 0; i--) {
312 for (j = 0; j < 32; j++) {
313 if(buf[i] & (1 << j)) {
314 dest[--n] = 1;
315 } else {
316 dest[--n] = -1;
317 }
318 }
319 }
320 }
321
322 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
323 // if crc provided, it will be written with the data verbatim (even if bogus)
324 // if not provided a valid crc will be computed from the data and written.
325 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
326 {
327 StartTicks();
328 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
329 if(crc == 0) {
330 crc = update_crc16(crc, (idlo)&0xff);
331 crc = update_crc16(crc, (idlo>>8)&0xff);
332 crc = update_crc16(crc, (idlo>>16)&0xff);
333 crc = update_crc16(crc, (idlo>>24)&0xff);
334 crc = update_crc16(crc, (idhi)&0xff);
335 crc = update_crc16(crc, (idhi>>8)&0xff);
336 crc = update_crc16(crc, (idhi>>16)&0xff);
337 crc = update_crc16(crc, (idhi>>24)&0xff);
338 }
339 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
340
341 // TI tags charge at 134.2Khz
342 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
343 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
344 // connects to SSP_DIN and the SSP_DOUT logic level controls
345 // whether we're modulating the antenna (high)
346 // or listening to the antenna (low)
347 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
348 LED_A_ON();
349
350 // steal this pin from the SSP and use it to control the modulation
351 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
352 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
353
354 // writing algorithm:
355 // a high bit consists of a field off for 1ms and field on for 1ms
356 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
357 // initiate a charge time of 50ms (field on) then immediately start writing bits
358 // start by writing 0xBB (keyword) and 0xEB (password)
359 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
360 // finally end with 0x0300 (write frame)
361 // all data is sent lsb first
362 // finish with 15ms programming time
363
364 // modulate antenna
365 HIGH(GPIO_SSC_DOUT);
366 WaitMS(50); // charge time
367
368 WriteTIbyte(0xbb); // keyword
369 WriteTIbyte(0xeb); // password
370 WriteTIbyte( (idlo )&0xff );
371 WriteTIbyte( (idlo>>8 )&0xff );
372 WriteTIbyte( (idlo>>16)&0xff );
373 WriteTIbyte( (idlo>>24)&0xff );
374 WriteTIbyte( (idhi )&0xff );
375 WriteTIbyte( (idhi>>8 )&0xff );
376 WriteTIbyte( (idhi>>16)&0xff );
377 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
378 WriteTIbyte( (crc )&0xff ); // crc lo
379 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
380 WriteTIbyte(0x00); // write frame lo
381 WriteTIbyte(0x03); // write frame hi
382 HIGH(GPIO_SSC_DOUT);
383 WaitMS(50); // programming time
384
385 LED_A_OFF();
386
387 // get TI tag data into the buffer
388 AcquireTiType();
389
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
391 DbpString("Now use `lf ti read` to check");
392 StopTicks();
393 }
394
395 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
396 {
397 int i = 0;
398 uint8_t *buf = BigBuf_get_addr();
399
400 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
401 //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
402 //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE );
403 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
404
405 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
406 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
407 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
408
409 // power on antenna
410 // OPEN_COIL();
411 // SpinDelay(50);
412
413 for(;;) {
414 WDT_HIT();
415
416 if (ledcontrol) LED_D_ON();
417
418 // wait until SSC_CLK goes HIGH
419 // used as a simple detection of a reader field?
420 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
421 WDT_HIT();
422 if ( usb_poll_validate_length() || BUTTON_PRESS() )
423 goto OUT;
424 }
425
426 if(buf[i])
427 OPEN_COIL();
428 else
429 SHORT_COIL();
430
431 //wait until SSC_CLK goes LOW
432 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
433 WDT_HIT();
434 if ( usb_poll_validate_length() || BUTTON_PRESS() )
435 goto OUT;
436 }
437
438 i++;
439 if(i == period) {
440 i = 0;
441 if (gap) {
442 WDT_HIT();
443 SHORT_COIL();
444 SpinDelayUs(gap);
445 }
446 }
447
448 if (ledcontrol) LED_D_OFF();
449 }
450 OUT:
451 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
452 LED_D_OFF();
453 DbpString("Simulation stopped");
454 return;
455 }
456
457 #define DEBUG_FRAME_CONTENTS 1
458 void SimulateTagLowFrequencyBidir(int divisor, int t0)
459 {
460 }
461
462 // compose fc/8 fc/10 waveform (FSK2)
463 static void fc(int c, int *n)
464 {
465 uint8_t *dest = BigBuf_get_addr();
466 int idx;
467
468 // for when we want an fc8 pattern every 4 logical bits
469 if(c==0) {
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=1;
473 dest[((*n)++)]=1;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 dest[((*n)++)]=0;
477 dest[((*n)++)]=0;
478 }
479
480 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
481 if(c==8) {
482 for (idx=0; idx<6; idx++) {
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 }
492 }
493
494 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
495 if(c==10) {
496 for (idx=0; idx<5; idx++) {
497 dest[((*n)++)]=1;
498 dest[((*n)++)]=1;
499 dest[((*n)++)]=1;
500 dest[((*n)++)]=1;
501 dest[((*n)++)]=1;
502 dest[((*n)++)]=0;
503 dest[((*n)++)]=0;
504 dest[((*n)++)]=0;
505 dest[((*n)++)]=0;
506 dest[((*n)++)]=0;
507 }
508 }
509 }
510 // compose fc/X fc/Y waveform (FSKx)
511 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
512 {
513 uint8_t *dest = BigBuf_get_addr();
514 uint8_t halfFC = fc/2;
515 uint8_t wavesPerClock = clock/fc;
516 uint8_t mod = clock % fc; //modifier
517 uint8_t modAdj = fc/mod; //how often to apply modifier
518 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
519 // loop through clock - step field clock
520 for (uint8_t idx=0; idx < wavesPerClock; idx++){
521 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
522 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
523 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
524 *n += fc;
525 }
526 if (mod>0) (*modCnt)++;
527 if ((mod>0) && modAdjOk){ //fsk2
528 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
529 memset(dest+(*n), 0, fc-halfFC);
530 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
531 *n += fc;
532 }
533 }
534 if (mod>0 && !modAdjOk){ //fsk1
535 memset(dest+(*n), 0, mod-(mod/2));
536 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
537 *n += mod;
538 }
539 }
540
541 // prepare a waveform pattern in the buffer based on the ID given then
542 // simulate a HID tag until the button is pressed
543 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
544 {
545 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
546 set_tracing(FALSE);
547
548 int n = 0, i = 0;
549 /*
550 HID tag bitstream format
551 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
552 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
553 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
554 A fc8 is inserted before every 4 bits
555 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
556 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
557 */
558
559 if (hi > 0xFFF) {
560 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
561 return;
562 }
563 fc(0,&n);
564 // special start of frame marker containing invalid bit sequences
565 fc(8, &n); fc(8, &n); // invalid
566 fc(8, &n); fc(10, &n); // logical 0
567 fc(10, &n); fc(10, &n); // invalid
568 fc(8, &n); fc(10, &n); // logical 0
569
570 WDT_HIT();
571 // manchester encode bits 43 to 32
572 for (i=11; i>=0; i--) {
573 if ((i%4)==3) fc(0,&n);
574 if ((hi>>i)&1) {
575 fc(10, &n); fc(8, &n); // low-high transition
576 } else {
577 fc(8, &n); fc(10, &n); // high-low transition
578 }
579 }
580
581 WDT_HIT();
582 // manchester encode bits 31 to 0
583 for (i=31; i>=0; i--) {
584 if ((i%4)==3) fc(0,&n);
585 if ((lo>>i)&1) {
586 fc(10, &n); fc(8, &n); // low-high transition
587 } else {
588 fc(8, &n); fc(10, &n); // high-low transition
589 }
590 }
591 WDT_HIT();
592
593 if (ledcontrol) LED_A_ON();
594 SimulateTagLowFrequency(n, 0, ledcontrol);
595 if (ledcontrol) LED_A_OFF();
596 }
597
598 // prepare a waveform pattern in the buffer based on the ID given then
599 // simulate a FSK tag until the button is pressed
600 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
601 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
602 {
603 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
604
605 // free eventually allocated BigBuf memory
606 BigBuf_free(); BigBuf_Clear_ext(false);
607 clear_trace();
608 set_tracing(FALSE);
609
610 int ledcontrol = 1, n = 0, i = 0;
611 uint8_t fcHigh = arg1 >> 8;
612 uint8_t fcLow = arg1 & 0xFF;
613 uint16_t modCnt = 0;
614 uint8_t clk = arg2 & 0xFF;
615 uint8_t invert = (arg2 >> 8) & 1;
616
617 for (i=0; i<size; i++){
618
619 if (BitStream[i] == invert)
620 fcAll(fcLow, &n, clk, &modCnt);
621 else
622 fcAll(fcHigh, &n, clk, &modCnt);
623 }
624 WDT_HIT();
625
626 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
627
628 if (ledcontrol) LED_A_ON();
629 SimulateTagLowFrequency(n, 0, ledcontrol);
630 if (ledcontrol) LED_A_OFF();
631 }
632
633 // compose ask waveform for one bit(ASK)
634 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
635 {
636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 // c = current bit 1 or 0
639 if (manchester==1){
640 memset(dest+(*n), c, halfClk);
641 memset(dest+(*n) + halfClk, c^1, halfClk);
642 } else {
643 memset(dest+(*n), c, clock);
644 }
645 *n += clock;
646 }
647
648 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
649 {
650 uint8_t *dest = BigBuf_get_addr();
651 uint8_t halfClk = clock/2;
652 if (c){
653 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
654 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
655 } else {
656 memset(dest+(*n), c ^ *phase, clock);
657 *phase ^= 1;
658 }
659 *n += clock;
660 }
661
662 static void stAskSimBit(int *n, uint8_t clock) {
663 uint8_t *dest = BigBuf_get_addr();
664 uint8_t halfClk = clock/2;
665 //ST = .5 high .5 low 1.5 high .5 low 1 high
666 memset(dest+(*n), 1, halfClk);
667 memset(dest+(*n) + halfClk, 0, halfClk);
668 memset(dest+(*n) + clock, 1, clock + halfClk);
669 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
670 memset(dest+(*n) + clock*3, 1, clock);
671 *n += clock*4;
672 }
673
674 // args clock, ask/man or askraw, invert, transmission separator
675 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
676 {
677 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
678 set_tracing(FALSE);
679
680 int ledcontrol = 1, n = 0, i = 0;
681 uint8_t clk = (arg1 >> 8) & 0xFF;
682 uint8_t encoding = arg1 & 0xFF;
683 uint8_t separator = arg2 & 1;
684 uint8_t invert = (arg2 >> 8) & 1;
685
686 if (encoding == 2){ //biphase
687 uint8_t phase = 0;
688 for (i=0; i<size; i++){
689 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
690 }
691 if (phase == 1) { //run a second set inverted to keep phase in check
692 for (i=0; i<size; i++){
693 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
694 }
695 }
696 } else { // ask/manchester || ask/raw
697 for (i=0; i<size; i++){
698 askSimBit(BitStream[i]^invert, &n, clk, encoding);
699 }
700 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
701 for (i=0; i<size; i++){
702 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
703 }
704 }
705 }
706 if (separator==1 && encoding == 1)
707 stAskSimBit(&n, clk);
708 else if (separator==1)
709 Dbprintf("sorry but separator option not yet available");
710
711 WDT_HIT();
712
713 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
714
715 if (ledcontrol) LED_A_ON();
716 SimulateTagLowFrequency(n, 0, ledcontrol);
717 if (ledcontrol) LED_A_OFF();
718 }
719
720 //carrier can be 2,4 or 8
721 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
722 {
723 uint8_t *dest = BigBuf_get_addr();
724 uint8_t halfWave = waveLen/2;
725 //uint8_t idx;
726 int i = 0;
727 if (phaseChg){
728 // write phase change
729 memset(dest+(*n), *curPhase^1, halfWave);
730 memset(dest+(*n) + halfWave, *curPhase, halfWave);
731 *n += waveLen;
732 *curPhase ^= 1;
733 i += waveLen;
734 }
735 //write each normal clock wave for the clock duration
736 for (; i < clk; i+=waveLen){
737 memset(dest+(*n), *curPhase, halfWave);
738 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
739 *n += waveLen;
740 }
741 }
742
743 // args clock, carrier, invert,
744 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
745 {
746 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
747 set_tracing(FALSE);
748
749 int ledcontrol = 1, n = 0, i = 0;
750 uint8_t clk = arg1 >> 8;
751 uint8_t carrier = arg1 & 0xFF;
752 uint8_t invert = arg2 & 0xFF;
753 uint8_t curPhase = 0;
754 for (i=0; i<size; i++){
755 if (BitStream[i] == curPhase){
756 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
757 } else {
758 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
759 }
760 }
761
762 WDT_HIT();
763
764 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
765
766 if (ledcontrol) LED_A_ON();
767 SimulateTagLowFrequency(n, 0, ledcontrol);
768 if (ledcontrol) LED_A_OFF();
769 }
770
771 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
772 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
773 {
774 uint8_t *dest = BigBuf_get_addr();
775 size_t size = 0;
776 uint32_t hi2=0, hi=0, lo=0;
777 int idx=0;
778 // Configure to go in 125Khz listen mode
779 LFSetupFPGAForADC(95, true);
780
781 //clear read buffer
782 BigBuf_Clear_keep_EM();
783
784 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
785
786 WDT_HIT();
787 if (ledcontrol) LED_A_ON();
788
789 DoAcquisition_default(-1,true);
790 // FSK demodulator
791 size = 50*128*2; //big enough to catch 2 sequences of largest format
792 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
793
794 if (idx>0 && lo>0 && (size==96 || size==192)){
795 // go over previously decoded manchester data and decode into usable tag ID
796 if (hi2 != 0){ //extra large HID tags 88/192 bits
797 Dbprintf("TAG ID: %x%08x%08x (%d)",
798 (unsigned int) hi2,
799 (unsigned int) hi,
800 (unsigned int) lo,
801 (unsigned int) (lo>>1) & 0xFFFF
802 );
803 } else { //standard HID tags 44/96 bits
804 uint8_t bitlen = 0;
805 uint32_t fc = 0;
806 uint32_t cardnum = 0;
807
808 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
809 uint32_t lo2=0;
810 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
811 uint8_t idx3 = 1;
812 while(lo2 > 1){ //find last bit set to 1 (format len bit)
813 lo2=lo2 >> 1;
814 idx3++;
815 }
816 bitlen = idx3+19;
817 fc =0;
818 cardnum=0;
819 if(bitlen == 26){
820 cardnum = (lo>>1)&0xFFFF;
821 fc = (lo>>17)&0xFF;
822 }
823 if(bitlen == 37){
824 cardnum = (lo>>1)&0x7FFFF;
825 fc = ((hi&0xF)<<12)|(lo>>20);
826 }
827 if(bitlen == 34){
828 cardnum = (lo>>1)&0xFFFF;
829 fc= ((hi&1)<<15)|(lo>>17);
830 }
831 if(bitlen == 35){
832 cardnum = (lo>>1)&0xFFFFF;
833 fc = ((hi&1)<<11)|(lo>>21);
834 }
835 }
836 else { //if bit 38 is not set then 37 bit format is used
837 bitlen= 37;
838 fc =0;
839 cardnum=0;
840 if(bitlen==37){
841 cardnum = (lo>>1)&0x7FFFF;
842 fc = ((hi&0xF)<<12)|(lo>>20);
843 }
844 }
845 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
846 (unsigned int) hi,
847 (unsigned int) lo,
848 (unsigned int) (lo>>1) & 0xFFFF,
849 (unsigned int) bitlen,
850 (unsigned int) fc,
851 (unsigned int) cardnum);
852 }
853 if (findone){
854 if (ledcontrol) LED_A_OFF();
855 *high = hi;
856 *low = lo;
857 goto OUT;
858 }
859 // reset
860 }
861 hi2 = hi = lo = idx = 0;
862 WDT_HIT();
863 }
864 OUT:
865 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
866 DbpString("Stopped");
867 if (ledcontrol) LED_A_OFF();
868 }
869
870 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
871 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
872 {
873 uint8_t *dest = BigBuf_get_addr();
874 size_t size;
875 int idx=0;
876 //clear read buffer
877 BigBuf_Clear_keep_EM();
878 // Configure to go in 125Khz listen mode
879 LFSetupFPGAForADC(95, true);
880
881 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
882
883 WDT_HIT();
884 if (ledcontrol) LED_A_ON();
885
886 DoAcquisition_default(-1,true);
887 // FSK demodulator
888 size = 50*128*2; //big enough to catch 2 sequences of largest format
889 idx = AWIDdemodFSK(dest, &size);
890
891 if (idx<=0 || size!=96) continue;
892 // Index map
893 // 0 10 20 30 40 50 60
894 // | | | | | | |
895 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
896 // -----------------------------------------------------------------------------
897 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
898 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
899 // |---26 bit---| |-----117----||-------------142-------------|
900 // b = format bit len, o = odd parity of last 3 bits
901 // f = facility code, c = card number
902 // w = wiegand parity
903 // (26 bit format shown)
904
905 //get raw ID before removing parities
906 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
907 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
908 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
909
910 size = removeParity(dest, idx+8, 4, 1, 88);
911 if (size != 66) continue;
912
913 // Index map
914 // 0 10 20 30 40 50 60
915 // | | | | | | |
916 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
917 // -----------------------------------------------------------------------------
918 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
919 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
920 // |26 bit| |-117--| |-----142------|
921 //
922 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
923 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
924 // |50 bit| |----4000------||-----------2248975-------------|
925 //
926 // b = format bit len, o = odd parity of last 3 bits
927 // f = facility code, c = card number
928 // w = wiegand parity
929
930 uint32_t fc = 0;
931 uint32_t cardnum = 0;
932 uint32_t code1 = 0;
933 uint32_t code2 = 0;
934 uint8_t fmtLen = bytebits_to_byte(dest,8);
935 switch(fmtLen) {
936 case 26:
937 fc = bytebits_to_byte(dest + 9, 8);
938 cardnum = bytebits_to_byte(dest + 17, 16);
939 code1 = bytebits_to_byte(dest + 8,fmtLen);
940 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
941 break;
942 case 50:
943 fc = bytebits_to_byte(dest + 9, 16);
944 cardnum = bytebits_to_byte(dest + 25, 32);
945 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
946 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
947 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
948 break;
949 default:
950 if (fmtLen > 32 ) {
951 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
952 code1 = bytebits_to_byte(dest+8,fmtLen-32);
953 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
954 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
955 } else {
956 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
957 code1 = bytebits_to_byte(dest+8,fmtLen);
958 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
959 }
960 break;
961 }
962 if (findone)
963 goto OUT;
964
965 idx = 0;
966 WDT_HIT();
967 }
968 OUT:
969 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
970 DbpString("Stopped");
971 if (ledcontrol) LED_A_OFF();
972 }
973
974 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
975 {
976 uint8_t *dest = BigBuf_get_addr();
977
978 size_t size=0, idx=0;
979 int clk=0, invert=0, errCnt=0, maxErr=20;
980 uint32_t hi=0;
981 uint64_t lo=0;
982 //clear read buffer
983 BigBuf_Clear_keep_EM();
984 // Configure to go in 125Khz listen mode
985 LFSetupFPGAForADC(95, true);
986
987 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
988
989 WDT_HIT();
990 if (ledcontrol) LED_A_ON();
991
992 DoAcquisition_default(-1,true);
993 size = BigBuf_max_traceLen();
994 //askdemod and manchester decode
995 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
996 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
997 WDT_HIT();
998
999 if (errCnt<0) continue;
1000
1001 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
1002 if (errCnt){
1003 if (size>64){
1004 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
1005 hi,
1006 (uint32_t)(lo>>32),
1007 (uint32_t)lo,
1008 (uint32_t)(lo&0xFFFF),
1009 (uint32_t)((lo>>16LL) & 0xFF),
1010 (uint32_t)(lo & 0xFFFFFF));
1011 } else {
1012 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1013 (uint32_t)(lo>>32),
1014 (uint32_t)lo,
1015 (uint32_t)(lo&0xFFFF),
1016 (uint32_t)((lo>>16LL) & 0xFF),
1017 (uint32_t)(lo & 0xFFFFFF));
1018 }
1019
1020 if (findone){
1021 if (ledcontrol) LED_A_OFF();
1022 *high=lo>>32;
1023 *low=lo & 0xFFFFFFFF;
1024 return;
1025 }
1026 }
1027 WDT_HIT();
1028 hi = lo = size = idx = 0;
1029 clk = invert = errCnt = 0;
1030 }
1031 DbpString("Stopped");
1032 if (ledcontrol) LED_A_OFF();
1033 }
1034
1035 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1036 {
1037 uint8_t *dest = BigBuf_get_addr();
1038 int idx=0;
1039 uint32_t code=0, code2=0;
1040 uint8_t version=0;
1041 uint8_t facilitycode=0;
1042 uint16_t number=0;
1043 uint8_t crc = 0;
1044 uint16_t calccrc = 0;
1045
1046 //clear read buffer
1047 BigBuf_Clear_keep_EM();
1048
1049 // Configure to go in 125Khz listen mode
1050 LFSetupFPGAForADC(95, true);
1051
1052 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1053 WDT_HIT();
1054 if (ledcontrol) LED_A_ON();
1055 DoAcquisition_default(-1,true);
1056 //fskdemod and get start index
1057 WDT_HIT();
1058 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1059 if (idx<0) continue;
1060 //valid tag found
1061
1062 //Index map
1063 //0 10 20 30 40 50 60
1064 //| | | | | | |
1065 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1066 //-----------------------------------------------------------------------------
1067 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1068 //
1069 //Checksum:
1070 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1071 //preamble F0 E0 01 03 B6 75
1072 // How to calc checksum,
1073 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1074 // F0 + E0 + 01 + 03 + B6 = 28A
1075 // 28A & FF = 8A
1076 // FF - 8A = 75
1077 // Checksum: 0x75
1078 //XSF(version)facility:codeone+codetwo
1079 //Handle the data
1080 // if(findone){ //only print binary if we are doing one
1081 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1082 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1083 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1084 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1085 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1086 // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1087 // Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1088 // }
1089 code = bytebits_to_byte(dest+idx,32);
1090 code2 = bytebits_to_byte(dest+idx+32,32);
1091 version = bytebits_to_byte(dest+idx+27,8); //14,4
1092 facilitycode = bytebits_to_byte(dest+idx+18,8);
1093 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1094
1095 crc = bytebits_to_byte(dest+idx+54,8);
1096 for (uint8_t i=1; i<6; ++i)
1097 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1098 calccrc &= 0xff;
1099 calccrc = 0xff - calccrc;
1100
1101 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1102
1103 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1104 // if we're only looking for one tag
1105 if (findone){
1106 if (ledcontrol) LED_A_OFF();
1107 *high=code;
1108 *low=code2;
1109 goto OUT;
1110 }
1111 code=code2=0;
1112 version=facilitycode=0;
1113 number=0;
1114 idx=0;
1115
1116 WDT_HIT();
1117 }
1118 OUT:
1119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1120 DbpString("Stopped");
1121 if (ledcontrol) LED_A_OFF();
1122 }
1123
1124 /*------------------------------
1125 * T5555/T5557/T5567/T5577 routines
1126 *------------------------------
1127 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1128 *
1129 * Relevant communication times in microsecond
1130 * To compensate antenna falling times shorten the write times
1131 * and enlarge the gap ones.
1132 * Q5 tags seems to have issues when these values changes.
1133 */
1134
1135 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
1136 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
1137 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
1138 #define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
1139 #define READ_GAP 15*8
1140
1141 // VALUES TAKEN FROM EM4x function: SendForward
1142 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1143 // WRITE_GAP = 128; (16*8)
1144 // WRITE_1 = 256 32*8; (32*8)
1145
1146 // These timings work for 4469/4269/4305 (with the 55*8 above)
1147 // WRITE_0 = 23*8 , 9*8
1148
1149 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1150 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1151 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1152 // T0 = TIMER_CLOCK1 / 125000 = 192
1153 // 1 Cycle = 8 microseconds(us) == 1 field clock
1154
1155 // new timer:
1156 // = 1us = 1.5ticks
1157 // 1fc = 8us = 12ticks
1158 void TurnReadLFOn(uint32_t delay) {
1159 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1160
1161 // measure antenna strength.
1162 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1163
1164 // Give it a bit of time for the resonant antenna to settle.
1165 WaitUS(delay);
1166 }
1167
1168 // Write one bit to card
1169 void T55xxWriteBit(int bit) {
1170 if (!bit)
1171 TurnReadLFOn(WRITE_0);
1172 else
1173 TurnReadLFOn(WRITE_1);
1174 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1175 WaitUS(WRITE_GAP);
1176 }
1177
1178 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1179 void T55xxResetRead(void) {
1180 LED_A_ON();
1181 //clear buffer now so it does not interfere with timing later
1182 BigBuf_Clear_keep_EM();
1183
1184 // Set up FPGA, 125kHz
1185 LFSetupFPGAForADC(95, true);
1186
1187 // Trigger T55x7 in mode.
1188 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1189 WaitUS(START_GAP);
1190
1191 // reset tag - op code 00
1192 T55xxWriteBit(0);
1193 T55xxWriteBit(0);
1194
1195 // Turn field on to read the response
1196 TurnReadLFOn(READ_GAP);
1197
1198 // Acquisition
1199 doT55x7Acquisition(BigBuf_max_traceLen());
1200
1201 // Turn the field off
1202 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1203 cmd_send(CMD_ACK,0,0,0,0,0);
1204 LED_A_OFF();
1205 }
1206
1207 // Write one card block in page 0, no lock
1208 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1209 LED_A_ON();
1210 bool PwdMode = arg & 0x1;
1211 uint8_t Page = (arg & 0x2)>>1;
1212 uint32_t i = 0;
1213
1214 // Set up FPGA, 125kHz
1215 LFSetupFPGAForADC(95, true);
1216
1217 // Trigger T55x7 in mode.
1218 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1219 WaitUS(START_GAP);
1220
1221 // Opcode 10
1222 T55xxWriteBit(1);
1223 T55xxWriteBit(Page); //Page 0
1224 if (PwdMode){
1225 // Send Pwd
1226 for (i = 0x80000000; i != 0; i >>= 1)
1227 T55xxWriteBit(Pwd & i);
1228 }
1229 // Send Lock bit
1230 T55xxWriteBit(0);
1231
1232 // Send Data
1233 for (i = 0x80000000; i != 0; i >>= 1)
1234 T55xxWriteBit(Data & i);
1235
1236 // Send Block number
1237 for (i = 0x04; i != 0; i >>= 1)
1238 T55xxWriteBit(Block & i);
1239
1240 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1241 // so wait a little more)
1242 TurnReadLFOn(20 * 1000);
1243
1244 //could attempt to do a read to confirm write took
1245 // as the tag should repeat back the new block
1246 // until it is reset, but to confirm it we would
1247 // need to know the current block 0 config mode
1248
1249 // turn field off
1250 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1251 LED_A_OFF();
1252 }
1253
1254 // Write one card block in page 0, no lock
1255 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1256 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1257 cmd_send(CMD_ACK,0,0,0,0,0);
1258 }
1259
1260 // Read one card block in page [page]
1261 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1262 LED_A_ON();
1263 bool PwdMode = arg0 & 0x1;
1264 uint8_t Page = (arg0 & 0x2) >> 1;
1265 uint32_t i = 0;
1266 bool RegReadMode = (Block == 0xFF);
1267
1268 //clear buffer now so it does not interfere with timing later
1269 BigBuf_Clear_keep_EM();
1270
1271 //make sure block is at max 7
1272 Block &= 0x7;
1273
1274 // Set up FPGA, 125kHz to power up the tag
1275 LFSetupFPGAForADC(95, true);
1276 SpinDelay(3);
1277
1278 // Trigger T55x7 Direct Access Mode with start gap
1279 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1280 WaitUS(START_GAP);
1281
1282 // Opcode 1[page]
1283 T55xxWriteBit(1);
1284 T55xxWriteBit(Page); //Page 0
1285
1286 if (PwdMode){
1287 // Send Pwd
1288 for (i = 0x80000000; i != 0; i >>= 1)
1289 T55xxWriteBit(Pwd & i);
1290 }
1291 // Send a zero bit separation
1292 T55xxWriteBit(0);
1293
1294 // Send Block number (if direct access mode)
1295 if (!RegReadMode)
1296 for (i = 0x04; i != 0; i >>= 1)
1297 T55xxWriteBit(Block & i);
1298
1299 // Turn field on to read the response
1300 TurnReadLFOn(READ_GAP);
1301
1302 // Acquisition
1303 doT55x7Acquisition(12000);
1304
1305 // Turn the field off
1306 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1307 cmd_send(CMD_ACK,0,0,0,0,0);
1308 LED_A_OFF();
1309 }
1310
1311 void T55xxWakeUp(uint32_t Pwd){
1312 LED_B_ON();
1313 uint32_t i = 0;
1314
1315 // Set up FPGA, 125kHz
1316 LFSetupFPGAForADC(95, true);
1317
1318 // Trigger T55x7 Direct Access Mode
1319 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1320 WaitUS(START_GAP);
1321
1322 // Opcode 10
1323 T55xxWriteBit(1);
1324 T55xxWriteBit(0); //Page 0
1325
1326 // Send Pwd
1327 for (i = 0x80000000; i != 0; i >>= 1)
1328 T55xxWriteBit(Pwd & i);
1329
1330 // Turn and leave field on to let the begin repeating transmission
1331 TurnReadLFOn(20*1000);
1332 }
1333
1334 /*-------------- Cloning routines -----------*/
1335 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1336 // write last block first and config block last (if included)
1337 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1338 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1339 }
1340
1341 // Copy HID id to card and setup block 0 config
1342 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1343 uint32_t data[] = {0,0,0,0,0,0,0};
1344 uint8_t last_block = 0;
1345
1346 if (longFMT){
1347 // Ensure no more than 84 bits supplied
1348 if (hi2 > 0xFFFFF) {
1349 DbpString("Tags can only have 84 bits.");
1350 return;
1351 }
1352 // Build the 6 data blocks for supplied 84bit ID
1353 last_block = 6;
1354 // load preamble (1D) & long format identifier (9E manchester encoded)
1355 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1356 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1357 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1358 data[3] = manchesterEncode2Bytes(hi >> 16);
1359 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1360 data[5] = manchesterEncode2Bytes(lo >> 16);
1361 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1362 } else {
1363 // Ensure no more than 44 bits supplied
1364 if (hi > 0xFFF) {
1365 DbpString("Tags can only have 44 bits.");
1366 return;
1367 }
1368 // Build the 3 data blocks for supplied 44bit ID
1369 last_block = 3;
1370 // load preamble
1371 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1372 data[2] = manchesterEncode2Bytes(lo >> 16);
1373 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1374 }
1375 // load chip config block
1376 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1377
1378 //TODO add selection of chip for Q5 or T55x7
1379 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1380
1381 LED_D_ON();
1382 // Program the data blocks for supplied ID
1383 // and the block 0 for HID format
1384 WriteT55xx(data, 0, last_block+1);
1385
1386 LED_D_OFF();
1387
1388 DbpString("DONE!");
1389 }
1390
1391 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1392 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1393 //TODO add selection of chip for Q5 or T55x7
1394 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1395 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1396
1397 LED_D_ON();
1398 // Program the data blocks for supplied ID
1399 // and the block 0 config
1400 WriteT55xx(data, 0, 3);
1401 LED_D_OFF();
1402 DbpString("DONE!");
1403 }
1404
1405 // Clone Indala 64-bit tag by UID to T55x7
1406 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1407 //Program the 2 data blocks for supplied 64bit UID
1408 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1409 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1410 //TODO add selection of chip for Q5 or T55x7
1411 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1412
1413 WriteT55xx(data, 0, 3);
1414 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1415 // T5567WriteBlock(0x603E1042,0);
1416 DbpString("DONE!");
1417 }
1418 // Clone Indala 224-bit tag by UID to T55x7
1419 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1420 //Program the 7 data blocks for supplied 224bit UID
1421 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1422 // and the block 0 for Indala224 format
1423 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1424 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1425 //TODO add selection of chip for Q5 or T55x7
1426 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1427 WriteT55xx(data, 0, 8);
1428 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1429 // T5567WriteBlock(0x603E10E2,0);
1430 DbpString("DONE!");
1431 }
1432 // clone viking tag to T55xx
1433 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1434 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1435 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1436 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1437 // Program the data blocks for supplied ID and the block 0 config
1438 WriteT55xx(data, 0, 3);
1439 LED_D_OFF();
1440 cmd_send(CMD_ACK,0,0,0,0,0);
1441 }
1442
1443 // Define 9bit header for EM410x tags
1444 #define EM410X_HEADER 0x1FF
1445 #define EM410X_ID_LENGTH 40
1446
1447 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1448 int i, id_bit;
1449 uint64_t id = EM410X_HEADER;
1450 uint64_t rev_id = 0; // reversed ID
1451 int c_parity[4]; // column parity
1452 int r_parity = 0; // row parity
1453 uint32_t clock = 0;
1454
1455 // Reverse ID bits given as parameter (for simpler operations)
1456 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1457 if (i < 32) {
1458 rev_id = (rev_id << 1) | (id_lo & 1);
1459 id_lo >>= 1;
1460 } else {
1461 rev_id = (rev_id << 1) | (id_hi & 1);
1462 id_hi >>= 1;
1463 }
1464 }
1465
1466 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1467 id_bit = rev_id & 1;
1468
1469 if (i % 4 == 0) {
1470 // Don't write row parity bit at start of parsing
1471 if (i)
1472 id = (id << 1) | r_parity;
1473 // Start counting parity for new row
1474 r_parity = id_bit;
1475 } else {
1476 // Count row parity
1477 r_parity ^= id_bit;
1478 }
1479
1480 // First elements in column?
1481 if (i < 4)
1482 // Fill out first elements
1483 c_parity[i] = id_bit;
1484 else
1485 // Count column parity
1486 c_parity[i % 4] ^= id_bit;
1487
1488 // Insert ID bit
1489 id = (id << 1) | id_bit;
1490 rev_id >>= 1;
1491 }
1492
1493 // Insert parity bit of last row
1494 id = (id << 1) | r_parity;
1495
1496 // Fill out column parity at the end of tag
1497 for (i = 0; i < 4; ++i)
1498 id = (id << 1) | c_parity[i];
1499
1500 // Add stop bit
1501 id <<= 1;
1502
1503 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1504 LED_D_ON();
1505
1506 // Write EM410x ID
1507 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1508
1509 clock = (card & 0xFF00) >> 8;
1510 clock = (clock == 0) ? 64 : clock;
1511 Dbprintf("Clock rate: %d", clock);
1512 if (card & 0xFF) { //t55x7
1513 clock = GetT55xxClockBit(clock);
1514 if (clock == 0) {
1515 Dbprintf("Invalid clock rate: %d", clock);
1516 return;
1517 }
1518 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1519 } else { //t5555 (Q5)
1520 clock = (clock-2)>>1; //n = (RF-2)/2
1521 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1522 }
1523
1524 WriteT55xx(data, 0, 3);
1525
1526 LED_D_OFF();
1527 Dbprintf("Tag %s written with 0x%08x%08x\n",
1528 card ? "T55x7":"T5555",
1529 (uint32_t)(id >> 32),
1530 (uint32_t)id);
1531 }
1532
1533 //-----------------------------------
1534 // EM4469 / EM4305 routines
1535 //-----------------------------------
1536 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1537 #define FWD_CMD_WRITE 0xA
1538 #define FWD_CMD_READ 0x9
1539 #define FWD_CMD_DISABLE 0x5
1540
1541 uint8_t forwardLink_data[64]; //array of forwarded bits
1542 uint8_t * forward_ptr; //ptr for forward message preparation
1543 uint8_t fwd_bit_sz; //forwardlink bit counter
1544 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1545
1546 //====================================================================
1547 // prepares command bits
1548 // see EM4469 spec
1549 //====================================================================
1550 //--------------------------------------------------------------------
1551 // VALUES TAKEN FROM EM4x function: SendForward
1552 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1553 // WRITE_GAP = 128; (16*8)
1554 // WRITE_1 = 256 32*8; (32*8)
1555
1556 // These timings work for 4469/4269/4305 (with the 55*8 above)
1557 // WRITE_0 = 23*8 , 9*8
1558
1559 uint8_t Prepare_Cmd( uint8_t cmd ) {
1560
1561 *forward_ptr++ = 0; //start bit
1562 *forward_ptr++ = 0; //second pause for 4050 code
1563
1564 *forward_ptr++ = cmd;
1565 cmd >>= 1;
1566 *forward_ptr++ = cmd;
1567 cmd >>= 1;
1568 *forward_ptr++ = cmd;
1569 cmd >>= 1;
1570 *forward_ptr++ = cmd;
1571
1572 return 6; //return number of emited bits
1573 }
1574
1575 //====================================================================
1576 // prepares address bits
1577 // see EM4469 spec
1578 //====================================================================
1579 uint8_t Prepare_Addr( uint8_t addr ) {
1580
1581 register uint8_t line_parity;
1582
1583 uint8_t i;
1584 line_parity = 0;
1585 for(i=0;i<6;i++) {
1586 *forward_ptr++ = addr;
1587 line_parity ^= addr;
1588 addr >>= 1;
1589 }
1590
1591 *forward_ptr++ = (line_parity & 1);
1592
1593 return 7; //return number of emited bits
1594 }
1595
1596 //====================================================================
1597 // prepares data bits intreleaved with parity bits
1598 // see EM4469 spec
1599 //====================================================================
1600 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1601
1602 register uint8_t line_parity;
1603 register uint8_t column_parity;
1604 register uint8_t i, j;
1605 register uint16_t data;
1606
1607 data = data_low;
1608 column_parity = 0;
1609
1610 for(i=0; i<4; i++) {
1611 line_parity = 0;
1612 for(j=0; j<8; j++) {
1613 line_parity ^= data;
1614 column_parity ^= (data & 1) << j;
1615 *forward_ptr++ = data;
1616 data >>= 1;
1617 }
1618 *forward_ptr++ = line_parity;
1619 if(i == 1)
1620 data = data_hi;
1621 }
1622
1623 for(j=0; j<8; j++) {
1624 *forward_ptr++ = column_parity;
1625 column_parity >>= 1;
1626 }
1627 *forward_ptr = 0;
1628
1629 return 45; //return number of emited bits
1630 }
1631
1632 //====================================================================
1633 // Forward Link send function
1634 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1635 // fwd_bit_count set with number of bits to be sent
1636 //====================================================================
1637 void SendForward(uint8_t fwd_bit_count) {
1638
1639 fwd_write_ptr = forwardLink_data;
1640 fwd_bit_sz = fwd_bit_count;
1641
1642 LED_D_ON();
1643
1644 // Set up FPGA, 125kHz
1645 LFSetupFPGAForADC(95, true);
1646
1647 // force 1st mod pulse (start gap must be longer for 4305)
1648 fwd_bit_sz--; //prepare next bit modulation
1649 fwd_write_ptr++;
1650 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1651 WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
1652 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1653 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1654
1655 // now start writting
1656 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1657 if(((*fwd_write_ptr++) & 1) == 1)
1658 WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1659 else {
1660 //These timings work for 4469/4269/4305 (with the 55*8 above)
1661 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1662 WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1663 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1664 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1665 }
1666 }
1667 }
1668
1669 void EM4xLogin(uint32_t Password) {
1670
1671 uint8_t fwd_bit_count;
1672 forward_ptr = forwardLink_data;
1673 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1674 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1675 SendForward(fwd_bit_count);
1676
1677 //Wait for command to complete
1678 WaitMS(20);
1679 }
1680
1681 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1682
1683 uint8_t fwd_bit_count;
1684 uint8_t *dest = BigBuf_get_addr();
1685 uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
1686 uint32_t i = 0;
1687
1688 // Clear destination buffer before sending the command
1689 BigBuf_Clear_ext(false);
1690
1691 //If password mode do login
1692 if (PwdMode == 1) EM4xLogin(Pwd);
1693
1694 forward_ptr = forwardLink_data;
1695 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1696 fwd_bit_count += Prepare_Addr( Address );
1697
1698 SendForward(fwd_bit_count);
1699
1700 // Now do the acquisition
1701 // ICEMAN, change to the one in lfsampling.c
1702 i = 0;
1703 for(;;) {
1704 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1705 AT91C_BASE_SSC->SSC_THR = 0x43;
1706 }
1707 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1708 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1709 ++i;
1710 if (i >= bufsize) break;
1711 }
1712 }
1713
1714 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1715 cmd_send(CMD_ACK,0,0,0,0,0);
1716 LED_D_OFF();
1717 }
1718
1719 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1720
1721 uint8_t fwd_bit_count;
1722
1723 //If password mode do login
1724 if (PwdMode == 1) EM4xLogin(Pwd);
1725
1726 forward_ptr = forwardLink_data;
1727 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1728 fwd_bit_count += Prepare_Addr( Address );
1729 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1730
1731 SendForward(fwd_bit_count);
1732
1733 //Wait for write to complete
1734 WaitMS(20);
1735 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1736 LED_D_OFF();
1737 }
Proxmark3 GIT tracking
Impressum, Datenschutz