1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
11 #include "proxmark3.h"
18 #include "lfsampling.h"
22 * Function to do a modulation and then get samples.
28 void ModThenAcquireRawAdcSamples125k(int delay_off
, int period_0
, int period_1
, uint8_t *command
)
31 int divisor_used
= 95; // 125 KHz
32 // see if 'h' was specified
34 if (command
[strlen((char *) command
) - 1] == 'h')
35 divisor_used
= 88; // 134.8 KHz
37 sample_config sc
= { 0,0,1, divisor_used
, 0};
38 setSamplingConfig(&sc
);
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
45 LFSetupFPGAForADC(sc
.divisor
, 1);
47 // And a little more time for the tag to fully power up
50 // now modulate the reader field
51 while(*command
!= '\0' && *command
!= ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
54 SpinDelayUs(delay_off
);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, sc
.divisor
);
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
59 if(*(command
++) == '0')
60 SpinDelayUs(period_0
);
62 SpinDelayUs(period_1
);
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
66 SpinDelayUs(delay_off
);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, sc
.divisor
);
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
72 DoAcquisition_config(false);
77 /* blank r/w tag data stream
78 ...0000000000000000 01111111
79 1010101010101010101010101010101010101010101010101010101010101010
82 101010101010101[0]000...
84 [5555fe852c5555555555555555fe0000]
88 // some hardcoded initial params
89 // when we read a TI tag we sample the zerocross line at 2Mhz
90 // TI tags modulate a 1 as 16 cycles of 123.2Khz
91 // TI tags modulate a 0 as 16 cycles of 134.2Khz
92 #define FSAMPLE 2000000
96 signed char *dest
= (signed char *)BigBuf_get_addr();
97 uint16_t n
= BigBuf_max_traceLen();
98 // 128 bit shift register [shift3:shift2:shift1:shift0]
99 uint32_t shift3
= 0, shift2
= 0, shift1
= 0, shift0
= 0;
101 int i
, cycles
=0, samples
=0;
102 // how many sample points fit in 16 cycles of each frequency
103 uint32_t sampleslo
= (FSAMPLE
<<4)/FREQLO
, sampleshi
= (FSAMPLE
<<4)/FREQHI
;
104 // when to tell if we're close enough to one freq or another
105 uint32_t threshold
= (sampleslo
- sampleshi
+ 1)>>1;
107 // TI tags charge at 134.2Khz
108 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
111 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
112 // connects to SSP_DIN and the SSP_DOUT logic level controls
113 // whether we're modulating the antenna (high)
114 // or listening to the antenna (low)
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
117 // get TI tag data into the buffer
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
122 for (i
=0; i
<n
-1; i
++) {
123 // count cycles by looking for lo to hi zero crossings
124 if ( (dest
[i
]<0) && (dest
[i
+1]>0) ) {
126 // after 16 cycles, measure the frequency
129 samples
=i
-samples
; // number of samples in these 16 cycles
131 // TI bits are coming to us lsb first so shift them
132 // right through our 128 bit right shift register
133 shift0
= (shift0
>>1) | (shift1
<< 31);
134 shift1
= (shift1
>>1) | (shift2
<< 31);
135 shift2
= (shift2
>>1) | (shift3
<< 31);
138 // check if the cycles fall close to the number
139 // expected for either the low or high frequency
140 if ( (samples
>(sampleslo
-threshold
)) && (samples
<(sampleslo
+threshold
)) ) {
141 // low frequency represents a 1
143 } else if ( (samples
>(sampleshi
-threshold
)) && (samples
<(sampleshi
+threshold
)) ) {
144 // high frequency represents a 0
146 // probably detected a gay waveform or noise
147 // use this as gaydar or discard shift register and start again
148 shift3
= shift2
= shift1
= shift0
= 0;
152 // for each bit we receive, test if we've detected a valid tag
154 // if we see 17 zeroes followed by 6 ones, we might have a tag
155 // remember the bits are backwards
156 if ( ((shift0
& 0x7fffff) == 0x7e0000) ) {
157 // if start and end bytes match, we have a tag so break out of the loop
158 if ( ((shift0
>>16)&0xff) == ((shift3
>>8)&0xff) ) {
159 cycles
= 0xF0B; //use this as a flag (ugly but whatever)
167 // if flag is set we have a tag
169 DbpString("Info: No valid tag detected.");
171 // put 64 bit data into shift1 and shift0
172 shift0
= (shift0
>>24) | (shift1
<< 8);
173 shift1
= (shift1
>>24) | (shift2
<< 8);
175 // align 16 bit crc into lower half of shift2
176 shift2
= ((shift2
>>24) | (shift3
<< 8)) & 0x0ffff;
178 // if r/w tag, check ident match
179 if (shift3
& (1<<15) ) {
180 DbpString("Info: TI tag is rewriteable");
181 // only 15 bits compare, last bit of ident is not valid
182 if (((shift3
>> 16) ^ shift0
) & 0x7fff ) {
183 DbpString("Error: Ident mismatch!");
185 DbpString("Info: TI tag ident is valid");
188 DbpString("Info: TI tag is readonly");
191 // WARNING the order of the bytes in which we calc crc below needs checking
192 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
193 // bytes in reverse or something
197 crc
= update_crc16(crc
, (shift0
)&0xff);
198 crc
= update_crc16(crc
, (shift0
>>8)&0xff);
199 crc
= update_crc16(crc
, (shift0
>>16)&0xff);
200 crc
= update_crc16(crc
, (shift0
>>24)&0xff);
201 crc
= update_crc16(crc
, (shift1
)&0xff);
202 crc
= update_crc16(crc
, (shift1
>>8)&0xff);
203 crc
= update_crc16(crc
, (shift1
>>16)&0xff);
204 crc
= update_crc16(crc
, (shift1
>>24)&0xff);
206 Dbprintf("Info: Tag data: %x%08x, crc=%x",
207 (unsigned int)shift1
, (unsigned int)shift0
, (unsigned int)shift2
& 0xFFFF);
208 if (crc
!= (shift2
&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc
);
211 DbpString("Info: CRC is good");
216 void WriteTIbyte(uint8_t b
)
220 // modulate 8 bits out to the antenna
224 // stop modulating antenna
231 // stop modulating antenna
241 void AcquireTiType(void)
244 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
245 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
246 #define TIBUFLEN 1250
249 uint32_t *BigBuf
= (uint32_t *)BigBuf_get_addr();
250 memset(BigBuf
,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DIN
;
254 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
;
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
258 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
260 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_SWRST
;
261 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_RXEN
| AT91C_SSC_TXEN
;
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC
->SSC_CMR
= 12;
267 AT91C_BASE_SSC
->SSC_RCMR
= SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC
->SSC_RFMR
= SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF
;
269 AT91C_BASE_SSC
->SSC_TCMR
= 0;
270 AT91C_BASE_SSC
->SSC_TFMR
= 0;
277 // Charge TI tag for 50ms.
280 // stop modulating antenna and listen
287 if(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
288 BigBuf
[i
] = AT91C_BASE_SSC
->SSC_RHR
; // store 32 bit values in buffer
289 i
++; if(i
>= TIBUFLEN
) break;
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DOUT
;
296 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
| GPIO_SSC_DOUT
;
298 char *dest
= (char *)BigBuf_get_addr();
301 for (i
=TIBUFLEN
-1; i
>=0; i
--) {
302 for (j
=0; j
<32; j
++) {
303 if(BigBuf
[i
] & (1 << j
)) {
312 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
313 // if crc provided, it will be written with the data verbatim (even if bogus)
314 // if not provided a valid crc will be computed from the data and written.
315 void WriteTItag(uint32_t idhi
, uint32_t idlo
, uint16_t crc
)
317 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
319 crc
= update_crc16(crc
, (idlo
)&0xff);
320 crc
= update_crc16(crc
, (idlo
>>8)&0xff);
321 crc
= update_crc16(crc
, (idlo
>>16)&0xff);
322 crc
= update_crc16(crc
, (idlo
>>24)&0xff);
323 crc
= update_crc16(crc
, (idhi
)&0xff);
324 crc
= update_crc16(crc
, (idhi
>>8)&0xff);
325 crc
= update_crc16(crc
, (idhi
>>16)&0xff);
326 crc
= update_crc16(crc
, (idhi
>>24)&0xff);
328 Dbprintf("Writing to tag: %x%08x, crc=%x",
329 (unsigned int) idhi
, (unsigned int) idlo
, crc
);
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
342 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb firts
352 // finish with 15ms programming time
356 SpinDelay(50); // charge time
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo
)&0xff );
361 WriteTIbyte( (idlo
>>8 )&0xff );
362 WriteTIbyte( (idlo
>>16)&0xff );
363 WriteTIbyte( (idlo
>>24)&0xff );
364 WriteTIbyte( (idhi
)&0xff );
365 WriteTIbyte( (idhi
>>8 )&0xff );
366 WriteTIbyte( (idhi
>>16)&0xff );
367 WriteTIbyte( (idhi
>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc
)&0xff ); // crc lo
369 WriteTIbyte( (crc
>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
373 SpinDelay(50); // programming time
377 // get TI tag data into the buffer
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
381 DbpString("Now use tiread to check");
384 void SimulateTagLowFrequency(int period
, int gap
, int ledcontrol
)
387 uint8_t *tab
= BigBuf_get_addr();
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
);
392 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
| GPIO_SSC_CLK
;
394 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
395 AT91C_BASE_PIOA
->PIO_ODR
= GPIO_SSC_CLK
;
397 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
398 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
402 while(!(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
)) {
404 DbpString("Stopped");
420 //wait for next sample time
421 while(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
) {
423 DbpString("Stopped");
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor
, int t0
)
445 // compose fc/8 fc/10 waveform (FSK2)
446 static void fc(int c
, int *n
)
448 uint8_t *dest
= BigBuf_get_addr();
451 // for when we want an fc8 pattern every 4 logical bits
463 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
465 for (idx
=0; idx
<6; idx
++) {
477 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
479 for (idx
=0; idx
<5; idx
++) {
493 // compose fc/X fc/Y waveform (FSKx)
494 static void fcAll(uint8_t c
, int *n
, uint8_t clock
)
496 uint8_t *dest
= BigBuf_get_addr();
499 // c = count of field clock for this bit
502 // loop through clock - step field clock
503 for (idx
=0; idx
< (uint8_t) clock
/c
; idx
++){
504 // loop through field clock length - put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 for (fcCnt
=0; fcCnt
< c
; fcCnt
++){
513 Dbprintf("mod: %d",mod
);
514 if (mod
>0){ //for FC counts that don't add up to a full clock cycle padd with extra wave
515 for (idx
=0; idx
< mod
; idx
++){
525 // prepare a waveform pattern in the buffer based on the ID given then
526 // simulate a HID tag until the button is pressed
527 void CmdHIDsimTAG(int hi
, int lo
, int ledcontrol
)
531 HID tag bitstream format
532 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
533 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
534 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
535 A fc8 is inserted before every 4 bits
536 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
537 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
541 DbpString("Tags can only have 44 bits.");
545 // special start of frame marker containing invalid bit sequences
546 fc(8, &n
); fc(8, &n
); // invalid
547 fc(8, &n
); fc(10, &n
); // logical 0
548 fc(10, &n
); fc(10, &n
); // invalid
549 fc(8, &n
); fc(10, &n
); // logical 0
552 // manchester encode bits 43 to 32
553 for (i
=11; i
>=0; i
--) {
554 if ((i
%4)==3) fc(0,&n
);
556 fc(10, &n
); fc(8, &n
); // low-high transition
558 fc(8, &n
); fc(10, &n
); // high-low transition
563 // manchester encode bits 31 to 0
564 for (i
=31; i
>=0; i
--) {
565 if ((i
%4)==3) fc(0,&n
);
567 fc(10, &n
); fc(8, &n
); // low-high transition
569 fc(8, &n
); fc(10, &n
); // high-low transition
575 SimulateTagLowFrequency(n
, 0, ledcontrol
);
581 // prepare a waveform pattern in the buffer based on the ID given then
582 // simulate a FSK tag until the button is pressed
583 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
584 void CmdFSKsimTAG(uint16_t arg1
, uint16_t arg2
, size_t size
, uint8_t *BitStream
)
588 uint8_t fcHigh
= arg1
>> 8;
589 uint8_t fcLow
= arg1
& 0xFF;
591 uint8_t clk
= arg2
& 0xFF;
592 uint8_t invert
= (arg2
>> 8) & 1;
596 for (i
=0; i
<size
; i
++){
597 if (BitStream
[i
] == invert
){
598 fcAll(fcLow
, &n
, clk
);
600 fcAll(fcHigh
, &n
, clk
);
603 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh
, fcLow
, clk
, invert
, n
);
604 //Dbprintf("First 64:");
605 //uint8_t *dest = BigBuf_get_addr();
607 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
609 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
611 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
613 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
617 SimulateTagLowFrequency(n
, 0, ledcontrol
);
623 // compose ask waveform for one bit(ASK)
624 static void askSimBit(uint8_t c
, int *n
, uint8_t clock
, uint8_t manchester
)
626 uint8_t *dest
= BigBuf_get_addr();
628 // c = current bit 1 or 0
630 // for when we want a separator
631 if (c
==2) { //separator
632 for (i
=0; i
<clock
/2; i
++){
637 for (idx
=0; idx
< (uint8_t) clock
/2; idx
++){
640 for (idx
=0; idx
< (uint8_t) clock
/2; idx
++){
644 for (idx
=0; idx
< (uint8_t) clock
; idx
++){
651 // args clock, ask/man or askraw, invert, transmission separator
652 void CmdASKsimTag(uint16_t arg1
, uint16_t arg2
, size_t size
, uint8_t *BitStream
)
656 uint8_t clk
= (arg1
>> 8) & 0xFF;
657 uint8_t manchester
= arg1
& 1;
658 uint8_t separator
= arg2
& 1;
659 uint8_t invert
= (arg2
>> 8) & 1;
661 for (i
=0; i
<size
; i
++){
662 askSimBit(BitStream
[i
]^invert
, &n
, clk
, manchester
);
664 if (separator
==1) Dbprintf("sorry but separator option not yet available"); //askSimBit(2, &n, clk, manchester);
666 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk
, invert
, manchester
, separator
, n
);
668 //Dbprintf("First 64:");
669 //uint8_t *dest = BigBuf_get_addr();
671 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
673 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
675 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
677 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
682 SimulateTagLowFrequency(n
, 0, ledcontrol
);
688 //carrier can be 2,4 or 8
689 static void pskSimBit(uint8_t waveLen
, int *n
, uint8_t clk
, uint8_t *curPhase
, bool phaseChg
)
691 uint8_t *dest
= BigBuf_get_addr();
695 // write phase change
696 for (i
=0; i
< waveLen
/2; i
++){
697 dest
[((*n
)++)] = *curPhase
^1;
699 for (i
=0; i
< waveLen
/2; i
++){
700 dest
[((*n
)++)] = *curPhase
;
704 //write each normal clock wave for the clock duration
705 for (; i
< clk
; i
+=waveLen
){
706 for (idx
=0; idx
<waveLen
/2; idx
++){
707 dest
[((*n
)++)] = *curPhase
;
709 for (idx
=0; idx
<waveLen
/2; idx
++){
710 dest
[((*n
)++)] = *curPhase
^1;
715 // args clock, carrier, invert,
716 void CmdPSKsimTag(uint16_t arg1
, uint16_t arg2
, size_t size
, uint8_t *BitStream
)
720 uint8_t clk
= arg1
>> 8;
721 uint8_t carrier
= arg1
& 0xFF;
722 uint8_t invert
= arg2
& 0xFF;
723 uint8_t phase
= carrier
/2; //extra phase changing bits = 1/2 a carrier wave to change the phase
724 //uint8_t invert = (arg2 >> 8) & 1;
725 uint8_t curPhase
= 0;
727 for (i
=0; i
<size
; i
++){
728 if (BitStream
[i
] == curPhase
){
729 pskSimBit(carrier
, &n
, clk
, &curPhase
, FALSE
);
731 pskSimBit(phase
, &n
, clk
, &curPhase
, TRUE
);
734 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier
, clk
, invert
, n
);
735 Dbprintf("First 64:");
736 uint8_t *dest
= BigBuf_get_addr();
738 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest
[i
],dest
[i
+1],dest
[i
+2],dest
[i
+3],dest
[i
+4],dest
[i
+5],dest
[i
+6],dest
[i
+7],dest
[i
+8],dest
[i
+9],dest
[i
+10],dest
[i
+11],dest
[i
+12],dest
[i
+13],dest
[i
+14],dest
[i
+15]);
740 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest
[i
],dest
[i
+1],dest
[i
+2],dest
[i
+3],dest
[i
+4],dest
[i
+5],dest
[i
+6],dest
[i
+7],dest
[i
+8],dest
[i
+9],dest
[i
+10],dest
[i
+11],dest
[i
+12],dest
[i
+13],dest
[i
+14],dest
[i
+15]);
742 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest
[i
],dest
[i
+1],dest
[i
+2],dest
[i
+3],dest
[i
+4],dest
[i
+5],dest
[i
+6],dest
[i
+7],dest
[i
+8],dest
[i
+9],dest
[i
+10],dest
[i
+11],dest
[i
+12],dest
[i
+13],dest
[i
+14],dest
[i
+15]);
744 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest
[i
],dest
[i
+1],dest
[i
+2],dest
[i
+3],dest
[i
+4],dest
[i
+5],dest
[i
+6],dest
[i
+7],dest
[i
+8],dest
[i
+9],dest
[i
+10],dest
[i
+11],dest
[i
+12],dest
[i
+13],dest
[i
+14],dest
[i
+15]);
748 SimulateTagLowFrequency(n
, 0, ledcontrol
);
754 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
755 void CmdHIDdemodFSK(int findone
, int *high
, int *low
, int ledcontrol
)
757 uint8_t *dest
= BigBuf_get_addr();
758 const size_t sizeOfBigBuff
= BigBuf_max_traceLen();
760 uint32_t hi2
=0, hi
=0, lo
=0;
762 // Configure to go in 125Khz listen mode
763 LFSetupFPGAForADC(95, true);
765 while(!BUTTON_PRESS()) {
768 if (ledcontrol
) LED_A_ON();
770 DoAcquisition_default(-1,true);
772 size
= sizeOfBigBuff
; //variable size will change after demod so re initialize it before use
773 idx
= HIDdemodFSK(dest
, &size
, &hi2
, &hi
, &lo
);
776 // final loop, go over previously decoded manchester data and decode into usable tag ID
777 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
778 if (hi2
!= 0){ //extra large HID tags
779 Dbprintf("TAG ID: %x%08x%08x (%d)",
780 (unsigned int) hi2
, (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF);
781 }else { //standard HID tags <38 bits
782 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
785 uint32_t cardnum
= 0;
786 if (((hi
>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
788 lo2
=(((hi
& 31) << 12) | (lo
>>20)); //get bits 21-37 to check for format len bit
790 while(lo2
> 1){ //find last bit set to 1 (format len bit)
798 cardnum
= (lo
>>1)&0xFFFF;
802 cardnum
= (lo
>>1)&0x7FFFF;
803 fc
= ((hi
&0xF)<<12)|(lo
>>20);
806 cardnum
= (lo
>>1)&0xFFFF;
807 fc
= ((hi
&1)<<15)|(lo
>>17);
810 cardnum
= (lo
>>1)&0xFFFFF;
811 fc
= ((hi
&1)<<11)|(lo
>>21);
814 else { //if bit 38 is not set then 37 bit format is used
819 cardnum
= (lo
>>1)&0x7FFFF;
820 fc
= ((hi
&0xF)<<12)|(lo
>>20);
823 //Dbprintf("TAG ID: %x%08x (%d)",
824 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
825 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
826 (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF,
827 (unsigned int) bitlen
, (unsigned int) fc
, (unsigned int) cardnum
);
830 if (ledcontrol
) LED_A_OFF();
840 DbpString("Stopped");
841 if (ledcontrol
) LED_A_OFF();
844 void CmdEM410xdemod(int findone
, int *high
, int *low
, int ledcontrol
)
846 uint8_t *dest
= BigBuf_get_addr();
848 size_t size
=0, idx
=0;
849 int clk
=0, invert
=0, errCnt
=0, maxErr
=20;
851 // Configure to go in 125Khz listen mode
852 LFSetupFPGAForADC(95, true);
854 while(!BUTTON_PRESS()) {
857 if (ledcontrol
) LED_A_ON();
859 DoAcquisition_default(-1,true);
860 size
= BigBuf_max_traceLen();
861 //Dbprintf("DEBUG: Buffer got");
862 //askdemod and manchester decode
863 errCnt
= askmandemod(dest
, &size
, &clk
, &invert
, maxErr
);
864 //Dbprintf("DEBUG: ASK Got");
868 lo
= Em410xDecode(dest
, &size
, &idx
);
869 //Dbprintf("DEBUG: EM GOT");
871 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
874 (uint32_t)(lo
&0xFFFF),
875 (uint32_t)((lo
>>16LL) & 0xFF),
876 (uint32_t)(lo
& 0xFFFFFF));
879 if (ledcontrol
) LED_A_OFF();
881 *low
=lo
& 0xFFFFFFFF;
885 //Dbprintf("DEBUG: No Tag");
894 DbpString("Stopped");
895 if (ledcontrol
) LED_A_OFF();
898 void CmdIOdemodFSK(int findone
, int *high
, int *low
, int ledcontrol
)
900 uint8_t *dest
= BigBuf_get_addr();
902 uint32_t code
=0, code2
=0;
904 uint8_t facilitycode
=0;
906 // Configure to go in 125Khz listen mode
907 LFSetupFPGAForADC(95, true);
909 while(!BUTTON_PRESS()) {
911 if (ledcontrol
) LED_A_ON();
912 DoAcquisition_default(-1,true);
913 //fskdemod and get start index
915 idx
= IOdemodFSK(dest
, BigBuf_max_traceLen());
920 //0 10 20 30 40 50 60
922 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
923 //-----------------------------------------------------------------------------
924 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
926 //XSF(version)facility:codeone+codetwo
928 if(findone
){ //only print binary if we are doing one
929 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
], dest
[idx
+1], dest
[idx
+2],dest
[idx
+3],dest
[idx
+4],dest
[idx
+5],dest
[idx
+6],dest
[idx
+7],dest
[idx
+8]);
930 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+9], dest
[idx
+10],dest
[idx
+11],dest
[idx
+12],dest
[idx
+13],dest
[idx
+14],dest
[idx
+15],dest
[idx
+16],dest
[idx
+17]);
931 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+18],dest
[idx
+19],dest
[idx
+20],dest
[idx
+21],dest
[idx
+22],dest
[idx
+23],dest
[idx
+24],dest
[idx
+25],dest
[idx
+26]);
932 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+27],dest
[idx
+28],dest
[idx
+29],dest
[idx
+30],dest
[idx
+31],dest
[idx
+32],dest
[idx
+33],dest
[idx
+34],dest
[idx
+35]);
933 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+36],dest
[idx
+37],dest
[idx
+38],dest
[idx
+39],dest
[idx
+40],dest
[idx
+41],dest
[idx
+42],dest
[idx
+43],dest
[idx
+44]);
934 Dbprintf("%d%d%d%d%d%d%d%d %d",dest
[idx
+45],dest
[idx
+46],dest
[idx
+47],dest
[idx
+48],dest
[idx
+49],dest
[idx
+50],dest
[idx
+51],dest
[idx
+52],dest
[idx
+53]);
935 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest
[idx
+54],dest
[idx
+55],dest
[idx
+56],dest
[idx
+57],dest
[idx
+58],dest
[idx
+59],dest
[idx
+60],dest
[idx
+61],dest
[idx
+62],dest
[idx
+63]);
937 code
= bytebits_to_byte(dest
+idx
,32);
938 code2
= bytebits_to_byte(dest
+idx
+32,32);
939 version
= bytebits_to_byte(dest
+idx
+27,8); //14,4
940 facilitycode
= bytebits_to_byte(dest
+idx
+18,8) ;
941 number
= (bytebits_to_byte(dest
+idx
+36,8)<<8)|(bytebits_to_byte(dest
+idx
+45,8)); //36,9
943 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version
,facilitycode
,number
,code
,code2
);
944 // if we're only looking for one tag
946 if (ledcontrol
) LED_A_OFF();
953 version
=facilitycode
=0;
959 DbpString("Stopped");
960 if (ledcontrol
) LED_A_OFF();
963 /*------------------------------
964 * T5555/T5557/T5567 routines
965 *------------------------------
968 /* T55x7 configuration register definitions */
969 #define T55x7_POR_DELAY 0x00000001
970 #define T55x7_ST_TERMINATOR 0x00000008
971 #define T55x7_PWD 0x00000010
972 #define T55x7_MAXBLOCK_SHIFT 5
973 #define T55x7_AOR 0x00000200
974 #define T55x7_PSKCF_RF_2 0
975 #define T55x7_PSKCF_RF_4 0x00000400
976 #define T55x7_PSKCF_RF_8 0x00000800
977 #define T55x7_MODULATION_DIRECT 0
978 #define T55x7_MODULATION_PSK1 0x00001000
979 #define T55x7_MODULATION_PSK2 0x00002000
980 #define T55x7_MODULATION_PSK3 0x00003000
981 #define T55x7_MODULATION_FSK1 0x00004000
982 #define T55x7_MODULATION_FSK2 0x00005000
983 #define T55x7_MODULATION_FSK1a 0x00006000
984 #define T55x7_MODULATION_FSK2a 0x00007000
985 #define T55x7_MODULATION_MANCHESTER 0x00008000
986 #define T55x7_MODULATION_BIPHASE 0x00010000
987 #define T55x7_BITRATE_RF_8 0
988 #define T55x7_BITRATE_RF_16 0x00040000
989 #define T55x7_BITRATE_RF_32 0x00080000
990 #define T55x7_BITRATE_RF_40 0x000C0000
991 #define T55x7_BITRATE_RF_50 0x00100000
992 #define T55x7_BITRATE_RF_64 0x00140000
993 #define T55x7_BITRATE_RF_100 0x00180000
994 #define T55x7_BITRATE_RF_128 0x001C0000
996 /* T5555 (Q5) configuration register definitions */
997 #define T5555_ST_TERMINATOR 0x00000001
998 #define T5555_MAXBLOCK_SHIFT 0x00000001
999 #define T5555_MODULATION_MANCHESTER 0
1000 #define T5555_MODULATION_PSK1 0x00000010
1001 #define T5555_MODULATION_PSK2 0x00000020
1002 #define T5555_MODULATION_PSK3 0x00000030
1003 #define T5555_MODULATION_FSK1 0x00000040
1004 #define T5555_MODULATION_FSK2 0x00000050
1005 #define T5555_MODULATION_BIPHASE 0x00000060
1006 #define T5555_MODULATION_DIRECT 0x00000070
1007 #define T5555_INVERT_OUTPUT 0x00000080
1008 #define T5555_PSK_RF_2 0
1009 #define T5555_PSK_RF_4 0x00000100
1010 #define T5555_PSK_RF_8 0x00000200
1011 #define T5555_USE_PWD 0x00000400
1012 #define T5555_USE_AOR 0x00000800
1013 #define T5555_BITRATE_SHIFT 12
1014 #define T5555_FAST_WRITE 0x00004000
1015 #define T5555_PAGE_SELECT 0x00008000
1018 * Relevant times in microsecond
1019 * To compensate antenna falling times shorten the write times
1020 * and enlarge the gap ones.
1022 #define START_GAP 250
1023 #define WRITE_GAP 160
1024 #define WRITE_0 144 // 192
1025 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
1027 // Write one bit to card
1028 void T55xxWriteBit(int bit
)
1030 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1031 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1032 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1034 SpinDelayUs(WRITE_0
);
1036 SpinDelayUs(WRITE_1
);
1037 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1038 SpinDelayUs(WRITE_GAP
);
1041 // Write one card block in page 0, no lock
1042 void T55xxWriteBlock(uint32_t Data
, uint32_t Block
, uint32_t Pwd
, uint8_t PwdMode
)
1044 //unsigned int i; //enio adjustment 12/10/14
1047 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1048 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1049 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1051 // Give it a bit of time for the resonant antenna to settle.
1052 // And for the tag to fully power up
1055 // Now start writting
1056 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1057 SpinDelayUs(START_GAP
);
1061 T55xxWriteBit(0); //Page 0
1064 for (i
= 0x80000000; i
!= 0; i
>>= 1)
1065 T55xxWriteBit(Pwd
& i
);
1071 for (i
= 0x80000000; i
!= 0; i
>>= 1)
1072 T55xxWriteBit(Data
& i
);
1075 for (i
= 0x04; i
!= 0; i
>>= 1)
1076 T55xxWriteBit(Block
& i
);
1078 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1079 // so wait a little more)
1080 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1081 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1083 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1086 // Read one card block in page 0
1087 void T55xxReadBlock(uint32_t Block
, uint32_t Pwd
, uint8_t PwdMode
)
1089 uint8_t *dest
= BigBuf_get_addr();
1090 //int m=0, i=0; //enio adjustment 12/10/14
1092 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1093 m
= BigBuf_max_traceLen();
1094 // Clear destination buffer before sending the command
1095 memset(dest
, 128, m
);
1096 // Connect the A/D to the peak-detected low-frequency path.
1097 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1098 // Now set up the SSC to get the ADC samples that are now streaming at us.
1102 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1103 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1105 // Give it a bit of time for the resonant antenna to settle.
1106 // And for the tag to fully power up
1109 // Now start writting
1110 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1111 SpinDelayUs(START_GAP
);
1115 T55xxWriteBit(0); //Page 0
1118 for (i
= 0x80000000; i
!= 0; i
>>= 1)
1119 T55xxWriteBit(Pwd
& i
);
1124 for (i
= 0x04; i
!= 0; i
>>= 1)
1125 T55xxWriteBit(Block
& i
);
1127 // Turn field on to read the response
1128 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1129 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1131 // Now do the acquisition
1134 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1135 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1137 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1138 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1139 // we don't care about actual value, only if it's more or less than a
1140 // threshold essentially we capture zero crossings for later analysis
1141 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1147 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1152 // Read card traceability data (page 1)
1153 void T55xxReadTrace(void){
1154 uint8_t *dest
= BigBuf_get_addr();
1157 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1158 m
= BigBuf_max_traceLen();
1159 // Clear destination buffer before sending the command
1160 memset(dest
, 128, m
);
1161 // Connect the A/D to the peak-detected low-frequency path.
1162 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1163 // Now set up the SSC to get the ADC samples that are now streaming at us.
1167 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1168 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1170 // Give it a bit of time for the resonant antenna to settle.
1171 // And for the tag to fully power up
1174 // Now start writting
1175 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1176 SpinDelayUs(START_GAP
);
1180 T55xxWriteBit(1); //Page 1
1182 // Turn field on to read the response
1183 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1184 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1186 // Now do the acquisition
1189 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1190 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1192 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1193 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1199 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1204 /*-------------- Cloning routines -----------*/
1205 // Copy HID id to card and setup block 0 config
1206 void CopyHIDtoT55x7(uint32_t hi2
, uint32_t hi
, uint32_t lo
, uint8_t longFMT
)
1208 int data1
=0, data2
=0, data3
=0, data4
=0, data5
=0, data6
=0; //up to six blocks for long format
1212 // Ensure no more than 84 bits supplied
1214 DbpString("Tags can only have 84 bits.");
1217 // Build the 6 data blocks for supplied 84bit ID
1219 data1
= 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1220 for (int i
=0;i
<4;i
++) {
1221 if (hi2
& (1<<(19-i
)))
1222 data1
|= (1<<(((3-i
)*2)+1)); // 1 -> 10
1224 data1
|= (1<<((3-i
)*2)); // 0 -> 01
1228 for (int i
=0;i
<16;i
++) {
1229 if (hi2
& (1<<(15-i
)))
1230 data2
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1232 data2
|= (1<<((15-i
)*2)); // 0 -> 01
1236 for (int i
=0;i
<16;i
++) {
1237 if (hi
& (1<<(31-i
)))
1238 data3
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1240 data3
|= (1<<((15-i
)*2)); // 0 -> 01
1244 for (int i
=0;i
<16;i
++) {
1245 if (hi
& (1<<(15-i
)))
1246 data4
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1248 data4
|= (1<<((15-i
)*2)); // 0 -> 01
1252 for (int i
=0;i
<16;i
++) {
1253 if (lo
& (1<<(31-i
)))
1254 data5
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1256 data5
|= (1<<((15-i
)*2)); // 0 -> 01
1260 for (int i
=0;i
<16;i
++) {
1261 if (lo
& (1<<(15-i
)))
1262 data6
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1264 data6
|= (1<<((15-i
)*2)); // 0 -> 01
1268 // Ensure no more than 44 bits supplied
1270 DbpString("Tags can only have 44 bits.");
1274 // Build the 3 data blocks for supplied 44bit ID
1277 data1
= 0x1D000000; // load preamble
1279 for (int i
=0;i
<12;i
++) {
1280 if (hi
& (1<<(11-i
)))
1281 data1
|= (1<<(((11-i
)*2)+1)); // 1 -> 10
1283 data1
|= (1<<((11-i
)*2)); // 0 -> 01
1287 for (int i
=0;i
<16;i
++) {
1288 if (lo
& (1<<(31-i
)))
1289 data2
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1291 data2
|= (1<<((15-i
)*2)); // 0 -> 01
1295 for (int i
=0;i
<16;i
++) {
1296 if (lo
& (1<<(15-i
)))
1297 data3
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1299 data3
|= (1<<((15-i
)*2)); // 0 -> 01
1304 // Program the data blocks for supplied ID
1305 // and the block 0 for HID format
1306 T55xxWriteBlock(data1
,1,0,0);
1307 T55xxWriteBlock(data2
,2,0,0);
1308 T55xxWriteBlock(data3
,3,0,0);
1310 if (longFMT
) { // if long format there are 6 blocks
1311 T55xxWriteBlock(data4
,4,0,0);
1312 T55xxWriteBlock(data5
,5,0,0);
1313 T55xxWriteBlock(data6
,6,0,0);
1316 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1317 T55xxWriteBlock(T55x7_BITRATE_RF_50
|
1318 T55x7_MODULATION_FSK2a
|
1319 last_block
<< T55x7_MAXBLOCK_SHIFT
,
1327 void CopyIOtoT55x7(uint32_t hi
, uint32_t lo
, uint8_t longFMT
)
1329 int data1
=0, data2
=0; //up to six blocks for long format
1331 data1
= hi
; // load preamble
1335 // Program the data blocks for supplied ID
1336 // and the block 0 for HID format
1337 T55xxWriteBlock(data1
,1,0,0);
1338 T55xxWriteBlock(data2
,2,0,0);
1341 T55xxWriteBlock(0x00147040,0,0,0);
1347 // Define 9bit header for EM410x tags
1348 #define EM410X_HEADER 0x1FF
1349 #define EM410X_ID_LENGTH 40
1351 void WriteEM410x(uint32_t card
, uint32_t id_hi
, uint32_t id_lo
)
1354 uint64_t id
= EM410X_HEADER
;
1355 uint64_t rev_id
= 0; // reversed ID
1356 int c_parity
[4]; // column parity
1357 int r_parity
= 0; // row parity
1360 // Reverse ID bits given as parameter (for simpler operations)
1361 for (i
= 0; i
< EM410X_ID_LENGTH
; ++i
) {
1363 rev_id
= (rev_id
<< 1) | (id_lo
& 1);
1366 rev_id
= (rev_id
<< 1) | (id_hi
& 1);
1371 for (i
= 0; i
< EM410X_ID_LENGTH
; ++i
) {
1372 id_bit
= rev_id
& 1;
1375 // Don't write row parity bit at start of parsing
1377 id
= (id
<< 1) | r_parity
;
1378 // Start counting parity for new row
1385 // First elements in column?
1387 // Fill out first elements
1388 c_parity
[i
] = id_bit
;
1390 // Count column parity
1391 c_parity
[i
% 4] ^= id_bit
;
1394 id
= (id
<< 1) | id_bit
;
1398 // Insert parity bit of last row
1399 id
= (id
<< 1) | r_parity
;
1401 // Fill out column parity at the end of tag
1402 for (i
= 0; i
< 4; ++i
)
1403 id
= (id
<< 1) | c_parity
[i
];
1408 Dbprintf("Started writing %s tag ...", card
? "T55x7":"T5555");
1412 T55xxWriteBlock((uint32_t)(id
>> 32), 1, 0, 0);
1413 T55xxWriteBlock((uint32_t)id
, 2, 0, 0);
1415 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1417 // Clock rate is stored in bits 8-15 of the card value
1418 clock
= (card
& 0xFF00) >> 8;
1419 Dbprintf("Clock rate: %d", clock
);
1423 clock
= T55x7_BITRATE_RF_32
;
1426 clock
= T55x7_BITRATE_RF_16
;
1429 // A value of 0 is assumed to be 64 for backwards-compatibility
1432 clock
= T55x7_BITRATE_RF_64
;
1435 Dbprintf("Invalid clock rate: %d", clock
);
1439 // Writing configuration for T55x7 tag
1440 T55xxWriteBlock(clock
|
1441 T55x7_MODULATION_MANCHESTER
|
1442 2 << T55x7_MAXBLOCK_SHIFT
,
1446 // Writing configuration for T5555(Q5) tag
1447 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT
|
1448 T5555_MODULATION_MANCHESTER
|
1449 2 << T5555_MAXBLOCK_SHIFT
,
1453 Dbprintf("Tag %s written with 0x%08x%08x\n", card
? "T55x7":"T5555",
1454 (uint32_t)(id
>> 32), (uint32_t)id
);
1457 // Clone Indala 64-bit tag by UID to T55x7
1458 void CopyIndala64toT55x7(int hi
, int lo
)
1461 //Program the 2 data blocks for supplied 64bit UID
1462 // and the block 0 for Indala64 format
1463 T55xxWriteBlock(hi
,1,0,0);
1464 T55xxWriteBlock(lo
,2,0,0);
1465 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1466 T55xxWriteBlock(T55x7_BITRATE_RF_32
|
1467 T55x7_MODULATION_PSK1
|
1468 2 << T55x7_MAXBLOCK_SHIFT
,
1470 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1471 // T5567WriteBlock(0x603E1042,0);
1477 void CopyIndala224toT55x7(int uid1
, int uid2
, int uid3
, int uid4
, int uid5
, int uid6
, int uid7
)
1480 //Program the 7 data blocks for supplied 224bit UID
1481 // and the block 0 for Indala224 format
1482 T55xxWriteBlock(uid1
,1,0,0);
1483 T55xxWriteBlock(uid2
,2,0,0);
1484 T55xxWriteBlock(uid3
,3,0,0);
1485 T55xxWriteBlock(uid4
,4,0,0);
1486 T55xxWriteBlock(uid5
,5,0,0);
1487 T55xxWriteBlock(uid6
,6,0,0);
1488 T55xxWriteBlock(uid7
,7,0,0);
1489 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1490 T55xxWriteBlock(T55x7_BITRATE_RF_32
|
1491 T55x7_MODULATION_PSK1
|
1492 7 << T55x7_MAXBLOCK_SHIFT
,
1494 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1495 // T5567WriteBlock(0x603E10E2,0);
1502 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1503 #define max(x,y) ( x<y ? y:x)
1505 int DemodPCF7931(uint8_t **outBlocks
) {
1506 uint8_t BitStream
[256];
1507 uint8_t Blocks
[8][16];
1508 uint8_t *GraphBuffer
= BigBuf_get_addr();
1509 int GraphTraceLen
= BigBuf_max_traceLen();
1510 int i
, j
, lastval
, bitidx
, half_switch
;
1512 int tolerance
= clock
/ 8;
1513 int pmc
, block_done
;
1514 int lc
, warnings
= 0;
1516 int lmin
=128, lmax
=128;
1519 LFSetupFPGAForADC(95, true);
1520 DoAcquisition_default(0, 0);
1528 /* Find first local max/min */
1529 if(GraphBuffer
[1] > GraphBuffer
[0]) {
1530 while(i
< GraphTraceLen
) {
1531 if( !(GraphBuffer
[i
] > GraphBuffer
[i
-1]) && GraphBuffer
[i
] > lmax
)
1538 while(i
< GraphTraceLen
) {
1539 if( !(GraphBuffer
[i
] < GraphBuffer
[i
-1]) && GraphBuffer
[i
] < lmin
)
1551 for (bitidx
= 0; i
< GraphTraceLen
; i
++)
1553 if ( (GraphBuffer
[i
-1] > GraphBuffer
[i
] && dir
== 1 && GraphBuffer
[i
] > lmax
) || (GraphBuffer
[i
-1] < GraphBuffer
[i
] && dir
== 0 && GraphBuffer
[i
] < lmin
))
1558 // Switch depending on lc length:
1559 // Tolerance is 1/8 of clock rate (arbitrary)
1560 if (abs(lc
-clock
/4) < tolerance
) {
1562 if((i
- pmc
) == lc
) { /* 16T0 was previous one */
1564 i
+= (128+127+16+32+33+16)-1;
1572 } else if (abs(lc
-clock
/2) < tolerance
) {
1574 if((i
- pmc
) == lc
) { /* 16T0 was previous one */
1576 i
+= (128+127+16+32+33)-1;
1581 else if(half_switch
== 1) {
1582 BitStream
[bitidx
++] = 0;
1587 } else if (abs(lc
-clock
) < tolerance
) {
1589 BitStream
[bitidx
++] = 1;
1595 Dbprintf("Error: too many detection errors, aborting.");
1600 if(block_done
== 1) {
1602 for(j
=0; j
<16; j
++) {
1603 Blocks
[num_blocks
][j
] = 128*BitStream
[j
*8+7]+
1604 64*BitStream
[j
*8+6]+
1605 32*BitStream
[j
*8+5]+
1606 16*BitStream
[j
*8+4]+
1618 if(i
< GraphTraceLen
)
1620 if (GraphBuffer
[i
-1] > GraphBuffer
[i
]) dir
=0;
1627 if(num_blocks
== 4) break;
1629 memcpy(outBlocks
, Blocks
, 16*num_blocks
);
1633 int IsBlock0PCF7931(uint8_t *Block
) {
1634 // Assume RFU means 0 :)
1635 if((memcmp(Block
, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block
+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1637 if((memcmp(Block
+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block
[7] == 0) // PAC disabled, can it *really* happen ?
1642 int IsBlock1PCF7931(uint8_t *Block
) {
1643 // Assume RFU means 0 :)
1644 if(Block
[10] == 0 && Block
[11] == 0 && Block
[12] == 0 && Block
[13] == 0)
1645 if((Block
[14] & 0x7f) <= 9 && Block
[15] <= 9)
1653 void ReadPCF7931() {
1654 uint8_t Blocks
[8][17];
1655 uint8_t tmpBlocks
[4][16];
1656 int i
, j
, ind
, ind2
, n
;
1663 memset(Blocks
, 0, 8*17*sizeof(uint8_t));
1666 memset(tmpBlocks
, 0, 4*16*sizeof(uint8_t));
1667 n
= DemodPCF7931((uint8_t**)tmpBlocks
);
1670 if(error
==10 && num_blocks
== 0) {
1671 Dbprintf("Error, no tag or bad tag");
1674 else if (tries
==20 || error
==10) {
1675 Dbprintf("Error reading the tag");
1676 Dbprintf("Here is the partial content");
1681 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1682 tmpBlocks
[i
][0], tmpBlocks
[i
][1], tmpBlocks
[i
][2], tmpBlocks
[i
][3], tmpBlocks
[i
][4], tmpBlocks
[i
][5], tmpBlocks
[i
][6], tmpBlocks
[i
][7],
1683 tmpBlocks
[i
][8], tmpBlocks
[i
][9], tmpBlocks
[i
][10], tmpBlocks
[i
][11], tmpBlocks
[i
][12], tmpBlocks
[i
][13], tmpBlocks
[i
][14], tmpBlocks
[i
][15]);
1685 for(i
=0; i
<n
; i
++) {
1686 if(IsBlock0PCF7931(tmpBlocks
[i
])) {
1688 if(i
< n
-1 && IsBlock1PCF7931(tmpBlocks
[i
+1])) {
1692 memcpy(Blocks
[0], tmpBlocks
[i
], 16);
1693 Blocks
[0][ALLOC
] = 1;
1694 memcpy(Blocks
[1], tmpBlocks
[i
+1], 16);
1695 Blocks
[1][ALLOC
] = 1;
1696 max_blocks
= max((Blocks
[1][14] & 0x7f), Blocks
[1][15]) + 1;
1698 Dbprintf("(dbg) Max blocks: %d", max_blocks
);
1700 // Handle following blocks
1701 for(j
=i
+2, ind2
=2; j
!=i
; j
++, ind2
++, num_blocks
++) {
1704 memcpy(Blocks
[ind2
], tmpBlocks
[j
], 16);
1705 Blocks
[ind2
][ALLOC
] = 1;
1713 for(i
=0; i
<n
; i
++) { // Look for identical block in known blocks
1714 if(memcmp(tmpBlocks
[i
], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1715 for(j
=0; j
<max_blocks
; j
++) {
1716 if(Blocks
[j
][ALLOC
] == 1 && !memcmp(tmpBlocks
[i
], Blocks
[j
], 16)) {
1717 // Found an identical block
1718 for(ind
=i
-1,ind2
=j
-1; ind
>= 0; ind
--,ind2
--) {
1721 if(!Blocks
[ind2
][ALLOC
]) { // Block ind2 not already found
1722 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1723 memcpy(Blocks
[ind2
], tmpBlocks
[ind
], 16);
1724 Blocks
[ind2
][ALLOC
] = 1;
1726 if(num_blocks
== max_blocks
) goto end
;
1729 for(ind
=i
+1,ind2
=j
+1; ind
< n
; ind
++,ind2
++) {
1730 if(ind2
> max_blocks
)
1732 if(!Blocks
[ind2
][ALLOC
]) { // Block ind2 not already found
1733 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1734 memcpy(Blocks
[ind2
], tmpBlocks
[ind
], 16);
1735 Blocks
[ind2
][ALLOC
] = 1;
1737 if(num_blocks
== max_blocks
) goto end
;
1746 if (BUTTON_PRESS()) return;
1747 } while (num_blocks
!= max_blocks
);
1749 Dbprintf("-----------------------------------------");
1750 Dbprintf("Memory content:");
1751 Dbprintf("-----------------------------------------");
1752 for(i
=0; i
<max_blocks
; i
++) {
1753 if(Blocks
[i
][ALLOC
]==1)
1754 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1755 Blocks
[i
][0], Blocks
[i
][1], Blocks
[i
][2], Blocks
[i
][3], Blocks
[i
][4], Blocks
[i
][5], Blocks
[i
][6], Blocks
[i
][7],
1756 Blocks
[i
][8], Blocks
[i
][9], Blocks
[i
][10], Blocks
[i
][11], Blocks
[i
][12], Blocks
[i
][13], Blocks
[i
][14], Blocks
[i
][15]);
1758 Dbprintf("<missing block %d>", i
);
1760 Dbprintf("-----------------------------------------");
1766 //-----------------------------------
1767 // EM4469 / EM4305 routines
1768 //-----------------------------------
1769 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1770 #define FWD_CMD_WRITE 0xA
1771 #define FWD_CMD_READ 0x9
1772 #define FWD_CMD_DISABLE 0x5
1775 uint8_t forwardLink_data
[64]; //array of forwarded bits
1776 uint8_t * forward_ptr
; //ptr for forward message preparation
1777 uint8_t fwd_bit_sz
; //forwardlink bit counter
1778 uint8_t * fwd_write_ptr
; //forwardlink bit pointer
1780 //====================================================================
1781 // prepares command bits
1783 //====================================================================
1784 //--------------------------------------------------------------------
1785 uint8_t Prepare_Cmd( uint8_t cmd
) {
1786 //--------------------------------------------------------------------
1788 *forward_ptr
++ = 0; //start bit
1789 *forward_ptr
++ = 0; //second pause for 4050 code
1791 *forward_ptr
++ = cmd
;
1793 *forward_ptr
++ = cmd
;
1795 *forward_ptr
++ = cmd
;
1797 *forward_ptr
++ = cmd
;
1799 return 6; //return number of emited bits
1802 //====================================================================
1803 // prepares address bits
1805 //====================================================================
1807 //--------------------------------------------------------------------
1808 uint8_t Prepare_Addr( uint8_t addr
) {
1809 //--------------------------------------------------------------------
1811 register uint8_t line_parity
;
1816 *forward_ptr
++ = addr
;
1817 line_parity
^= addr
;
1821 *forward_ptr
++ = (line_parity
& 1);
1823 return 7; //return number of emited bits
1826 //====================================================================
1827 // prepares data bits intreleaved with parity bits
1829 //====================================================================
1831 //--------------------------------------------------------------------
1832 uint8_t Prepare_Data( uint16_t data_low
, uint16_t data_hi
) {
1833 //--------------------------------------------------------------------
1835 register uint8_t line_parity
;
1836 register uint8_t column_parity
;
1837 register uint8_t i
, j
;
1838 register uint16_t data
;
1843 for(i
=0; i
<4; i
++) {
1845 for(j
=0; j
<8; j
++) {
1846 line_parity
^= data
;
1847 column_parity
^= (data
& 1) << j
;
1848 *forward_ptr
++ = data
;
1851 *forward_ptr
++ = line_parity
;
1856 for(j
=0; j
<8; j
++) {
1857 *forward_ptr
++ = column_parity
;
1858 column_parity
>>= 1;
1862 return 45; //return number of emited bits
1865 //====================================================================
1866 // Forward Link send function
1867 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1868 // fwd_bit_count set with number of bits to be sent
1869 //====================================================================
1870 void SendForward(uint8_t fwd_bit_count
) {
1872 fwd_write_ptr
= forwardLink_data
;
1873 fwd_bit_sz
= fwd_bit_count
;
1878 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1879 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1880 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1882 // Give it a bit of time for the resonant antenna to settle.
1883 // And for the tag to fully power up
1886 // force 1st mod pulse (start gap must be longer for 4305)
1887 fwd_bit_sz
--; //prepare next bit modulation
1889 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1890 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1891 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1892 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);//field on
1893 SpinDelayUs(16*8); //16 cycles on (8us each)
1895 // now start writting
1896 while(fwd_bit_sz
-- > 0) { //prepare next bit modulation
1897 if(((*fwd_write_ptr
++) & 1) == 1)
1898 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1900 //These timings work for 4469/4269/4305 (with the 55*8 above)
1901 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1902 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1903 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1904 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);//field on
1905 SpinDelayUs(9*8); //16 cycles on (8us each)
1910 void EM4xLogin(uint32_t Password
) {
1912 uint8_t fwd_bit_count
;
1914 forward_ptr
= forwardLink_data
;
1915 fwd_bit_count
= Prepare_Cmd( FWD_CMD_LOGIN
);
1916 fwd_bit_count
+= Prepare_Data( Password
&0xFFFF, Password
>>16 );
1918 SendForward(fwd_bit_count
);
1920 //Wait for command to complete
1925 void EM4xReadWord(uint8_t Address
, uint32_t Pwd
, uint8_t PwdMode
) {
1927 uint8_t fwd_bit_count
;
1928 uint8_t *dest
= BigBuf_get_addr();
1931 //If password mode do login
1932 if (PwdMode
== 1) EM4xLogin(Pwd
);
1934 forward_ptr
= forwardLink_data
;
1935 fwd_bit_count
= Prepare_Cmd( FWD_CMD_READ
);
1936 fwd_bit_count
+= Prepare_Addr( Address
);
1938 m
= BigBuf_max_traceLen();
1939 // Clear destination buffer before sending the command
1940 memset(dest
, 128, m
);
1941 // Connect the A/D to the peak-detected low-frequency path.
1942 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1943 // Now set up the SSC to get the ADC samples that are now streaming at us.
1946 SendForward(fwd_bit_count
);
1948 // Now do the acquisition
1951 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1952 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1954 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1955 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1960 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1964 void EM4xWriteWord(uint32_t Data
, uint8_t Address
, uint32_t Pwd
, uint8_t PwdMode
) {
1966 uint8_t fwd_bit_count
;
1968 //If password mode do login
1969 if (PwdMode
== 1) EM4xLogin(Pwd
);
1971 forward_ptr
= forwardLink_data
;
1972 fwd_bit_count
= Prepare_Cmd( FWD_CMD_WRITE
);
1973 fwd_bit_count
+= Prepare_Addr( Address
);
1974 fwd_bit_count
+= Prepare_Data( Data
&0xFFFF, Data
>>16 );
1976 SendForward(fwd_bit_count
);
1978 //Wait for write to complete
1980 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off