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CHG: "hf legic write" got a make over in how its called. Now called with 'offset...
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 // 2016 Iceman
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // LEGIC RF simulation code
10 //-----------------------------------------------------------------------------
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 uint8_t bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 // testing calculating in (us) microseconds.
73 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
74 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
75 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
76 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
77 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
78
79 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
80
81 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
82 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
83
84 #define OFFSET_LOG 1024
85
86 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
87
88 #ifndef SHORT_COIL
89 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
90 #endif
91 #ifndef OPEN_COIL
92 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
93 #endif
94 #ifndef LINE_IN
95 # define LINE_IN \
96 do { \
97 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; \
98 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; \
99 } while (0);
100 #endif
101 // Pause pulse, off in 20us / 30ticks,
102 // ONE / ZERO bit pulse,
103 // one == 80us / 120ticks
104 // zero == 40us / 60ticks
105 #ifndef COIL_PULSE
106 # define COIL_PULSE(x) \
107 do { \
108 SHORT_COIL; \
109 WaitTicks( (RWD_TIME_PAUSE) ); \
110 OPEN_COIL; \
111 WaitTicks((x)); \
112 } while (0);
113 #endif
114
115 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
116 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
117 #define LEGIC_CARD_MEMSIZE 1024
118 static uint8_t* cardmem;
119
120 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
121 // Overflow, won't happen
122 if (f->bits >= 31) return;
123
124 f->data |= (bit << f->bits);
125 f->bits++;
126 }
127
128 static void frame_clean(struct legic_frame * const f) {
129 f->data = 0;
130 f->bits = 0;
131 }
132
133 // Prng works when waiting in 99.1us cycles.
134 // and while sending/receiving in bit frames (100, 60)
135 /*static void CalibratePrng( uint32_t time){
136 // Calculate Cycles based on timer 100us
137 uint32_t i = (time - sendFrameStop) / 100 ;
138
139 // substract cycles of finished frames
140 int k = i - legic_prng_count()+1;
141
142 // substract current frame length, rewind to beginning
143 if ( k > 0 )
144 legic_prng_forward(k);
145 }
146 */
147
148 /* Generate Keystream */
149 uint32_t get_key_stream(int skip, int count) {
150
151 int i;
152
153 // Use int to enlarge timer tc to 32bit
154 legic_prng_bc += prng_timer->TC_CV;
155
156 // reset the prng timer.
157
158 /* If skip == -1, forward prng time based */
159 if(skip == -1) {
160 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
161 i -= legic_prng_count(); /* substract cycles of finished frames */
162 i -= count; /* substract current frame length, rewind to beginning */
163 legic_prng_forward(i);
164 } else {
165 legic_prng_forward(skip);
166 }
167
168 i = (count == 6) ? -1 : legic_read_count;
169
170 /* Generate KeyStream */
171 return legic_prng_get_bits(count);
172 }
173
174 /* Send a frame in tag mode, the FPGA must have been set up by
175 * LegicRfSimulate
176 */
177 void frame_send_tag(uint16_t response, uint8_t bits) {
178
179 uint16_t mask = 1;
180
181 /* Bitbang the response */
182 SHORT_COIL;
183 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
184 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
185
186 /* TAG_FRAME_WAIT -> shift by 2 */
187 legic_prng_forward(2);
188 response ^= legic_prng_get_bits(bits);
189
190 /* Wait for the frame start */
191 WaitTicks( TAG_FRAME_WAIT );
192
193 for (; mask < BITMASK(bits); mask <<= 1) {
194 if (response & mask)
195 OPEN_COIL
196 else
197 SHORT_COIL
198 WaitTicks(TAG_BIT_PERIOD);
199 }
200 SHORT_COIL;
201 }
202
203 /* Send a frame in reader mode, the FPGA must have been set up by
204 * LegicRfReader
205 */
206 void frame_sendAsReader(uint32_t data, uint8_t bits){
207
208 uint32_t starttime = GET_TICKS, send = 0;
209 uint16_t mask = 1;
210
211 // xor lsfr onto data.
212 send = data ^ legic_prng_get_bits(bits);
213
214 for (; mask < BITMASK(bits); mask <<= 1) {
215 if (send & mask)
216 COIL_PULSE(RWD_TIME_1)
217 else
218 COIL_PULSE(RWD_TIME_0)
219 }
220
221 // Final pause to mark the end of the frame
222 COIL_PULSE(0);
223
224 // log
225 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1)};
226 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
227 }
228
229 /* Receive a frame from the card in reader emulation mode, the FPGA and
230 * timer must have been set up by LegicRfReader and frame_sendAsReader.
231 *
232 * The LEGIC RF protocol from card to reader does not include explicit
233 * frame start/stop information or length information. The reader must
234 * know beforehand how many bits it wants to receive. (Notably: a card
235 * sending a stream of 0-bits is indistinguishable from no card present.)
236 *
237 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
238 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
239 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
240 * for edges. Count the edges in each bit interval. If they are approximately
241 * 0 this was a 0-bit, if they are approximately equal to the number of edges
242 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
243 * timer that's still running from frame_sendAsReader in order to get a synchronization
244 * with the frame that we just sent.
245 *
246 * FIXME: Because we're relying on the hysteresis to just do the right thing
247 * the range is severely reduced (and you'll probably also need a good antenna).
248 * So this should be fixed some time in the future for a proper receiver.
249 */
250 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
251
252 if ( bits > 32 ) return;
253
254 uint8_t i = bits, edges = 0;
255 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
256 uint32_t old_level = 0;
257 volatile uint32_t level = 0;
258
259 frame_clean(f);
260
261 /* Bitbang the receiver */
262 LINE_IN;
263
264 // calibrate the prng.
265 legic_prng_forward(2);
266 data = legic_prng_get_bits(bits);
267
268 //FIXED time between sending frame and now listening frame. 330us
269 uint32_t starttime = GET_TICKS;
270 // its about 9+9 ticks delay from end-send to here.
271 WaitTicks( 477 );
272
273 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
274
275 while ( i-- ){
276 edges = 0;
277 while ( GET_TICKS < next_bit_at) {
278
279 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
280
281 if (level != old_level)
282 ++edges;
283
284 old_level = level;
285 }
286
287 next_bit_at += TAG_BIT_PERIOD;
288
289 // We expect 42 edges (ONE)
290 if ( edges > 20 )
291 data ^= the_bit;
292
293 the_bit <<= 1;
294 }
295
296 // output
297 f->data = data;
298 f->bits = bits;
299
300 // log
301 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
302 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
303 }
304
305 // Setup pm3 as a Legic Reader
306 static uint32_t setup_phase_reader(uint8_t iv) {
307
308 // Switch on carrier and let the tag charge for 1ms
309 HIGH(GPIO_SSC_DOUT);
310 WaitUS(5000);
311
312 ResetTicks();
313
314 // no keystream yet
315 legic_prng_init(0);
316
317 // send IV handshake
318 frame_sendAsReader(iv, 7);
319
320 // Now both tag and reader has same IV. Prng can start.
321 legic_prng_init(iv);
322
323 frame_receiveAsReader(&current_frame, 6);
324
325 // 292us (438t) - fixed delay before sending ack.
326 // minus log and stuff 100tick?
327 WaitTicks(338);
328 legic_prng_forward(3);
329
330 // Send obsfuscated acknowledgment frame.
331 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
332 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
333 switch ( current_frame.data ) {
334 case 0x0D: frame_sendAsReader(0x19, 6); break;
335 case 0x1D:
336 case 0x3D: frame_sendAsReader(0x39, 6); break;
337 default: break;
338 }
339
340 legic_prng_forward(2);
341 return current_frame.data;
342 }
343
344 static void LegicCommonInit(void) {
345
346 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
347 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
348 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
349
350 /* Bitbang the transmitter */
351 LOW(GPIO_SSC_DOUT);
352 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
353 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
354
355 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
356 cardmem = BigBuf_get_EM_addr();
357 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
358
359 clear_trace();
360 set_tracing(TRUE);
361 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
362
363 StartTicks();
364 }
365
366 // Switch off carrier, make sure tag is reset
367 static void switch_off_tag_rwd(void) {
368 LOW(GPIO_SSC_DOUT);
369 WaitUS(20);
370 WDT_HIT();
371 }
372
373 // calculate crc4 for a legic READ command
374 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
375 crc_clear(&legic_crc);
376 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
377 crc_update(&legic_crc, temp, cmd_sz + 8 );
378 return crc_finish(&legic_crc);
379 }
380
381 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
382
383 uint8_t byte, crc, calcCrc = 0;
384 uint32_t cmd = (index << 1) | LEGIC_READ;
385
386 // 90ticks = 60us (should be 100us but crc calc takes time.)
387 //WaitTicks(330); // 330ticks prng(4) - works
388 WaitTicks(240); // 240ticks prng(3) - works
389
390 frame_sendAsReader(cmd, cmd_sz);
391 frame_receiveAsReader(&current_frame, 12);
392
393 // CRC check.
394 byte = BYTEx(current_frame.data, 0);
395 crc = BYTEx(current_frame.data, 1);
396 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
397
398 if( calcCrc != crc ) {
399 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
400 return -1;
401 }
402
403 legic_prng_forward(3);
404 return byte;
405 }
406
407 /*
408 * - assemble a write_cmd_frame with crc and send it
409 * - wait until the tag sends back an ACK ('1' bit unencrypted)
410 * - forward the prng based on the timing
411 */
412 int legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
413
414 // crc
415 crc_clear(&legic_crc);
416 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
417 crc_update(&legic_crc, index, addr_sz);
418 crc_update(&legic_crc, byte, 8);
419 uint32_t crc = crc_finish(&legic_crc);
420 /*
421 uint32_t crc2 = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
422 if ( crc != crc2 ) {
423 Dbprintf("crc is missmatch");
424 return 1;
425 }
426 */
427 // send write command
428 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
429 |(byte <<(addr_sz+1)) //Data
430 |(index <<1) //index
431 | LEGIC_WRITE); //CMD = Write
432
433 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
434
435 legic_prng_forward(2);
436
437 WaitTicks(330);
438
439 frame_sendAsReader(cmd, cmd_sz);
440
441 /* Bitbang the receiver */
442 LINE_IN;
443
444 int t, old_level = 0, edges = 0;
445 int next_bit_at = 0;
446
447 // ACK 3.6ms = 3600us * 1.5 = 5400ticks.
448 WaitTicks(5400);
449
450 for( t = 0; t < 80; ++t) {
451 edges = 0;
452 next_bit_at += TAG_BIT_PERIOD;
453 while(timer->TC_CV < next_bit_at) {
454 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
455 if(level != old_level)
456 edges++;
457
458 old_level = level;
459 }
460 /* expected are 42 edges (ONE) */
461 if(edges > 20 ) {
462 int t = timer->TC_CV;
463 int c = t / TAG_BIT_PERIOD;
464
465 ResetTimer(timer);
466 legic_prng_forward(c);
467 return 0;
468 }
469 }
470
471 return -1;
472 }
473
474 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
475
476 uint16_t i = 0;
477 uint8_t isOK = 1;
478 legic_card_select_t card;
479
480 LegicCommonInit();
481
482 if ( legic_select_card_iv(&card, iv) ) {
483 isOK = 0;
484 goto OUT;
485 }
486
487 switch_off_tag_rwd();
488
489 if (len + offset >= card.cardsize)
490 len = card.cardsize - offset;
491
492 setup_phase_reader(iv);
493
494 LED_B_ON();
495 while (i < len) {
496 int r = legic_read_byte(offset + i, card.cmdsize);
497
498 if (r == -1 || BUTTON_PRESS()) {
499 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
500 isOK = 0;
501 goto OUT;
502 }
503 cardmem[i++] = r;
504 WDT_HIT();
505 }
506
507 OUT:
508 WDT_HIT();
509 switch_off_tag_rwd();
510 LEDsoff();
511 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
512 return 0;
513 }
514
515 void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
516
517 #define LOWERLIMIT 4
518
519 int r = 0;
520 uint8_t isOK = 1;
521 legic_card_select_t card;
522
523 // uid NOT is writeable.
524 if ( offset <= LOWERLIMIT ) {
525 isOK = 0;
526 goto OUT;
527 }
528
529 LegicCommonInit();
530
531 if ( legic_select_card_iv(&card, iv) ) {
532 isOK = 0;
533 goto OUT;
534 }
535
536 switch_off_tag_rwd();
537
538 if ( len + offset + LOWERLIMIT >= card.cardsize) {
539 isOK = 0;
540 goto OUT;
541 }
542
543 setup_phase_reader(iv);
544
545 LED_B_ON();
546 while( len > 0 ) {
547
548 int r = legic_write_byte( len + offset + LOWERLIMIT, data[len], card.addrsize);
549 if ( r == -1 ) {
550 Dbprintf("operation aborted @ 0x%03.3x", len);
551 isOK = 0;
552 goto OUT;
553 }
554 --len;
555 WDT_HIT();
556 }
557
558 OUT:
559 cmd_send(CMD_ACK, isOK, 0,0,0,0);
560 switch_off_tag_rwd();
561 LEDsoff();
562 }
563
564 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
565
566 if ( p_card == NULL ) return 1;
567
568 p_card->tagtype = setup_phase_reader(iv);
569
570 switch(p_card->tagtype) {
571 case 0x0d:
572 p_card->cmdsize = 6;
573 p_card->addrsize = 5;
574 p_card->cardsize = 22;
575 break;
576 case 0x1d:
577 p_card->cmdsize = 9;
578 p_card->addrsize = 8;
579 p_card->cardsize = 256;
580 break;
581 case 0x3d:
582 p_card->cmdsize = 11;
583 p_card->addrsize = 10;
584 p_card->cardsize = 1024;
585 break;
586 default:
587 p_card->cmdsize = 0;
588 p_card->addrsize = 0;
589 p_card->cardsize = 0;
590 return 2;
591 }
592 return 0;
593 }
594 int legic_select_card(legic_card_select_t *p_card){
595 return legic_select_card_iv(p_card, 0x01);
596 }
597
598 //-----------------------------------------------------------------------------
599 // Work with emulator memory
600 //
601 // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
602 // involved in dealing with emulator memory. But if it is called later, it might
603 // destroy the Emulator Memory.
604 //-----------------------------------------------------------------------------
605 // arg0 = offset
606 // arg1 = num of bytes
607 void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
608 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
609 legic_emlset_mem(data, arg0, arg1);
610 }
611 // arg0 = offset
612 // arg1 = num of bytes
613 void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
614 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
615 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
616 legic_emlget_mem(buf, arg0, arg1);
617 LED_B_ON();
618 cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
619 LED_B_OFF();
620 }
621 void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
622 cardmem = BigBuf_get_EM_addr();
623 memcpy(cardmem + offset, data, numofbytes);
624 }
625 void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
626 cardmem = BigBuf_get_EM_addr();
627 memcpy(data, cardmem + offset, numofbytes);
628 }
629
630 void LegicRfInfo(void){
631
632 int r;
633
634 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
635 legic_card_select_t *card = (legic_card_select_t*) buf;
636
637 LegicCommonInit();
638
639 if ( legic_select_card(card) ) {
640 cmd_send(CMD_ACK,0,0,0,0,0);
641 goto OUT;
642 }
643
644 // read UID bytes
645 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
646 r = legic_read_byte(i, card->cmdsize);
647 if ( r == -1 ) {
648 cmd_send(CMD_ACK,0,0,0,0,0);
649 goto OUT;
650 }
651 card->uid[i] = r & 0xFF;
652 }
653
654 // MCC byte.
655 r = legic_read_byte(4, card->cmdsize);
656 uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
657 if ( r != calc_mcc) {
658 cmd_send(CMD_ACK,0,0,0,0,0);
659 goto OUT;
660 }
661
662 // OK
663 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
664
665 OUT:
666 switch_off_tag_rwd();
667 LEDsoff();
668 }
669
670 /* Handle (whether to respond) a frame in tag mode
671 * Only called when simulating a tag.
672 */
673 static void frame_handle_tag(struct legic_frame const * const f)
674 {
675 // log
676 //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
677 //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
678
679 cardmem = BigBuf_get_EM_addr();
680
681 /* First Part of Handshake (IV) */
682 if(f->bits == 7) {
683
684 LED_C_ON();
685
686 // Reset prng timer
687 ResetTimer(prng_timer);
688
689 // IV from reader.
690 legic_prng_init(f->data);
691
692 // We should have three tagtypes with three different answers.
693 frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */
694
695 legic_state = STATE_IV;
696 legic_read_count = 0;
697 legic_prng_bc = 0;
698 legic_prng_iv = f->data;
699
700
701 ResetTimer(timer);
702 WaitUS(280);
703 return;
704 }
705
706 /* 0x19==??? */
707 if(legic_state == STATE_IV) {
708 uint32_t local_key = get_key_stream(3, 6);
709 int xored = 0x39 ^ local_key;
710 if((f->bits == 6) && (f->data == xored)) {
711 legic_state = STATE_CON;
712
713 ResetTimer(timer);
714 WaitUS(200);
715 return;
716
717 } else {
718 legic_state = STATE_DISCON;
719 LED_C_OFF();
720 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
721 return;
722 }
723 }
724
725 /* Read */
726 if(f->bits == 11) {
727 if(legic_state == STATE_CON) {
728 uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11);
729 uint16_t addr = f->data ^ key;
730 addr >>= 1;
731 uint8_t data = cardmem[addr];
732 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
733
734 legic_read_count++;
735 legic_prng_forward(legic_reqresp_drift);
736
737 frame_send_tag(hash | data, 12);
738 ResetTimer(timer);
739 legic_prng_forward(2);
740 WaitTicks(330);
741 return;
742 }
743 }
744
745 /* Write */
746 if(f->bits == 23) {
747 uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23);
748 uint16_t addr = f->data ^ key;
749 addr >>= 1;
750 addr &= 0x3ff;
751 uint32_t data = f->data ^ key;
752 data >>= 11;
753 data &= 0xff;
754
755 cardmem[addr] = data;
756 /* write command */
757 legic_state = STATE_DISCON;
758 LED_C_OFF();
759 Dbprintf("write - addr: %x, data: %x", addr, data);
760 // should send a ACK within 3.5ms too
761 return;
762 }
763
764 if(legic_state != STATE_DISCON) {
765 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
766 Dbprintf("IV: %03.3x", legic_prng_iv);
767 }
768
769 legic_state = STATE_DISCON;
770 legic_read_count = 0;
771 SpinDelay(10);
772 LED_C_OFF();
773 return;
774 }
775
776 /* Read bit by bit untill full frame is received
777 * Call to process frame end answer
778 */
779 static void emit(int bit) {
780
781 switch (bit) {
782 case 1:
783 frame_append_bit(&current_frame, 1);
784 break;
785 case 0:
786 frame_append_bit(&current_frame, 0);
787 break;
788 default:
789 if(current_frame.bits <= 4) {
790 frame_clean(&current_frame);
791 } else {
792 frame_handle_tag(&current_frame);
793 frame_clean(&current_frame);
794 }
795 WDT_HIT();
796 break;
797 }
798 }
799
800 void LegicRfSimulate(int phase, int frame, int reqresp)
801 {
802 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
803 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
804 * envelope waveform on DIN and should send our response on DOUT.
805 *
806 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
807 * measure the time between two rising edges on DIN, and no encoding on the
808 * subcarrier from card to reader, so we'll just shift out our verbatim data
809 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
810 * seems to be 300us-ish.
811 */
812
813 int old_level = 0, active = 0;
814 legic_state = STATE_DISCON;
815
816 legic_phase_drift = phase;
817 legic_frame_drift = frame;
818 legic_reqresp_drift = reqresp;
819
820 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
821 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
822 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
823
824 /* Bitbang the receiver */
825 LINE_IN;
826
827 // need a way to determine which tagtype we are simulating
828
829 // hook up emulator memory
830 cardmem = BigBuf_get_EM_addr();
831
832 clear_trace();
833 set_tracing(TRUE);
834
835 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
836
837 StartTicks();
838
839 LED_B_ON();
840 DbpString("Starting Legic emulator, press button to end");
841
842 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
843 volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
844
845 uint32_t time = GET_TICKS;
846
847 if (level != old_level) {
848
849 if (level) {
850
851 ResetTicks();
852
853 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
854 /* 1 bit */
855 emit(1);
856 active = 1;
857 LED_A_ON();
858 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
859 /* 0 bit */
860 emit(0);
861 active = 1;
862 LED_A_ON();
863 } else if (active) {
864 /* invalid */
865 emit(-1);
866 active = 0;
867 LED_A_OFF();
868 }
869 }
870 }
871
872 /* Frame end */
873 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
874 emit(-1);
875 active = 0;
876 LED_A_OFF();
877 }
878
879 /*
880 * Disable the counter, Then wait for the clock to acknowledge the
881 * shutdown in its status register. Reading the SR has the
882 * side-effect of clearing any pending state in there.
883 */
884 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
885 StopTicks();
886
887 old_level = level;
888 WDT_HIT();
889 }
890
891 WDT_HIT();
892 switch_off_tag_rwd();
893 LEDsoff();
894 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
895 }
896
897 //-----------------------------------------------------------------------------
898 // Code up a string of octets at layer 2 (including CRC, we don't generate
899 // that here) so that they can be transmitted to the reader. Doesn't transmit
900 // them yet, just leaves them ready to send in ToSend[].
901 //-----------------------------------------------------------------------------
902 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
903 // {
904 // int i;
905
906 // ToSendReset();
907
908 // // Transmit a burst of ones, as the initial thing that lets the
909 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
910 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
911 // // so I will too.
912 // for(i = 0; i < 20; i++) {
913 // ToSendStuffBit(1);
914 // ToSendStuffBit(1);
915 // ToSendStuffBit(1);
916 // ToSendStuffBit(1);
917 // }
918
919 // // Send SOF.
920 // for(i = 0; i < 10; i++) {
921 // ToSendStuffBit(0);
922 // ToSendStuffBit(0);
923 // ToSendStuffBit(0);
924 // ToSendStuffBit(0);
925 // }
926 // for(i = 0; i < 2; i++) {
927 // ToSendStuffBit(1);
928 // ToSendStuffBit(1);
929 // ToSendStuffBit(1);
930 // ToSendStuffBit(1);
931 // }
932
933 // for(i = 0; i < len; i++) {
934 // int j;
935 // uint8_t b = cmd[i];
936
937 // // Start bit
938 // ToSendStuffBit(0);
939 // ToSendStuffBit(0);
940 // ToSendStuffBit(0);
941 // ToSendStuffBit(0);
942
943 // // Data bits
944 // for(j = 0; j < 8; j++) {
945 // if(b & 1) {
946 // ToSendStuffBit(1);
947 // ToSendStuffBit(1);
948 // ToSendStuffBit(1);
949 // ToSendStuffBit(1);
950 // } else {
951 // ToSendStuffBit(0);
952 // ToSendStuffBit(0);
953 // ToSendStuffBit(0);
954 // ToSendStuffBit(0);
955 // }
956 // b >>= 1;
957 // }
958
959 // // Stop bit
960 // ToSendStuffBit(1);
961 // ToSendStuffBit(1);
962 // ToSendStuffBit(1);
963 // ToSendStuffBit(1);
964 // }
965
966 // // Send EOF.
967 // for(i = 0; i < 10; i++) {
968 // ToSendStuffBit(0);
969 // ToSendStuffBit(0);
970 // ToSendStuffBit(0);
971 // ToSendStuffBit(0);
972 // }
973 // for(i = 0; i < 2; i++) {
974 // ToSendStuffBit(1);
975 // ToSendStuffBit(1);
976 // ToSendStuffBit(1);
977 // ToSendStuffBit(1);
978 // }
979
980 // // Convert from last byte pos to length
981 // ToSendMax++;
982 // }
983
984 //-----------------------------------------------------------------------------
985 // The software UART that receives commands from the reader, and its state
986 // variables.
987 //-----------------------------------------------------------------------------
988 /*
989 static struct {
990 enum {
991 STATE_UNSYNCD,
992 STATE_GOT_FALLING_EDGE_OF_SOF,
993 STATE_AWAITING_START_BIT,
994 STATE_RECEIVING_DATA
995 } state;
996 uint16_t shiftReg;
997 int bitCnt;
998 int byteCnt;
999 int byteCntMax;
1000 int posCnt;
1001 uint8_t *output;
1002 } Uart;
1003 */
1004 /* Receive & handle a bit coming from the reader.
1005 *
1006 * This function is called 4 times per bit (every 2 subcarrier cycles).
1007 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1008 *
1009 * LED handling:
1010 * LED A -> ON once we have received the SOF and are expecting the rest.
1011 * LED A -> OFF once we have received EOF or are in error state or unsynced
1012 *
1013 * Returns: true if we received a EOF
1014 * false if we are still waiting for some more
1015 */
1016 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1017 // {
1018 // switch(Uart.state) {
1019 // case STATE_UNSYNCD:
1020 // if(!bit) {
1021 // // we went low, so this could be the beginning of an SOF
1022 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1023 // Uart.posCnt = 0;
1024 // Uart.bitCnt = 0;
1025 // }
1026 // break;
1027
1028 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1029 // Uart.posCnt++;
1030 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1031 // if(bit) {
1032 // if(Uart.bitCnt > 9) {
1033 // // we've seen enough consecutive
1034 // // zeros that it's a valid SOF
1035 // Uart.posCnt = 0;
1036 // Uart.byteCnt = 0;
1037 // Uart.state = STATE_AWAITING_START_BIT;
1038 // LED_A_ON(); // Indicate we got a valid SOF
1039 // } else {
1040 // // didn't stay down long enough
1041 // // before going high, error
1042 // Uart.state = STATE_UNSYNCD;
1043 // }
1044 // } else {
1045 // // do nothing, keep waiting
1046 // }
1047 // Uart.bitCnt++;
1048 // }
1049 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1050 // if(Uart.bitCnt > 12) {
1051 // // Give up if we see too many zeros without
1052 // // a one, too.
1053 // LED_A_OFF();
1054 // Uart.state = STATE_UNSYNCD;
1055 // }
1056 // break;
1057
1058 // case STATE_AWAITING_START_BIT:
1059 // Uart.posCnt++;
1060 // if(bit) {
1061 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1062 // // stayed high for too long between
1063 // // characters, error
1064 // Uart.state = STATE_UNSYNCD;
1065 // }
1066 // } else {
1067 // // falling edge, this starts the data byte
1068 // Uart.posCnt = 0;
1069 // Uart.bitCnt = 0;
1070 // Uart.shiftReg = 0;
1071 // Uart.state = STATE_RECEIVING_DATA;
1072 // }
1073 // break;
1074
1075 // case STATE_RECEIVING_DATA:
1076 // Uart.posCnt++;
1077 // if(Uart.posCnt == 2) {
1078 // // time to sample a bit
1079 // Uart.shiftReg >>= 1;
1080 // if(bit) {
1081 // Uart.shiftReg |= 0x200;
1082 // }
1083 // Uart.bitCnt++;
1084 // }
1085 // if(Uart.posCnt >= 4) {
1086 // Uart.posCnt = 0;
1087 // }
1088 // if(Uart.bitCnt == 10) {
1089 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1090 // {
1091 // // this is a data byte, with correct
1092 // // start and stop bits
1093 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1094 // Uart.byteCnt++;
1095
1096 // if(Uart.byteCnt >= Uart.byteCntMax) {
1097 // // Buffer overflowed, give up
1098 // LED_A_OFF();
1099 // Uart.state = STATE_UNSYNCD;
1100 // } else {
1101 // // so get the next byte now
1102 // Uart.posCnt = 0;
1103 // Uart.state = STATE_AWAITING_START_BIT;
1104 // }
1105 // } else if (Uart.shiftReg == 0x000) {
1106 // // this is an EOF byte
1107 // LED_A_OFF(); // Finished receiving
1108 // Uart.state = STATE_UNSYNCD;
1109 // if (Uart.byteCnt != 0) {
1110 // return TRUE;
1111 // }
1112 // } else {
1113 // // this is an error
1114 // LED_A_OFF();
1115 // Uart.state = STATE_UNSYNCD;
1116 // }
1117 // }
1118 // break;
1119
1120 // default:
1121 // LED_A_OFF();
1122 // Uart.state = STATE_UNSYNCD;
1123 // break;
1124 // }
1125
1126 // return FALSE;
1127 // }
1128 /*
1129
1130 static void UartReset() {
1131 Uart.byteCntMax = 3;
1132 Uart.state = STATE_UNSYNCD;
1133 Uart.byteCnt = 0;
1134 Uart.bitCnt = 0;
1135 Uart.posCnt = 0;
1136 memset(Uart.output, 0x00, 3);
1137 }
1138 */
1139 // static void UartInit(uint8_t *data) {
1140 // Uart.output = data;
1141 // UartReset();
1142 // }
1143
1144 //=============================================================================
1145 // An LEGIC reader. We take layer two commands, code them
1146 // appropriately, and then send them to the tag. We then listen for the
1147 // tag's response, which we leave in the buffer to be demodulated on the
1148 // PC side.
1149 //=============================================================================
1150 /*
1151 static struct {
1152 enum {
1153 DEMOD_UNSYNCD,
1154 DEMOD_PHASE_REF_TRAINING,
1155 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1156 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1157 DEMOD_AWAITING_START_BIT,
1158 DEMOD_RECEIVING_DATA
1159 } state;
1160 int bitCount;
1161 int posCount;
1162 int thisBit;
1163 uint16_t shiftReg;
1164 uint8_t *output;
1165 int len;
1166 int sumI;
1167 int sumQ;
1168 } Demod;
1169 */
1170 /*
1171 * Handles reception of a bit from the tag
1172 *
1173 * This function is called 2 times per bit (every 4 subcarrier cycles).
1174 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1175 *
1176 * LED handling:
1177 * LED C -> ON once we have received the SOF and are expecting the rest.
1178 * LED C -> OFF once we have received EOF or are unsynced
1179 *
1180 * Returns: true if we received a EOF
1181 * false if we are still waiting for some more
1182 *
1183 */
1184
1185 /*
1186 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1187 {
1188 int v = 0;
1189 int ai = ABS(ci);
1190 int aq = ABS(cq);
1191 int halfci = (ai >> 1);
1192 int halfcq = (aq >> 1);
1193
1194 switch(Demod.state) {
1195 case DEMOD_UNSYNCD:
1196
1197 CHECK_FOR_SUBCARRIER()
1198
1199 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1200 Demod.state = DEMOD_PHASE_REF_TRAINING;
1201 Demod.sumI = ci;
1202 Demod.sumQ = cq;
1203 Demod.posCount = 1;
1204 }
1205 break;
1206
1207 case DEMOD_PHASE_REF_TRAINING:
1208 if(Demod.posCount < 8) {
1209
1210 CHECK_FOR_SUBCARRIER()
1211
1212 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1213 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1214 // note: synchronization time > 80 1/fs
1215 Demod.sumI += ci;
1216 Demod.sumQ += cq;
1217 ++Demod.posCount;
1218 } else {
1219 // subcarrier lost
1220 Demod.state = DEMOD_UNSYNCD;
1221 }
1222 } else {
1223 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1224 }
1225 break;
1226
1227 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1228
1229 MAKE_SOFT_DECISION()
1230
1231 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1232 // logic '0' detected
1233 if (v <= 0) {
1234
1235 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1236
1237 // start of SOF sequence
1238 Demod.posCount = 0;
1239 } else {
1240 // maximum length of TR1 = 200 1/fs
1241 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1242 }
1243 ++Demod.posCount;
1244 break;
1245
1246 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1247 ++Demod.posCount;
1248
1249 MAKE_SOFT_DECISION()
1250
1251 if(v > 0) {
1252 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1253 if(Demod.posCount < 10*2) {
1254 Demod.state = DEMOD_UNSYNCD;
1255 } else {
1256 LED_C_ON(); // Got SOF
1257 Demod.state = DEMOD_AWAITING_START_BIT;
1258 Demod.posCount = 0;
1259 Demod.len = 0;
1260 }
1261 } else {
1262 // low phase of SOF too long (> 12 etu)
1263 if(Demod.posCount > 13*2) {
1264 Demod.state = DEMOD_UNSYNCD;
1265 LED_C_OFF();
1266 }
1267 }
1268 break;
1269
1270 case DEMOD_AWAITING_START_BIT:
1271 ++Demod.posCount;
1272
1273 MAKE_SOFT_DECISION()
1274
1275 if(v > 0) {
1276 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1277 if(Demod.posCount > 3*2) {
1278 Demod.state = DEMOD_UNSYNCD;
1279 LED_C_OFF();
1280 }
1281 } else {
1282 // start bit detected
1283 Demod.bitCount = 0;
1284 Demod.posCount = 1; // this was the first half
1285 Demod.thisBit = v;
1286 Demod.shiftReg = 0;
1287 Demod.state = DEMOD_RECEIVING_DATA;
1288 }
1289 break;
1290
1291 case DEMOD_RECEIVING_DATA:
1292
1293 MAKE_SOFT_DECISION()
1294
1295 if(Demod.posCount == 0) {
1296 // first half of bit
1297 Demod.thisBit = v;
1298 Demod.posCount = 1;
1299 } else {
1300 // second half of bit
1301 Demod.thisBit += v;
1302 Demod.shiftReg >>= 1;
1303 // logic '1'
1304 if(Demod.thisBit > 0)
1305 Demod.shiftReg |= 0x200;
1306
1307 ++Demod.bitCount;
1308
1309 if(Demod.bitCount == 10) {
1310
1311 uint16_t s = Demod.shiftReg;
1312
1313 if((s & 0x200) && !(s & 0x001)) {
1314 // stop bit == '1', start bit == '0'
1315 uint8_t b = (s >> 1);
1316 Demod.output[Demod.len] = b;
1317 ++Demod.len;
1318 Demod.state = DEMOD_AWAITING_START_BIT;
1319 } else {
1320 Demod.state = DEMOD_UNSYNCD;
1321 LED_C_OFF();
1322
1323 if(s == 0x000) {
1324 // This is EOF (start, stop and all data bits == '0'
1325 return TRUE;
1326 }
1327 }
1328 }
1329 Demod.posCount = 0;
1330 }
1331 break;
1332
1333 default:
1334 Demod.state = DEMOD_UNSYNCD;
1335 LED_C_OFF();
1336 break;
1337 }
1338 return FALSE;
1339 }
1340 */
1341 /*
1342 // Clear out the state of the "UART" that receives from the tag.
1343 static void DemodReset() {
1344 Demod.len = 0;
1345 Demod.state = DEMOD_UNSYNCD;
1346 Demod.posCount = 0;
1347 Demod.sumI = 0;
1348 Demod.sumQ = 0;
1349 Demod.bitCount = 0;
1350 Demod.thisBit = 0;
1351 Demod.shiftReg = 0;
1352 memset(Demod.output, 0x00, 3);
1353 }
1354
1355 static void DemodInit(uint8_t *data) {
1356 Demod.output = data;
1357 DemodReset();
1358 }
1359 */
1360
1361 /*
1362 * Demodulate the samples we received from the tag, also log to tracebuffer
1363 * quiet: set to 'TRUE' to disable debug output
1364 */
1365
1366 /*
1367 #define LEGIC_DMA_BUFFER_SIZE 256
1368
1369 static void GetSamplesForLegicDemod(int n, bool quiet)
1370 {
1371 int max = 0;
1372 bool gotFrame = FALSE;
1373 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1374 int ci, cq, samples = 0;
1375
1376 BigBuf_free();
1377
1378 // And put the FPGA in the appropriate mode
1379 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1380
1381 // The response (tag -> reader) that we're receiving.
1382 // Set up the demodulator for tag -> reader responses.
1383 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1384
1385 // The DMA buffer, used to stream samples from the FPGA
1386 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1387 int8_t *upTo = dmaBuf;
1388
1389 // Setup and start DMA.
1390 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1391 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1392 return;
1393 }
1394
1395 // Signal field is ON with the appropriate LED:
1396 LED_D_ON();
1397 for(;;) {
1398 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1399 if(behindBy > max) max = behindBy;
1400
1401 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1402 ci = upTo[0];
1403 cq = upTo[1];
1404 upTo += 2;
1405 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1406 upTo = dmaBuf;
1407 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1408 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1409 }
1410 lastRxCounter -= 2;
1411 if(lastRxCounter <= 0)
1412 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1413
1414 samples += 2;
1415
1416 gotFrame = HandleLegicSamplesDemod(ci , cq );
1417 if ( gotFrame )
1418 break;
1419 }
1420
1421 if(samples > n || gotFrame)
1422 break;
1423 }
1424
1425 FpgaDisableSscDma();
1426
1427 if (!quiet && Demod.len == 0) {
1428 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1429 max,
1430 samples,
1431 gotFrame,
1432 Demod.len,
1433 Demod.sumI,
1434 Demod.sumQ
1435 );
1436 }
1437
1438 //Tracing
1439 if (Demod.len > 0) {
1440 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1441 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1442 }
1443 }
1444
1445 */
1446
1447 //-----------------------------------------------------------------------------
1448 // Transmit the command (to the tag) that was placed in ToSend[].
1449 //-----------------------------------------------------------------------------
1450 /*
1451 static void TransmitForLegic(void)
1452 {
1453 int c;
1454
1455 FpgaSetupSsc();
1456
1457 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1458 AT91C_BASE_SSC->SSC_THR = 0xff;
1459
1460 // Signal field is ON with the appropriate Red LED
1461 LED_D_ON();
1462
1463 // Signal we are transmitting with the Green LED
1464 LED_B_ON();
1465 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1466
1467 for(c = 0; c < 10;) {
1468 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1469 AT91C_BASE_SSC->SSC_THR = 0xff;
1470 c++;
1471 }
1472 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1473 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1474 (void)r;
1475 }
1476 WDT_HIT();
1477 }
1478
1479 c = 0;
1480 for(;;) {
1481 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1482 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1483 legic_prng_forward(1); // forward the lfsr
1484 c++;
1485 if(c >= ToSendMax) {
1486 break;
1487 }
1488 }
1489 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1490 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1491 (void)r;
1492 }
1493 WDT_HIT();
1494 }
1495 LED_B_OFF();
1496 }
1497 */
1498
1499 //-----------------------------------------------------------------------------
1500 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1501 // so that it is ready to transmit to the tag using TransmitForLegic().
1502 //-----------------------------------------------------------------------------
1503 /*
1504 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1505 {
1506 int i, j;
1507 uint8_t b;
1508
1509 ToSendReset();
1510
1511 // Send SOF
1512 for(i = 0; i < 7; i++)
1513 ToSendStuffBit(1);
1514
1515
1516 for(i = 0; i < cmdlen; i++) {
1517 // Start bit
1518 ToSendStuffBit(0);
1519
1520 // Data bits
1521 b = cmd[i];
1522 for(j = 0; j < bits; j++) {
1523 if(b & 1) {
1524 ToSendStuffBit(1);
1525 } else {
1526 ToSendStuffBit(0);
1527 }
1528 b >>= 1;
1529 }
1530 }
1531
1532 // Convert from last character reference to length
1533 ++ToSendMax;
1534 }
1535 */
1536 /**
1537 Convenience function to encode, transmit and trace Legic comms
1538 **/
1539 /*
1540 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1541 {
1542 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1543 TransmitForLegic();
1544 if (tracing) {
1545 uint8_t parity[1] = {0x00};
1546 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1547 }
1548 }
1549
1550 */
1551 // Set up LEGIC communication
1552 /*
1553 void ice_legic_setup() {
1554
1555 // standard things.
1556 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1557 BigBuf_free(); BigBuf_Clear_ext(false);
1558 clear_trace();
1559 set_tracing(TRUE);
1560 DemodReset();
1561 UartReset();
1562
1563 // Set up the synchronous serial port
1564 FpgaSetupSsc();
1565
1566 // connect Demodulated Signal to ADC:
1567 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1568
1569 // Signal field is on with the appropriate LED
1570 LED_D_ON();
1571 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1572 SpinDelay(20);
1573 // Start the timer
1574 //StartCountSspClk();
1575
1576 // initalize CRC
1577 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1578
1579 // initalize prng
1580 legic_prng_init(0);
1581 }
1582 */
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