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1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18 #include "iso14443crc.h"
19 #include "iso14443a.h"
20 #include "iso14443b.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23 #include "BigBuf.h"
24 #include "parity.h"
25
26 static uint32_t iso14a_timeout;
27 int rsamples = 0;
28 uint8_t trigger = 0;
29 // the block number for the ISO14443-4 PCB
30 static uint8_t iso14_pcb_blocknum = 0;
31
32 static uint8_t* free_buffer_pointer;
33
34 //
35 // ISO14443 timing:
36 //
37 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
38 #define REQUEST_GUARD_TIME (7000/16 + 1)
39 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
40 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
41 // bool LastCommandWasRequest = FALSE;
42
43 //
44 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
45 //
46 // When the PM acts as reader and is receiving tag data, it takes
47 // 3 ticks delay in the AD converter
48 // 16 ticks until the modulation detector completes and sets curbit
49 // 8 ticks until bit_to_arm is assigned from curbit
50 // 8*16 ticks for the transfer from FPGA to ARM
51 // 4*16 ticks until we measure the time
52 // - 8*16 ticks because we measure the time of the previous transfer
53 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
54
55 // When the PM acts as a reader and is sending, it takes
56 // 4*16 ticks until we can write data to the sending hold register
57 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
58 // 8 ticks until the first transfer starts
59 // 8 ticks later the FPGA samples the data
60 // 1 tick to assign mod_sig_coil
61 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
62
63 // When the PM acts as tag and is receiving it takes
64 // 2 ticks delay in the RF part (for the first falling edge),
65 // 3 ticks for the A/D conversion,
66 // 8 ticks on average until the start of the SSC transfer,
67 // 8 ticks until the SSC samples the first data
68 // 7*16 ticks to complete the transfer from FPGA to ARM
69 // 8 ticks until the next ssp_clk rising edge
70 // 4*16 ticks until we measure the time
71 // - 8*16 ticks because we measure the time of the previous transfer
72 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
73
74 // The FPGA will report its internal sending delay in
75 uint16_t FpgaSendQueueDelay;
76 // the 5 first bits are the number of bits buffered in mod_sig_buf
77 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
78 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
79
80 // When the PM acts as tag and is sending, it takes
81 // 4*16 ticks until we can write data to the sending hold register
82 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
83 // 8 ticks until the first transfer starts
84 // 8 ticks later the FPGA samples the data
85 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
86 // + 1 tick to assign mod_sig_coil
87 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
88
89 // When the PM acts as sniffer and is receiving tag data, it takes
90 // 3 ticks A/D conversion
91 // 14 ticks to complete the modulation detection
92 // 8 ticks (on average) until the result is stored in to_arm
93 // + the delays in transferring data - which is the same for
94 // sniffing reader and tag data and therefore not relevant
95 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
96
97 // When the PM acts as sniffer and is receiving reader data, it takes
98 // 2 ticks delay in analogue RF receiver (for the falling edge of the
99 // start bit, which marks the start of the communication)
100 // 3 ticks A/D conversion
101 // 8 ticks on average until the data is stored in to_arm.
102 // + the delays in transferring data - which is the same for
103 // sniffing reader and tag data and therefore not relevant
104 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
105
106 //variables used for timing purposes:
107 //these are in ssp_clk cycles:
108 static uint32_t NextTransferTime;
109 static uint32_t LastTimeProxToAirStart;
110 static uint32_t LastProxToAirDuration;
111
112 // CARD TO READER - manchester
113 // Sequence D: 11110000 modulation with subcarrier during first half
114 // Sequence E: 00001111 modulation with subcarrier during second half
115 // Sequence F: 00000000 no modulation with subcarrier
116 // READER TO CARD - miller
117 // Sequence X: 00001100 drop after half a period
118 // Sequence Y: 00000000 no drop
119 // Sequence Z: 11000000 drop at start
120 #define SEC_D 0xf0
121 #define SEC_E 0x0f
122 #define SEC_F 0x00
123 #define SEC_X 0x0c
124 #define SEC_Y 0x00
125 #define SEC_Z 0xc0
126
127 void iso14a_set_trigger(bool enable) {
128 trigger = enable;
129 }
130
131 void iso14a_set_timeout(uint32_t timeout) {
132 iso14a_timeout = timeout;
133 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
134 }
135
136 void iso14a_set_ATS_timeout(uint8_t *ats) {
137 uint8_t tb1;
138 uint8_t fwi;
139 uint32_t fwt;
140
141 if (ats[0] > 1) { // there is a format byte T0
142 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
143
144 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
145 tb1 = ats[3];
146 else
147 tb1 = ats[2];
148
149 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
150 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
151 //fwt = 4096 * (1 << fwi);
152
153 iso14a_set_timeout(fwt/(8*16));
154 //iso14a_set_timeout(fwt/128);
155 }
156 }
157 }
158
159 //-----------------------------------------------------------------------------
160 // Generate the parity value for a byte sequence
161 //
162 //-----------------------------------------------------------------------------
163 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
164 uint16_t paritybit_cnt = 0;
165 uint16_t paritybyte_cnt = 0;
166 uint8_t parityBits = 0;
167
168 for (uint16_t i = 0; i < iLen; i++) {
169 // Generate the parity bits
170 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
171 if (paritybit_cnt == 7) {
172 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
173 parityBits = 0; // and advance to next Parity Byte
174 paritybyte_cnt++;
175 paritybit_cnt = 0;
176 } else {
177 paritybit_cnt++;
178 }
179 }
180
181 // save remaining parity bits
182 par[paritybyte_cnt] = parityBits;
183 }
184
185 void AppendCrc14443a(uint8_t* data, int len) {
186 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
187 }
188
189 //=============================================================================
190 // ISO 14443 Type A - Miller decoder
191 //=============================================================================
192 // Basics:
193 // This decoder is used when the PM3 acts as a tag.
194 // The reader will generate "pauses" by temporarily switching of the field.
195 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
196 // The FPGA does a comparison with a threshold and would deliver e.g.:
197 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
198 // The Miller decoder needs to identify the following sequences:
199 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
200 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
201 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
202 // Note 1: the bitstream may start at any time. We therefore need to sync.
203 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
204 //-----------------------------------------------------------------------------
205 static tUart Uart;
206
207 // Lookup-Table to decide if 4 raw bits are a modulation.
208 // We accept the following:
209 // 0001 - a 3 tick wide pause
210 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
211 // 0111 - a 2 tick wide pause shifted left
212 // 1001 - a 2 tick wide pause shifted right
213 const bool Mod_Miller_LUT[] = {
214 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
215 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
216 };
217 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
218 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
219
220 void UartReset() {
221 Uart.state = STATE_UNSYNCD;
222 Uart.bitCount = 0;
223 Uart.len = 0; // number of decoded data bytes
224 Uart.parityLen = 0; // number of decoded parity bytes
225 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
226 Uart.parityBits = 0; // holds 8 parity bits
227 Uart.startTime = 0;
228 Uart.endTime = 0;
229
230 Uart.byteCntMax = 0;
231 Uart.posCnt = 0;
232 Uart.syncBit = 9999;
233 }
234
235 void UartInit(uint8_t *data, uint8_t *parity) {
236 Uart.output = data;
237 Uart.parity = parity;
238 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
239 UartReset();
240 }
241
242 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
243 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
244 Uart.fourBits = (Uart.fourBits << 8) | bit;
245
246 if (Uart.state == STATE_UNSYNCD) { // not yet synced
247 Uart.syncBit = 9999; // not set
248
249 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
250 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
251 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
252
253 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
254 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
255 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
256 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
257 //
258 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
259 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
260
261 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
262 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
263 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
264 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
265 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
266 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
267 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
268 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
269
270 if (Uart.syncBit != 9999) { // found a sync bit
271 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
272 Uart.startTime -= Uart.syncBit;
273 Uart.endTime = Uart.startTime;
274 Uart.state = STATE_START_OF_COMMUNICATION;
275 }
276 } else {
277
278 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
279 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
280 UartReset();
281 } else { // Modulation in first half = Sequence Z = logic "0"
282 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
283 UartReset();
284 } else {
285 Uart.bitCount++;
286 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
287 Uart.state = STATE_MILLER_Z;
288 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
289 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
290 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
291 Uart.parityBits <<= 1; // make room for the parity bit
292 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
293 Uart.bitCount = 0;
294 Uart.shiftReg = 0;
295 if((Uart.len&0x0007) == 0) { // every 8 data bytes
296 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
297 Uart.parityBits = 0;
298 }
299 }
300 }
301 }
302 } else {
303 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
304 Uart.bitCount++;
305 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
306 Uart.state = STATE_MILLER_X;
307 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
308 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
309 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
310 Uart.parityBits <<= 1; // make room for the new parity bit
311 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
312 Uart.bitCount = 0;
313 Uart.shiftReg = 0;
314 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
315 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
316 Uart.parityBits = 0;
317 }
318 }
319 } else { // no modulation in both halves - Sequence Y
320 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
321 Uart.state = STATE_UNSYNCD;
322 Uart.bitCount--; // last "0" was part of EOC sequence
323 Uart.shiftReg <<= 1; // drop it
324 if(Uart.bitCount > 0) { // if we decoded some bits
325 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
326 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
327 Uart.parityBits <<= 1; // add a (void) parity bit
328 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
329 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
330 return TRUE;
331 } else if (Uart.len & 0x0007) { // there are some parity bits to store
332 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
333 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
334 }
335 if (Uart.len) {
336 return TRUE; // we are finished with decoding the raw data sequence
337 } else {
338 UartReset(); // Nothing received - start over
339 }
340 }
341 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
342 UartReset();
343 } else { // a logic "0"
344 Uart.bitCount++;
345 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
346 Uart.state = STATE_MILLER_Y;
347 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
348 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
349 Uart.parityBits <<= 1; // make room for the parity bit
350 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
351 Uart.bitCount = 0;
352 Uart.shiftReg = 0;
353 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
354 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
355 Uart.parityBits = 0;
356 }
357 }
358 }
359 }
360 }
361 }
362 return FALSE; // not finished yet, need more data
363 }
364
365 //=============================================================================
366 // ISO 14443 Type A - Manchester decoder
367 //=============================================================================
368 // Basics:
369 // This decoder is used when the PM3 acts as a reader.
370 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
371 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
372 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
373 // The Manchester decoder needs to identify the following sequences:
374 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
375 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
376 // 8 ticks unmodulated: Sequence F = end of communication
377 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
378 // Note 1: the bitstream may start at any time. We therefore need to sync.
379 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
380 static tDemod Demod;
381
382 // Lookup-Table to decide if 4 raw bits are a modulation.
383 // We accept three or four "1" in any position
384 const bool Mod_Manchester_LUT[] = {
385 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
386 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
387 };
388
389 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
390 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
391
392 void DemodReset() {
393 Demod.state = DEMOD_UNSYNCD;
394 Demod.len = 0; // number of decoded data bytes
395 Demod.parityLen = 0;
396 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
397 Demod.parityBits = 0; //
398 Demod.collisionPos = 0; // Position of collision bit
399 Demod.twoBits = 0xffff; // buffer for 2 Bits
400 Demod.highCnt = 0;
401 Demod.startTime = 0;
402 Demod.endTime = 0;
403 Demod.bitCount = 0;
404 Demod.syncBit = 0xFFFF;
405 Demod.samples = 0;
406 }
407
408 void DemodInit(uint8_t *data, uint8_t *parity) {
409 Demod.output = data;
410 Demod.parity = parity;
411 DemodReset();
412 }
413
414 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
415 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
416 Demod.twoBits = (Demod.twoBits << 8) | bit;
417
418 if (Demod.state == DEMOD_UNSYNCD) {
419
420 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
421 if (Demod.twoBits == 0x0000) {
422 Demod.highCnt++;
423 } else {
424 Demod.highCnt = 0;
425 }
426 } else {
427 Demod.syncBit = 0xFFFF; // not set
428 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
429 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
430 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
431 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
432 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
433 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
434 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
435 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
436 if (Demod.syncBit != 0xFFFF) {
437 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
438 Demod.startTime -= Demod.syncBit;
439 Demod.bitCount = offset; // number of decoded data bits
440 Demod.state = DEMOD_MANCHESTER_DATA;
441 }
442 }
443 } else {
444
445 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
446 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
447 if (!Demod.collisionPos) {
448 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
449 }
450 } // modulation in first half only - Sequence D = 1
451 Demod.bitCount++;
452 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
453 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
454 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
455 Demod.parityBits <<= 1; // make room for the parity bit
456 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
457 Demod.bitCount = 0;
458 Demod.shiftReg = 0;
459 if((Demod.len&0x0007) == 0) { // every 8 data bytes
460 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
461 Demod.parityBits = 0;
462 }
463 }
464 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
465 } else { // no modulation in first half
466 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
467 Demod.bitCount++;
468 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
469 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
470 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
471 Demod.parityBits <<= 1; // make room for the new parity bit
472 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
473 Demod.bitCount = 0;
474 Demod.shiftReg = 0;
475 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
476 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
477 Demod.parityBits = 0;
478 }
479 }
480 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
481 } else { // no modulation in both halves - End of communication
482 if(Demod.bitCount > 0) { // there are some remaining data bits
483 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
484 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
485 Demod.parityBits <<= 1; // add a (void) parity bit
486 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
487 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
488 return TRUE;
489 } else if (Demod.len & 0x0007) { // there are some parity bits to store
490 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
491 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
492 }
493 if (Demod.len) {
494 return TRUE; // we are finished with decoding the raw data sequence
495 } else { // nothing received. Start over
496 DemodReset();
497 }
498 }
499 }
500 }
501 return FALSE; // not finished yet, need more data
502 }
503
504 //=============================================================================
505 // Finally, a `sniffer' for ISO 14443 Type A
506 // Both sides of communication!
507 //=============================================================================
508
509 //-----------------------------------------------------------------------------
510 // Record the sequence of commands sent by the reader to the tag, with
511 // triggering so that we start recording at the point that the tag is moved
512 // near the reader.
513 // "hf 14a sniff"
514 //-----------------------------------------------------------------------------
515 void RAMFUNC SniffIso14443a(uint8_t param) {
516 // param:
517 // bit 0 - trigger from first card answer
518 // bit 1 - trigger from first reader 7-bit request
519 LEDsoff();
520
521 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
522
523 // Allocate memory from BigBuf for some buffers
524 // free all previous allocations first
525 BigBuf_free(); BigBuf_Clear_ext(false);
526 clear_trace();
527 set_tracing(TRUE);
528
529 // The command (reader -> tag) that we're receiving.
530 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
531 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
532
533 // The response (tag -> reader) that we're receiving.
534 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
535 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
536
537 // The DMA buffer, used to stream samples from the FPGA
538 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
539
540 uint8_t *data = dmaBuf;
541 uint8_t previous_data = 0;
542 int maxDataLen = 0;
543 int dataLen = 0;
544 bool TagIsActive = FALSE;
545 bool ReaderIsActive = FALSE;
546
547 // Set up the demodulator for tag -> reader responses.
548 DemodInit(receivedResponse, receivedResponsePar);
549
550 // Set up the demodulator for the reader -> tag commands
551 UartInit(receivedCmd, receivedCmdPar);
552
553 // Setup and start DMA.
554 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
555
556 // We won't start recording the frames that we acquire until we trigger;
557 // a good trigger condition to get started is probably when we see a
558 // response from the tag.
559 // triggered == FALSE -- to wait first for card
560 bool triggered = !(param & 0x03);
561
562 // And now we loop, receiving samples.
563 for(uint32_t rsamples = 0; TRUE; ) {
564
565 if(BUTTON_PRESS()) {
566 DbpString("cancelled by button");
567 break;
568 }
569
570 LED_A_ON();
571 WDT_HIT();
572
573 int register readBufDataP = data - dmaBuf;
574 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
575 if (readBufDataP <= dmaBufDataP){
576 dataLen = dmaBufDataP - readBufDataP;
577 } else {
578 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
579 }
580 // test for length of buffer
581 if(dataLen > maxDataLen) {
582 maxDataLen = dataLen;
583 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
584 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
585 break;
586 }
587 }
588 if(dataLen < 1) continue;
589
590 // primary buffer was stopped( <-- we lost data!
591 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
592 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
593 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
594 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
595 }
596 // secondary buffer sets as primary, secondary buffer was stopped
597 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
598 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
599 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
600 }
601
602 LED_A_OFF();
603
604 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
605
606 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
607 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
608 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
609 LED_C_ON();
610
611 // check - if there is a short 7bit request from reader
612 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
613
614 if(triggered) {
615 if (!LogTrace(receivedCmd,
616 Uart.len,
617 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
618 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
619 Uart.parity,
620 TRUE)) break;
621 }
622 /* And ready to receive another command. */
623 UartReset();
624 /* And also reset the demod code, which might have been */
625 /* false-triggered by the commands from the reader. */
626 DemodReset();
627 LED_B_OFF();
628 }
629 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
630 }
631
632 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
633 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
634 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
635 LED_B_ON();
636
637 if (!LogTrace(receivedResponse,
638 Demod.len,
639 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
640 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
641 Demod.parity,
642 FALSE)) break;
643
644 if ((!triggered) && (param & 0x01)) triggered = TRUE;
645
646 // And ready to receive another response.
647 DemodReset();
648 // And reset the Miller decoder including itS (now outdated) input buffer
649 UartInit(receivedCmd, receivedCmdPar);
650 LED_C_OFF();
651 }
652 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
653 }
654 }
655
656 previous_data = *data;
657 rsamples++;
658 data++;
659 if(data == dmaBuf + DMA_BUFFER_SIZE) {
660 data = dmaBuf;
661 }
662 } // main cycle
663
664 if (MF_DBGLEVEL >= 1) {
665 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
666 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
667 }
668 FpgaDisableSscDma();
669 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
670 LEDsoff();
671 set_tracing(FALSE);
672 }
673
674 //-----------------------------------------------------------------------------
675 // Prepare tag messages
676 //-----------------------------------------------------------------------------
677 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
678 ToSendReset();
679
680 // Correction bit, might be removed when not needed
681 ToSendStuffBit(0);
682 ToSendStuffBit(0);
683 ToSendStuffBit(0);
684 ToSendStuffBit(0);
685 ToSendStuffBit(1); // 1
686 ToSendStuffBit(0);
687 ToSendStuffBit(0);
688 ToSendStuffBit(0);
689
690 // Send startbit
691 ToSend[++ToSendMax] = SEC_D;
692 LastProxToAirDuration = 8 * ToSendMax - 4;
693
694 for(uint16_t i = 0; i < len; i++) {
695 uint8_t b = cmd[i];
696
697 // Data bits
698 for(uint16_t j = 0; j < 8; j++) {
699 if(b & 1) {
700 ToSend[++ToSendMax] = SEC_D;
701 } else {
702 ToSend[++ToSendMax] = SEC_E;
703 }
704 b >>= 1;
705 }
706
707 // Get the parity bit
708 if (parity[i>>3] & (0x80>>(i&0x0007))) {
709 ToSend[++ToSendMax] = SEC_D;
710 LastProxToAirDuration = 8 * ToSendMax - 4;
711 } else {
712 ToSend[++ToSendMax] = SEC_E;
713 LastProxToAirDuration = 8 * ToSendMax;
714 }
715 }
716
717 // Send stopbit
718 ToSend[++ToSendMax] = SEC_F;
719
720 // Convert from last byte pos to length
721 ++ToSendMax;
722 }
723
724 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
725 uint8_t par[MAX_PARITY_SIZE] = {0};
726 GetParity(cmd, len, par);
727 CodeIso14443aAsTagPar(cmd, len, par);
728 }
729
730 static void Code4bitAnswerAsTag(uint8_t cmd) {
731 uint8_t b = cmd;
732
733 ToSendReset();
734
735 // Correction bit, might be removed when not needed
736 ToSendStuffBit(0);
737 ToSendStuffBit(0);
738 ToSendStuffBit(0);
739 ToSendStuffBit(0);
740 ToSendStuffBit(1); // 1
741 ToSendStuffBit(0);
742 ToSendStuffBit(0);
743 ToSendStuffBit(0);
744
745 // Send startbit
746 ToSend[++ToSendMax] = SEC_D;
747
748 for(uint8_t i = 0; i < 4; i++) {
749 if(b & 1) {
750 ToSend[++ToSendMax] = SEC_D;
751 LastProxToAirDuration = 8 * ToSendMax - 4;
752 } else {
753 ToSend[++ToSendMax] = SEC_E;
754 LastProxToAirDuration = 8 * ToSendMax;
755 }
756 b >>= 1;
757 }
758
759 // Send stopbit
760 ToSend[++ToSendMax] = SEC_F;
761
762 // Convert from last byte pos to length
763 ToSendMax++;
764 }
765
766 //-----------------------------------------------------------------------------
767 // Wait for commands from reader
768 // Stop when button is pressed
769 // Or return TRUE when command is captured
770 //-----------------------------------------------------------------------------
771 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
772 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
773 // only, since we are receiving, not transmitting).
774 // Signal field is off with the appropriate LED
775 LED_D_OFF();
776 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
777
778 // Now run a `software UART` on the stream of incoming samples.
779 UartInit(received, parity);
780
781 // clear RXRDY:
782 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
783
784 for(;;) {
785 WDT_HIT();
786
787 if(BUTTON_PRESS()) return FALSE;
788
789 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
790 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
791 if(MillerDecoding(b, 0)) {
792 *len = Uart.len;
793 return TRUE;
794 }
795 }
796 }
797 }
798
799 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
800 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
801 // This will need the following byte array for a modulation sequence
802 // 144 data bits (18 * 8)
803 // 18 parity bits
804 // 2 Start and stop
805 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
806 // 1 just for the case
807 // ----------- +
808 // 166 bytes, since every bit that needs to be send costs us a byte
809 //
810 // Prepare the tag modulation bits from the message
811 CodeIso14443aAsTag(response_info->response,response_info->response_n);
812
813 // Make sure we do not exceed the free buffer space
814 if (ToSendMax > max_buffer_size) {
815 Dbprintf("Out of memory, when modulating bits for tag answer:");
816 Dbhexdump(response_info->response_n,response_info->response,false);
817 return FALSE;
818 }
819
820 // Copy the byte array, used for this modulation to the buffer position
821 memcpy(response_info->modulation,ToSend,ToSendMax);
822
823 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
824 response_info->modulation_n = ToSendMax;
825 response_info->ProxToAirDuration = LastProxToAirDuration;
826 return TRUE;
827 }
828
829 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
830 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
831 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
832 // -> need 273 bytes buffer
833 // 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
834 // 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
835 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
836
837 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
838 // Retrieve and store the current buffer index
839 response_info->modulation = free_buffer_pointer;
840
841 // Determine the maximum size we can use from our buffer
842 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
843
844 // Forward the prepare tag modulation function to the inner function
845 if (prepare_tag_modulation(response_info, max_buffer_size)) {
846 // Update the free buffer offset
847 free_buffer_pointer += ToSendMax;
848 return true;
849 } else {
850 return false;
851 }
852 }
853
854 //-----------------------------------------------------------------------------
855 // Main loop of simulated tag: receive commands from reader, decide what
856 // response to send, and send it.
857 //-----------------------------------------------------------------------------
858 void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
859
860 //Here, we collect CUID, NT, NR, AR, CUID, NT2, NR2, AR2
861 // This can be used in a reader-only attack.
862 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
863 uint8_t ar_nr_collected = 0;
864 uint8_t sak = 0;
865 uint32_t cuid = 0;
866 uint32_t nonce = 0;
867
868 // PACK response to PWD AUTH for EV1/NTAG
869 uint8_t response8[4] = {0,0,0,0};
870 // Counter for EV1/NTAG
871 uint32_t counters[] = {0,0,0};
872
873 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
874 uint8_t response1[] = {0,0};
875
876 switch (tagType) {
877 case 1: { // MIFARE Classic 1k
878 response1[0] = 0x04;
879 sak = 0x08;
880 } break;
881 case 2: { // MIFARE Ultralight
882 response1[0] = 0x44;
883 sak = 0x00;
884 } break;
885 case 3: { // MIFARE DESFire
886 response1[0] = 0x04;
887 response1[1] = 0x03;
888 sak = 0x20;
889 } break;
890 case 4: { // ISO/IEC 14443-4 - javacard (JCOP)
891 response1[0] = 0x04;
892 sak = 0x28;
893 } break;
894 case 5: { // MIFARE TNP3XXX
895 response1[0] = 0x01;
896 response1[1] = 0x0f;
897 sak = 0x01;
898 } break;
899 case 6: { // MIFARE Mini 320b
900 response1[0] = 0x44;
901 sak = 0x09;
902 } break;
903 case 7: { // NTAG
904 response1[0] = 0x44;
905 sak = 0x00;
906 // PACK
907 response8[0] = 0x80;
908 response8[1] = 0x80;
909 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
910 // uid not supplied then get from emulator memory
911 if (data[0]==0) {
912 uint16_t start = 4 * (0+12);
913 uint8_t emdata[8];
914 emlGetMemBt( emdata, start, sizeof(emdata));
915 memcpy(data, emdata, 3); //uid bytes 0-2
916 memcpy(data+3, emdata+4, 4); //uid bytes 3-7
917 flags |= FLAG_7B_UID_IN_DATA;
918 }
919 } break;
920 default: {
921 Dbprintf("Error: unkown tagtype (%d)",tagType);
922 return;
923 } break;
924 }
925
926 // The second response contains the (mandatory) first 24 bits of the UID
927 uint8_t response2[5] = {0x00};
928
929 // For UID size 7,
930 uint8_t response2a[5] = {0x00};
931
932 if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA ) {
933 response2[0] = 0x88; // Cascade Tag marker
934 response2[1] = data[0];
935 response2[2] = data[1];
936 response2[3] = data[2];
937
938 response2a[0] = data[3];
939 response2a[1] = data[4];
940 response2a[2] = data[5];
941 response2a[3] = data[6]; //??
942 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
943
944 // Configure the ATQA and SAK accordingly
945 response1[0] |= 0x40;
946 sak |= 0x04;
947
948 cuid = bytes_to_num(data+3, 4);
949 } else {
950 memcpy(response2, data, 4);
951 // Configure the ATQA and SAK accordingly
952 response1[0] &= 0xBF;
953 sak &= 0xFB;
954 cuid = bytes_to_num(data, 4);
955 }
956
957 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
958 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
959
960 // Prepare the mandatory SAK (for 4 and 7 byte UID)
961 uint8_t response3[3] = {sak, 0x00, 0x00};
962 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
963
964 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
965 uint8_t response3a[3] = {0x00};
966 response3a[0] = sak & 0xFB;
967 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
968
969 uint8_t response5[] = { 0x01, 0x01, 0x01, 0x01 }; // Very random tag nonce
970 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
971 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
972 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
973 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
974 // TC(1) = 0x02: CID supported, NAD not supported
975 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
976
977 // the randon nonce
978 nonce = bytes_to_num(response5, 4);
979
980 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
981 //uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
982 //uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
983 // Prepare CHK_TEARING
984 //uint8_t response9[] = {0xBD,0x90,0x3f};
985
986 #define TAG_RESPONSE_COUNT 10
987 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
988 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
989 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
990 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
991 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
992 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
993 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
994 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
995
996 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
997 };
998 //{ .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
999 //{ .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
1000
1001
1002 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1003 // Such a response is less time critical, so we can prepare them on the fly
1004 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1005 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1006 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1007 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1008 tag_response_info_t dynamic_response_info = {
1009 .response = dynamic_response_buffer,
1010 .response_n = 0,
1011 .modulation = dynamic_modulation_buffer,
1012 .modulation_n = 0
1013 };
1014
1015 // We need to listen to the high-frequency, peak-detected path.
1016 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1017
1018 BigBuf_free_keep_EM();
1019 clear_trace();
1020 set_tracing(TRUE);
1021
1022 // allocate buffers:
1023 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1024 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1025 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1026
1027 // Prepare the responses of the anticollision phase
1028 // there will be not enough time to do this at the moment the reader sends it REQA
1029 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
1030 prepare_allocated_tag_modulation(&responses[i]);
1031
1032 int len = 0;
1033
1034 // To control where we are in the protocol
1035 int order = 0;
1036 int lastorder;
1037
1038 // Just to allow some checks
1039 int happened = 0;
1040 int happened2 = 0;
1041 int cmdsRecvd = 0;
1042 tag_response_info_t* p_response;
1043
1044 LED_A_ON();
1045 for(;;) {
1046 WDT_HIT();
1047
1048 // Clean receive command buffer
1049 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1050 DbpString("Button press");
1051 break;
1052 }
1053
1054 // incease nonce at every command recieved
1055 nonce++;
1056 num_to_bytes(nonce, 4, response5);
1057
1058 p_response = NULL;
1059
1060 // Okay, look at the command now.
1061 lastorder = order;
1062 if(receivedCmd[0] == ISO14443A_CMD_REQA) { // Received a REQUEST
1063 p_response = &responses[0]; order = 1;
1064 } else if(receivedCmd[0] == ISO14443A_CMD_WUPA) { // Received a WAKEUP
1065 p_response = &responses[0]; order = 6;
1066 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received request for UID (cascade 1)
1067 p_response = &responses[1]; order = 2;
1068 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received request for UID (cascade 2)
1069 p_response = &responses[2]; order = 20;
1070 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received a SELECT (cascade 1)
1071 p_response = &responses[3]; order = 3;
1072 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received a SELECT (cascade 2)
1073 p_response = &responses[4]; order = 30;
1074 } else if(receivedCmd[0] == ISO14443A_CMD_READBLOCK) { // Received a (plain) READ
1075 uint8_t block = receivedCmd[1];
1076 // if Ultralight or NTAG (4 byte blocks)
1077 if ( tagType == 7 || tagType == 2 ) {
1078 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1079 uint16_t start = 4 * (block+12);
1080 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1081 emlGetMemBt( emdata, start, 16);
1082 AppendCrc14443a(emdata, 16);
1083 EmSendCmdEx(emdata, sizeof(emdata), false);
1084 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1085 p_response = NULL;
1086 } else { // all other tags (16 byte block tags)
1087 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1088 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1089 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1090 p_response = NULL;
1091 }
1092 } else if(receivedCmd[0] == MIFARE_ULEV1_FASTREAD) { // Received a FAST READ (ranged read)
1093 uint8_t emdata[MAX_FRAME_SIZE];
1094 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1095 int start = (receivedCmd[1]+12) * 4;
1096 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1097 emlGetMemBt( emdata, start, len);
1098 AppendCrc14443a(emdata, len);
1099 EmSendCmdEx(emdata, len+2, false);
1100 p_response = NULL;
1101 } else if(receivedCmd[0] == MIFARE_ULEV1_READSIG && tagType == 7) { // Received a READ SIGNATURE --
1102 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1103 uint16_t start = 4 * 4;
1104 uint8_t emdata[34];
1105 emlGetMemBt( emdata, start, 32);
1106 AppendCrc14443a(emdata, 32);
1107 EmSendCmdEx(emdata, sizeof(emdata), false);
1108 p_response = NULL;
1109 } else if (receivedCmd[0] == MIFARE_ULEV1_READ_CNT && tagType == 7) { // Received a READ COUNTER --
1110 uint8_t index = receivedCmd[1];
1111 uint8_t data[] = {0x00,0x00,0x00,0x14,0xa5};
1112 if ( counters[index] > 0) {
1113 num_to_bytes(counters[index], 3, data);
1114 AppendCrc14443a(data, sizeof(data)-2);
1115 }
1116 EmSendCmdEx(data,sizeof(data),false);
1117 p_response = NULL;
1118 } else if (receivedCmd[0] == MIFARE_ULEV1_INCR_CNT && tagType == 7) { // Received a INC COUNTER --
1119 // number of counter
1120 uint8_t counter = receivedCmd[1];
1121 uint32_t val = bytes_to_num(receivedCmd+2,4);
1122 counters[counter] = val;
1123
1124 // send ACK
1125 uint8_t ack[] = {0x0a};
1126 EmSendCmdEx(ack,sizeof(ack),false);
1127 p_response = NULL;
1128 } else if(receivedCmd[0] == MIFARE_ULEV1_CHECKTEAR && tagType == 7) { // Received a CHECK_TEARING_EVENT --
1129 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1130 uint8_t emdata[3];
1131 uint8_t counter=0;
1132 if (receivedCmd[1]<3) counter = receivedCmd[1];
1133 emlGetMemBt( emdata, 10+counter, 1);
1134 AppendCrc14443a(emdata, sizeof(emdata)-2);
1135 EmSendCmdEx(emdata, sizeof(emdata), false);
1136 p_response = NULL;
1137 } else if(receivedCmd[0] == ISO14443A_CMD_HALT) { // Received a HALT
1138 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1139 p_response = NULL;
1140 } else if(receivedCmd[0] == MIFARE_AUTH_KEYA || receivedCmd[0] == MIFARE_AUTH_KEYB) { // Received an authentication request
1141
1142 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
1143 uint8_t emdata[10];
1144 emlGetMemBt( emdata, 0, 8 );
1145 AppendCrc14443a(emdata, sizeof(emdata)-2);
1146 EmSendCmdEx(emdata, sizeof(emdata), false);
1147 p_response = NULL;
1148 } else {
1149 p_response = &responses[5]; order = 7;
1150 }
1151 } else if(receivedCmd[0] == ISO14443A_CMD_RATS) { // Received a RATS request
1152 if (tagType == 1 || tagType == 2) { // RATS not supported
1153 EmSend4bit(CARD_NACK_NA);
1154 p_response = NULL;
1155 } else {
1156 p_response = &responses[6]; order = 70;
1157 }
1158 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1159 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1160 uint32_t nr = bytes_to_num(receivedCmd,4);
1161 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1162
1163 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
1164 if(ar_nr_collected < 2){
1165 // Avoid duplicates... probably not necessary, nr should vary.
1166 // nr doesn't change in pm3's reading etc. its fixed.
1167 //if(ar_nr_responses[3] != nr){
1168 ar_nr_responses[ar_nr_collected*4] = cuid;
1169 ar_nr_responses[ar_nr_collected*4+1] = nonce;
1170 ar_nr_responses[ar_nr_collected*4+2] = nr;
1171 ar_nr_responses[ar_nr_collected*4+3] = ar;
1172 ar_nr_collected++;
1173 //}
1174 }
1175
1176 if(ar_nr_collected > 1 ) {
1177 if (MF_DBGLEVEL >= 2 && !(flags & FLAG_INTERACTIVE)) {
1178 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
1179 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
1180 ar_nr_responses[0], // CUID
1181 ar_nr_responses[1], // NT
1182 ar_nr_responses[2], // AR1
1183 ar_nr_responses[3], // NR1
1184 ar_nr_responses[6], // AR2
1185 ar_nr_responses[7] // NR2
1186 );
1187 }
1188 uint8_t len = ar_nr_collected*4*4;
1189 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
1190 ar_nr_collected = 0;
1191 memset(ar_nr_responses, 0x00, len);
1192 }
1193 }
1194 } else if (receivedCmd[0] == MIFARE_ULC_AUTH_1 ) { // ULC authentication, or Desfire Authentication
1195 } else if (receivedCmd[0] == MIFARE_ULEV1_AUTH) { // NTAG / EV-1 authentication
1196 if ( tagType == 7 ) {
1197 uint16_t start = 13; //first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
1198 uint8_t emdata[4];
1199 emlGetMemBt( emdata, start, 2);
1200 AppendCrc14443a(emdata, 2);
1201 EmSendCmdEx(emdata, sizeof(emdata), false);
1202 p_response = NULL;
1203 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
1204
1205 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
1206 }
1207 } else {
1208 // Check for ISO 14443A-4 compliant commands, look at left nibble
1209 switch (receivedCmd[0]) {
1210 case 0x02:
1211 case 0x03: { // IBlock (command no CID)
1212 dynamic_response_info.response[0] = receivedCmd[0];
1213 dynamic_response_info.response[1] = 0x90;
1214 dynamic_response_info.response[2] = 0x00;
1215 dynamic_response_info.response_n = 3;
1216 } break;
1217 case 0x0B:
1218 case 0x0A: { // IBlock (command CID)
1219 dynamic_response_info.response[0] = receivedCmd[0];
1220 dynamic_response_info.response[1] = 0x00;
1221 dynamic_response_info.response[2] = 0x90;
1222 dynamic_response_info.response[3] = 0x00;
1223 dynamic_response_info.response_n = 4;
1224 } break;
1225
1226 case 0x1A:
1227 case 0x1B: { // Chaining command
1228 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1229 dynamic_response_info.response_n = 2;
1230 } break;
1231
1232 case 0xaa:
1233 case 0xbb: {
1234 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1235 dynamic_response_info.response_n = 2;
1236 } break;
1237
1238 case 0xBA: { // ping / pong
1239 dynamic_response_info.response[0] = 0xAB;
1240 dynamic_response_info.response[1] = 0x00;
1241 dynamic_response_info.response_n = 2;
1242 } break;
1243
1244 case 0xCA:
1245 case 0xC2: { // Readers sends deselect command
1246 dynamic_response_info.response[0] = 0xCA;
1247 dynamic_response_info.response[1] = 0x00;
1248 dynamic_response_info.response_n = 2;
1249 } break;
1250
1251 default: {
1252 // Never seen this command before
1253 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1254 Dbprintf("Received unknown command (len=%d):",len);
1255 Dbhexdump(len,receivedCmd,false);
1256 // Do not respond
1257 dynamic_response_info.response_n = 0;
1258 } break;
1259 }
1260
1261 if (dynamic_response_info.response_n > 0) {
1262 // Copy the CID from the reader query
1263 dynamic_response_info.response[1] = receivedCmd[1];
1264
1265 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1266 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1267 dynamic_response_info.response_n += 2;
1268
1269 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1270 Dbprintf("Error preparing tag response");
1271 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1272 break;
1273 }
1274 p_response = &dynamic_response_info;
1275 }
1276 }
1277
1278 // Count number of wakeups received after a halt
1279 if(order == 6 && lastorder == 5) { happened++; }
1280
1281 // Count number of other messages after a halt
1282 if(order != 6 && lastorder == 5) { happened2++; }
1283
1284 // comment this limit if you want to simulation longer
1285 if (!tracing) {
1286 Dbprintf("Trace Full. Simulation stopped.");
1287 break;
1288 }
1289 // comment this limit if you want to simulation longer
1290 if(cmdsRecvd > 999) {
1291 DbpString("1000 commands later...");
1292 break;
1293 }
1294 cmdsRecvd++;
1295
1296 if (p_response != NULL) {
1297 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1298 // do the tracing for the previous reader request and this tag answer:
1299 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1300 GetParity(p_response->response, p_response->response_n, par);
1301
1302 EmLogTrace(Uart.output,
1303 Uart.len,
1304 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1305 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1306 Uart.parity,
1307 p_response->response,
1308 p_response->response_n,
1309 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1310 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1311 par);
1312 }
1313 }
1314
1315 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1316 set_tracing(FALSE);
1317 BigBuf_free_keep_EM();
1318 LED_A_OFF();
1319
1320 if (MF_DBGLEVEL >= 4){
1321 Dbprintf("-[ Wake ups after halt [%d]", happened);
1322 Dbprintf("-[ Messages after halt [%d]", happened2);
1323 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
1324 }
1325 }
1326
1327 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1328 // of bits specified in the delay parameter.
1329 void PrepareDelayedTransfer(uint16_t delay) {
1330 delay &= 0x07;
1331 if (!delay) return;
1332
1333 uint8_t bitmask = 0;
1334 uint8_t bits_to_shift = 0;
1335 uint8_t bits_shifted = 0;
1336 uint16_t i = 0;
1337
1338 for (i = 0; i < delay; ++i)
1339 bitmask |= (0x01 << i);
1340
1341 ToSend[++ToSendMax] = 0x00;
1342
1343 for (i = 0; i < ToSendMax; ++i) {
1344 bits_to_shift = ToSend[i] & bitmask;
1345 ToSend[i] = ToSend[i] >> delay;
1346 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1347 bits_shifted = bits_to_shift;
1348 }
1349 }
1350
1351
1352 //-------------------------------------------------------------------------------------
1353 // Transmit the command (to the tag) that was placed in ToSend[].
1354 // Parameter timing:
1355 // if NULL: transfer at next possible time, taking into account
1356 // request guard time and frame delay time
1357 // if == 0: transfer immediately and return time of transfer
1358 // if != 0: delay transfer until time specified
1359 //-------------------------------------------------------------------------------------
1360 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) {
1361 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1362
1363 uint32_t ThisTransferTime = 0;
1364
1365 if (timing) {
1366 if(*timing == 0) { // Measure time
1367 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1368 } else {
1369 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1370 }
1371 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1372 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1373 LastTimeProxToAirStart = *timing;
1374 } else {
1375 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1376
1377 while(GetCountSspClk() < ThisTransferTime);
1378
1379 LastTimeProxToAirStart = ThisTransferTime;
1380 }
1381
1382 // clear TXRDY
1383 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1384
1385 uint16_t c = 0;
1386 for(;;) {
1387 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1388 AT91C_BASE_SSC->SSC_THR = cmd[c];
1389 ++c;
1390 if(c >= len)
1391 break;
1392 }
1393 }
1394
1395 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1396 }
1397
1398 //-----------------------------------------------------------------------------
1399 // Prepare reader command (in bits, support short frames) to send to FPGA
1400 //-----------------------------------------------------------------------------
1401 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1402 {
1403 int i, j;
1404 int last = 0;
1405 uint8_t b;
1406
1407 ToSendReset();
1408
1409 // Start of Communication (Seq. Z)
1410 ToSend[++ToSendMax] = SEC_Z;
1411 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1412
1413 size_t bytecount = nbytes(bits);
1414 // Generate send structure for the data bits
1415 for (i = 0; i < bytecount; i++) {
1416 // Get the current byte to send
1417 b = cmd[i];
1418 size_t bitsleft = MIN((bits-(i*8)),8);
1419
1420 for (j = 0; j < bitsleft; j++) {
1421 if (b & 1) {
1422 // Sequence X
1423 ToSend[++ToSendMax] = SEC_X;
1424 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1425 last = 1;
1426 } else {
1427 if (last == 0) {
1428 // Sequence Z
1429 ToSend[++ToSendMax] = SEC_Z;
1430 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1431 } else {
1432 // Sequence Y
1433 ToSend[++ToSendMax] = SEC_Y;
1434 last = 0;
1435 }
1436 }
1437 b >>= 1;
1438 }
1439
1440 // Only transmit parity bit if we transmitted a complete byte
1441 if (j == 8 && parity != NULL) {
1442 // Get the parity bit
1443 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1444 // Sequence X
1445 ToSend[++ToSendMax] = SEC_X;
1446 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1447 last = 1;
1448 } else {
1449 if (last == 0) {
1450 // Sequence Z
1451 ToSend[++ToSendMax] = SEC_Z;
1452 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1453 } else {
1454 // Sequence Y
1455 ToSend[++ToSendMax] = SEC_Y;
1456 last = 0;
1457 }
1458 }
1459 }
1460 }
1461
1462 // End of Communication: Logic 0 followed by Sequence Y
1463 if (last == 0) {
1464 // Sequence Z
1465 ToSend[++ToSendMax] = SEC_Z;
1466 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1467 } else {
1468 // Sequence Y
1469 ToSend[++ToSendMax] = SEC_Y;
1470 last = 0;
1471 }
1472 ToSend[++ToSendMax] = SEC_Y;
1473
1474 // Convert to length of command:
1475 ++ToSendMax;
1476 }
1477
1478 //-----------------------------------------------------------------------------
1479 // Prepare reader command to send to FPGA
1480 //-----------------------------------------------------------------------------
1481 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity) {
1482 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1483 }
1484
1485 //-----------------------------------------------------------------------------
1486 // Wait for commands from reader
1487 // Stop when button is pressed (return 1) or field was gone (return 2)
1488 // Or return 0 when command is captured
1489 //-----------------------------------------------------------------------------
1490 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) {
1491 *len = 0;
1492
1493 uint32_t timer = 0, vtime = 0;
1494 int analogCnt = 0;
1495 int analogAVG = 0;
1496
1497 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1498 // only, since we are receiving, not transmitting).
1499 // Signal field is off with the appropriate LED
1500 LED_D_OFF();
1501 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1502
1503 // Set ADC to read field strength
1504 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1505 AT91C_BASE_ADC->ADC_MR =
1506 ADC_MODE_PRESCALE(63) |
1507 ADC_MODE_STARTUP_TIME(1) |
1508 ADC_MODE_SAMPLE_HOLD_TIME(15);
1509 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1510 // start ADC
1511 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1512
1513 // Now run a 'software UART' on the stream of incoming samples.
1514 UartInit(received, parity);
1515
1516 // Clear RXRDY:
1517 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1518
1519 for(;;) {
1520 WDT_HIT();
1521
1522 if (BUTTON_PRESS()) return 1;
1523
1524 // test if the field exists
1525 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1526 analogCnt++;
1527 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1528 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1529 if (analogCnt >= 32) {
1530 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1531 vtime = GetTickCount();
1532 if (!timer) timer = vtime;
1533 // 50ms no field --> card to idle state
1534 if (vtime - timer > 50) return 2;
1535 } else
1536 if (timer) timer = 0;
1537 analogCnt = 0;
1538 analogAVG = 0;
1539 }
1540 }
1541
1542 // receive and test the miller decoding
1543 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1544 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1545 if(MillerDecoding(b, 0)) {
1546 *len = Uart.len;
1547 return 0;
1548 }
1549 }
1550 }
1551 }
1552
1553 int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
1554 uint8_t b;
1555 uint16_t i = 0;
1556 uint32_t ThisTransferTime;
1557
1558 // Modulate Manchester
1559 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1560
1561 // include correction bit if necessary
1562 if (Uart.parityBits & 0x01) {
1563 correctionNeeded = TRUE;
1564 }
1565 // 1236, so correction bit needed
1566 i = (correctionNeeded) ? 0 : 1;
1567
1568 // clear receiving shift register and holding register
1569 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1570 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1571 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1572 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1573
1574 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1575 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1576 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1577 if (AT91C_BASE_SSC->SSC_RHR) break;
1578 }
1579
1580 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1581
1582 // Clear TXRDY:
1583 AT91C_BASE_SSC->SSC_THR = SEC_F;
1584
1585 // send cycle
1586 for(; i < respLen; ) {
1587 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1588 AT91C_BASE_SSC->SSC_THR = resp[i++];
1589 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1590 }
1591
1592 if(BUTTON_PRESS()) break;
1593 }
1594
1595 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1596 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
1597 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1598 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1599 AT91C_BASE_SSC->SSC_THR = SEC_F;
1600 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1601 i++;
1602 }
1603 }
1604 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1605 return 0;
1606 }
1607
1608 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1609 Code4bitAnswerAsTag(resp);
1610 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1611 // do the tracing for the previous reader request and this tag answer:
1612 uint8_t par[1] = {0x00};
1613 GetParity(&resp, 1, par);
1614 EmLogTrace(Uart.output,
1615 Uart.len,
1616 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1617 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1618 Uart.parity,
1619 &resp,
1620 1,
1621 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1622 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1623 par);
1624 return res;
1625 }
1626
1627 int EmSend4bit(uint8_t resp){
1628 return EmSend4bitEx(resp, false);
1629 }
1630
1631 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1632 CodeIso14443aAsTagPar(resp, respLen, par);
1633 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1634 // do the tracing for the previous reader request and this tag answer:
1635 EmLogTrace(Uart.output,
1636 Uart.len,
1637 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1638 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1639 Uart.parity,
1640 resp,
1641 respLen,
1642 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1643 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1644 par);
1645 return res;
1646 }
1647
1648 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1649 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1650 GetParity(resp, respLen, par);
1651 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1652 }
1653
1654 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1655 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1656 GetParity(resp, respLen, par);
1657 return EmSendCmdExPar(resp, respLen, false, par);
1658 }
1659
1660 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1661 return EmSendCmdExPar(resp, respLen, false, par);
1662 }
1663
1664 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1665 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1666 {
1667 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1668 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1669 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1670 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1671 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1672 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1673 reader_EndTime = tag_StartTime - exact_fdt;
1674 reader_StartTime = reader_EndTime - reader_modlen;
1675
1676 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1677 return FALSE;
1678 else
1679 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1680
1681 }
1682
1683 //-----------------------------------------------------------------------------
1684 // Wait a certain time for tag response
1685 // If a response is captured return TRUE
1686 // If it takes too long return FALSE
1687 //-----------------------------------------------------------------------------
1688 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) {
1689 uint32_t c = 0x00;
1690
1691 // Set FPGA mode to "reader listen mode", no modulation (listen
1692 // only, since we are receiving, not transmitting).
1693 // Signal field is on with the appropriate LED
1694 LED_D_ON();
1695 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1696
1697 // Now get the answer from the card
1698 DemodInit(receivedResponse, receivedResponsePar);
1699
1700 // clear RXRDY:
1701 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1702
1703 for(;;) {
1704 WDT_HIT();
1705
1706 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1707 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1708 if(ManchesterDecoding(b, offset, 0)) {
1709 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1710 return TRUE;
1711 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1712 return FALSE;
1713 }
1714 }
1715 }
1716 }
1717
1718 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) {
1719
1720 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1721 // Send command to tag
1722 TransmitFor14443a(ToSend, ToSendMax, timing);
1723 if(trigger) LED_A_ON();
1724
1725 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
1726 }
1727
1728 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) {
1729 ReaderTransmitBitsPar(frame, len*8, par, timing);
1730 }
1731
1732 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) {
1733 // Generate parity and redirect
1734 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1735 GetParity(frame, len/8, par);
1736 ReaderTransmitBitsPar(frame, len, par, timing);
1737 }
1738
1739 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) {
1740 // Generate parity and redirect
1741 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1742 GetParity(frame, len, par);
1743 ReaderTransmitBitsPar(frame, len*8, par, timing);
1744 }
1745
1746 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) {
1747 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1748 return FALSE;
1749 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1750 return Demod.len;
1751 }
1752
1753 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
1754 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1755 return FALSE;
1756 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1757 return Demod.len;
1758 }
1759
1760 // performs iso14443a anticollision (optional) and card select procedure
1761 // fills the uid and cuid pointer unless NULL
1762 // fills the card info record unless NULL
1763 // if anticollision is false, then the UID must be provided in uid_ptr[]
1764 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1765 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
1766 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1767 uint8_t sel_all[] = { 0x93,0x20 };
1768 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1769 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1770 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1771 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1772 byte_t uid_resp[4] = {0};
1773 size_t uid_resp_len = 0;
1774
1775 uint8_t sak = 0x04; // cascade uid
1776 int cascade_level = 0;
1777 int len;
1778
1779 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1780 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
1781
1782 // Receive the ATQA
1783 if(!ReaderReceive(resp, resp_par)) return 0;
1784
1785 if(p_hi14a_card) {
1786 memcpy(p_hi14a_card->atqa, resp, 2);
1787 p_hi14a_card->uidlen = 0;
1788 memset(p_hi14a_card->uid,0,10);
1789 }
1790
1791 if (anticollision) {
1792 // clear uid
1793 if (uid_ptr)
1794 memset(uid_ptr,0,10);
1795 }
1796
1797 // check for proprietary anticollision:
1798 if ((resp[0] & 0x1F) == 0) return 3;
1799
1800 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1801 // which case we need to make a cascade 2 request and select - this is a long UID
1802 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1803 for(; sak & 0x04; cascade_level++) {
1804 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1805 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1806
1807 if (anticollision) {
1808 // SELECT_ALL
1809 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1810 if (!ReaderReceive(resp, resp_par)) return 0;
1811
1812 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1813 memset(uid_resp, 0, 4);
1814 uint16_t uid_resp_bits = 0;
1815 uint16_t collision_answer_offset = 0;
1816 // anti-collision-loop:
1817 while (Demod.collisionPos) {
1818 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1819 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1820 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1821 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1822 }
1823 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1824 uid_resp_bits++;
1825 // construct anticollosion command:
1826 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1827 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1828 sel_uid[2+i] = uid_resp[i];
1829 }
1830 collision_answer_offset = uid_resp_bits%8;
1831 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1832 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1833 }
1834 // finally, add the last bits and BCC of the UID
1835 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1836 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1837 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1838 }
1839
1840 } else { // no collision, use the response to SELECT_ALL as current uid
1841 memcpy(uid_resp, resp, 4);
1842 }
1843
1844 } else {
1845 if (cascade_level < num_cascades - 1) {
1846 uid_resp[0] = 0x88;
1847 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1848 } else {
1849 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1850 }
1851 }
1852 uid_resp_len = 4;
1853
1854 // calculate crypto UID. Always use last 4 Bytes.
1855 if(cuid_ptr)
1856 *cuid_ptr = bytes_to_num(uid_resp, 4);
1857
1858 // Construct SELECT UID command
1859 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1860 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
1861 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1862 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1863 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1864
1865 // Receive the SAK
1866 if (!ReaderReceive(resp, resp_par)) return 0;
1867
1868 sak = resp[0];
1869
1870 // Test if more parts of the uid are coming
1871 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1872 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1873 // http://www.nxp.com/documents/application_note/AN10927.pdf
1874 uid_resp[0] = uid_resp[1];
1875 uid_resp[1] = uid_resp[2];
1876 uid_resp[2] = uid_resp[3];
1877 uid_resp_len = 3;
1878 }
1879
1880 if(uid_ptr && anticollision)
1881 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1882
1883 if(p_hi14a_card) {
1884 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1885 p_hi14a_card->uidlen += uid_resp_len;
1886 }
1887 }
1888
1889 if(p_hi14a_card) {
1890 p_hi14a_card->sak = sak;
1891 p_hi14a_card->ats_len = 0;
1892 }
1893
1894 // non iso14443a compliant tag
1895 if( (sak & 0x20) == 0) return 2;
1896
1897 // Request for answer to select
1898 AppendCrc14443a(rats, 2);
1899 ReaderTransmit(rats, sizeof(rats), NULL);
1900
1901 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1902
1903 if(p_hi14a_card) {
1904 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1905 p_hi14a_card->ats_len = len;
1906 }
1907
1908 // reset the PCB block number
1909 iso14_pcb_blocknum = 0;
1910
1911 // set default timeout based on ATS
1912 iso14a_set_ATS_timeout(resp);
1913
1914 return 1;
1915 }
1916
1917 void iso14443a_setup(uint8_t fpga_minor_mode) {
1918 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1919 // Set up the synchronous serial port
1920 FpgaSetupSsc();
1921 // connect Demodulated Signal to ADC:
1922 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1923
1924 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1925
1926 LED_D_OFF();
1927 // Signal field is on with the appropriate LED
1928 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
1929 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
1930 LED_D_ON();
1931
1932 // Prepare the demodulation functions
1933 DemodReset();
1934 UartReset();
1935
1936 iso14a_set_timeout(10*106); // 10ms default
1937
1938 //NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
1939 NextTransferTime = DELAY_ARM2AIR_AS_READER << 1;
1940
1941 // Start the timer
1942 StartCountSspClk();
1943 }
1944
1945 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1946 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1947 uint8_t real_cmd[cmd_len+4];
1948 real_cmd[0] = 0x0a; //I-Block
1949 // put block number into the PCB
1950 real_cmd[0] |= iso14_pcb_blocknum;
1951 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1952 memcpy(real_cmd+2, cmd, cmd_len);
1953 AppendCrc14443a(real_cmd,cmd_len+2);
1954
1955 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1956 size_t len = ReaderReceive(data, parity);
1957 //DATA LINK ERROR
1958 if (!len) return 0;
1959
1960 uint8_t *data_bytes = (uint8_t *) data;
1961
1962 // if we received an I- or R(ACK)-Block with a block number equal to the
1963 // current block number, toggle the current block number
1964 if (len >= 4 // PCB+CID+CRC = 4 bytes
1965 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1966 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1967 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1968 {
1969 iso14_pcb_blocknum ^= 1;
1970 }
1971
1972 return len;
1973 }
1974
1975 //-----------------------------------------------------------------------------
1976 // Read an ISO 14443a tag. Send out commands and store answers.
1977 //
1978 //-----------------------------------------------------------------------------
1979 void ReaderIso14443a(UsbCommand *c) {
1980 iso14a_command_t param = c->arg[0];
1981 size_t len = c->arg[1] & 0xffff;
1982 size_t lenbits = c->arg[1] >> 16;
1983 uint32_t timeout = c->arg[2];
1984 uint8_t *cmd = c->d.asBytes;
1985 uint32_t arg0 = 0;
1986 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
1987 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1988
1989 if (param & ISO14A_CONNECT)
1990 clear_trace();
1991
1992 set_tracing(TRUE);
1993
1994 if (param & ISO14A_REQUEST_TRIGGER)
1995 iso14a_set_trigger(TRUE);
1996
1997 if (param & ISO14A_CONNECT) {
1998 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1999 if(!(param & ISO14A_NO_SELECT)) {
2000 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
2001 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
2002 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
2003 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
2004 if ( arg0 == 0 ) return;
2005 }
2006 }
2007
2008 if (param & ISO14A_SET_TIMEOUT)
2009 iso14a_set_timeout(timeout);
2010
2011 if (param & ISO14A_APDU) {
2012 arg0 = iso14_apdu(cmd, len, buf);
2013 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2014 }
2015
2016 if (param & ISO14A_RAW) {
2017 if(param & ISO14A_APPEND_CRC) {
2018 if(param & ISO14A_TOPAZMODE) {
2019 AppendCrc14443b(cmd,len);
2020 } else {
2021 AppendCrc14443a(cmd,len);
2022 }
2023 len += 2;
2024 if (lenbits) lenbits += 16;
2025 }
2026 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2027 if(param & ISO14A_TOPAZMODE) {
2028 int bits_to_send = lenbits;
2029 uint16_t i = 0;
2030 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2031 bits_to_send -= 7;
2032 while (bits_to_send > 0) {
2033 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2034 bits_to_send -= 8;
2035 }
2036 } else {
2037 GetParity(cmd, lenbits/8, par);
2038 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2039 }
2040 } else { // want to send complete bytes only
2041 if(param & ISO14A_TOPAZMODE) {
2042 uint16_t i = 0;
2043 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2044 while (i < len) {
2045 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2046 }
2047 } else {
2048 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2049 }
2050 }
2051 arg0 = ReaderReceive(buf, par);
2052 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2053 }
2054
2055 if (param & ISO14A_REQUEST_TRIGGER)
2056 iso14a_set_trigger(FALSE);
2057
2058 if (param & ISO14A_NO_DISCONNECT)
2059 return;
2060
2061 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2062 set_tracing(FALSE);
2063 LEDsoff();
2064 }
2065
2066 // Determine the distance between two nonces.
2067 // Assume that the difference is small, but we don't know which is first.
2068 // Therefore try in alternating directions.
2069 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2070
2071 if (nt1 == nt2) return 0;
2072
2073 uint16_t i;
2074 uint32_t nttmp1 = nt1;
2075 uint32_t nttmp2 = nt2;
2076
2077 for (i = 1; i < (32768/8); ++i) {
2078 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i;
2079 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -i;
2080
2081 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+1;
2082 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+1);
2083 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+2;
2084 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+2);
2085 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+3;
2086 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+3);
2087 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+4;
2088 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+4);
2089 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+5;
2090 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+5);
2091 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+6;
2092 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+6);
2093 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+7;
2094 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+7);
2095 }
2096 // either nt1 or nt2 are invalid nonces
2097 return(-99999);
2098 }
2099
2100 //-----------------------------------------------------------------------------
2101 // Recover several bits of the cypher stream. This implements (first stages of)
2102 // the algorithm described in "The Dark Side of Security by Obscurity and
2103 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2104 // (article by Nicolas T. Courtois, 2009)
2105 //-----------------------------------------------------------------------------
2106 void ReaderMifare(bool first_try, uint8_t block ) {
2107 uint8_t mf_auth[] = { MIFARE_AUTH_KEYA, block, 0x00, 0x00 };
2108 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2109 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2110 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2111 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
2112 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2113 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
2114 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2115 byte_t nt_diff = 0;
2116 uint32_t nt = 0;
2117 uint32_t previous_nt = 0;
2118 uint32_t cuid = 0;
2119
2120 int32_t catch_up_cycles = 0;
2121 int32_t last_catch_up = 0;
2122 int32_t isOK = 0;
2123 int32_t nt_distance = 0;
2124
2125 uint16_t elapsed_prng_sequences = 1;
2126 uint16_t consecutive_resyncs = 0;
2127 uint16_t unexpected_random = 0;
2128 uint16_t sync_tries = 0;
2129
2130 // static variables here, is re-used in the next call
2131 static uint32_t nt_attacked = 0;
2132 static uint32_t sync_time = 0;
2133 static uint32_t sync_cycles = 0;
2134 static uint8_t par_low = 0;
2135 static uint8_t mf_nr_ar3 = 0;
2136
2137 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2138 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2139 #define MAX_SYNC_TRIES 32
2140
2141 BigBuf_free(); BigBuf_Clear_ext(false);
2142 clear_trace();
2143 set_tracing(TRUE);
2144 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2145
2146 AppendCrc14443a(mf_auth, 2);
2147
2148 if (first_try) {
2149 sync_time = GetCountSspClk() & 0xfffffff8;
2150 sync_cycles = PRNG_SEQUENCE_LENGTH + 1130; //65536; //0x10000 // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2151 mf_nr_ar3 = 0;
2152 nt_attacked = 0;
2153 par_low = 0;
2154 } else {
2155 // we were unsuccessful on a previous call.
2156 // Try another READER nonce (first 3 parity bits remain the same)
2157 ++mf_nr_ar3;
2158 mf_nr_ar[3] = mf_nr_ar3;
2159 par[0] = par_low;
2160 }
2161
2162 bool have_uid = FALSE;
2163 uint8_t cascade_levels = 0;
2164
2165 LED_C_ON();
2166 uint16_t i;
2167 for(i = 0; TRUE; ++i) {
2168
2169 WDT_HIT();
2170
2171 // Test if the action was cancelled
2172 if(BUTTON_PRESS()) {
2173 isOK = -1;
2174 break;
2175 }
2176
2177 // this part is from Piwi's faster nonce collecting part in Hardnested.
2178 if (!have_uid) { // need a full select cycle to get the uid first
2179 iso14a_card_select_t card_info;
2180 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2181 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2182 break;
2183 }
2184 switch (card_info.uidlen) {
2185 case 4 : cascade_levels = 1; break;
2186 case 7 : cascade_levels = 2; break;
2187 case 10: cascade_levels = 3; break;
2188 default: break;
2189 }
2190 have_uid = TRUE;
2191 } else { // no need for anticollision. We can directly select the card
2192 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2193 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2194 continue;
2195 }
2196 }
2197
2198 // Sending timeslot of ISO14443a frame
2199 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
2200 catch_up_cycles = 0;
2201
2202 // if we missed the sync time already, advance to the next nonce repeat
2203 while( GetCountSspClk() > sync_time) {
2204 ++elapsed_prng_sequences;
2205 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2206 }
2207
2208 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2209 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2210
2211 // Receive the (4 Byte) "random" nonce from TAG
2212 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
2213 continue;
2214
2215 previous_nt = nt;
2216 nt = bytes_to_num(receivedAnswer, 4);
2217
2218 // Transmit reader nonce with fake par
2219 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2220
2221 WDT_HIT();
2222 LED_B_ON();
2223 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2224
2225 nt_distance = dist_nt(previous_nt, nt);
2226
2227 // if no distance between, then we are in sync.
2228 if (nt_distance == 0) {
2229 nt_attacked = nt;
2230 } else {
2231 if (nt_distance == -99999) { // invalid nonce received
2232 ++unexpected_random;
2233 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2234 isOK = -3; // Card has an unpredictable PRNG. Give up
2235 break;
2236 } else {
2237 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2238 LED_B_OFF();
2239 continue; // continue trying...
2240 }
2241 }
2242
2243 if (++sync_tries > MAX_SYNC_TRIES) {
2244 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2245 break;
2246 }
2247
2248 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
2249
2250 if (sync_cycles <= 0)
2251 sync_cycles += PRNG_SEQUENCE_LENGTH;
2252
2253 if (MF_DBGLEVEL >= 4)
2254 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2255
2256 LED_B_OFF();
2257 continue;
2258 }
2259 }
2260 LED_B_OFF();
2261
2262 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2263
2264 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
2265 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2266 catch_up_cycles = 0;
2267 continue;
2268 }
2269 // average?
2270 catch_up_cycles /= elapsed_prng_sequences;
2271
2272 if (catch_up_cycles == last_catch_up) {
2273 ++consecutive_resyncs;
2274 } else {
2275 last_catch_up = catch_up_cycles;
2276 consecutive_resyncs = 0;
2277 }
2278
2279 if (consecutive_resyncs < 3) {
2280 if (MF_DBGLEVEL >= 4)
2281 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
2282 } else {
2283 sync_cycles += catch_up_cycles;
2284
2285 if (MF_DBGLEVEL >= 4)
2286 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
2287
2288 last_catch_up = 0;
2289 catch_up_cycles = 0;
2290 consecutive_resyncs = 0;
2291 }
2292 continue;
2293 }
2294
2295 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2296 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2297 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2298
2299 if (nt_diff == 0)
2300 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2301
2302 par_list[nt_diff] = SwapBits(par[0], 8);
2303 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
2304
2305 // Test if the information is complete
2306 if (nt_diff == 0x07) {
2307 isOK = 1;
2308 break;
2309 }
2310
2311 nt_diff = (nt_diff + 1) & 0x07;
2312 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2313 par[0] = par_low;
2314
2315 } else {
2316 // No NACK.
2317 if (nt_diff == 0 && first_try) {
2318 par[0]++;
2319 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2320 isOK = -2;
2321 break;
2322 }
2323 } else {
2324 // Why this?
2325 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2326 }
2327 }
2328
2329 // reset the resyncs since we got a complete transaction on right time.
2330 consecutive_resyncs = 0;
2331 } // end for loop
2332
2333 mf_nr_ar[3] &= 0x1F;
2334
2335 if (MF_DBGLEVEL >= 4) Dbprintf("Number of sent auth requestes: %u", i);
2336
2337 uint8_t buf[28] = {0x00};
2338 memset(buf, 0x00, sizeof(buf));
2339 num_to_bytes(cuid, 4, buf);
2340 num_to_bytes(nt, 4, buf + 4);
2341 memcpy(buf + 8, par_list, 8);
2342 memcpy(buf + 16, ks_list, 8);
2343 memcpy(buf + 24, mf_nr_ar, 4);
2344
2345 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
2346
2347 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2348 LEDsoff();
2349 set_tracing(FALSE);
2350 }
2351
2352 /**
2353 *MIFARE 1K simulate.
2354 *
2355 *@param flags :
2356 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2357 * FLAG_4B_UID_IN_DATA - use 4-byte UID in the data-section
2358 * FLAG_7B_UID_IN_DATA - use 7-byte UID in the data-section
2359 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section
2360 * FLAG_UID_IN_EMUL - use 4-byte UID from emulator memory
2361 * FLAG_NR_AR_ATTACK - collect NR_AR responses for bruteforcing later
2362 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2363 */
2364 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
2365 int cardSTATE = MFEMUL_NOFIELD;
2366 int _UID_LEN = 0; // 4, 7, 10
2367 int vHf = 0; // in mV
2368 int res = 0;
2369 uint32_t selTimer = 0;
2370 uint32_t authTimer = 0;
2371 uint16_t len = 0;
2372 uint8_t cardWRBL = 0;
2373 uint8_t cardAUTHSC = 0;
2374 uint8_t cardAUTHKEY = 0xff; // no authentication
2375 uint32_t cuid = 0;
2376 uint32_t ans = 0;
2377 uint32_t cardINTREG = 0;
2378 uint8_t cardINTBLOCK = 0;
2379 struct Crypto1State mpcs = {0, 0};
2380 struct Crypto1State *pcs;
2381 pcs = &mpcs;
2382 uint32_t numReads = 0; //Counts numer of times reader read a block
2383 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2384 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2385 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2386 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2387
2388 uint8_t atqa[] = {0x04, 0x00}; // Mifare classic 1k
2389 uint8_t sak_4[] = {0x0C, 0x00, 0x00}; // CL1 - 4b uid
2390 uint8_t sak_7[] = {0x0C, 0x00, 0x00}; // CL2 - 7b uid
2391 uint8_t sak_10[] = {0x0C, 0x00, 0x00}; // CL3 - 10b uid
2392 //uint8_t sak[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
2393
2394 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2395 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2396 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2397
2398 uint8_t rAUTH_NT[] = {0x01, 0x01, 0x01, 0x01}; // very random nonce
2399 //uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};// nonce from nested? why this?
2400 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2401
2402 // Here, we collect CUID, NT, NR, AR, CUID2, NT2, NR2, AR2
2403 // This can be used in a reader-only attack.
2404 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0};
2405 uint8_t ar_nr_collected = 0;
2406
2407 // Authenticate response - nonce
2408 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2409 ar_nr_responses[1] = nonce;
2410
2411 //-- Determine the UID
2412 // Can be set from emulator memory or incoming data
2413 // Length: 4,7,or 10 bytes
2414 if ( (flags & FLAG_UID_IN_EMUL) == FLAG_UID_IN_EMUL)
2415 emlGetMemBt(datain, 0, 10); // load 10bytes from EMUL to the datain pointer. to be used below.
2416
2417 if ( (flags & FLAG_4B_UID_IN_DATA) == FLAG_4B_UID_IN_DATA) {
2418 memcpy(rUIDBCC1, datain, 4);
2419 _UID_LEN = 4;
2420 } else if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA) {
2421 memcpy(&rUIDBCC1[1], datain, 3);
2422 memcpy( rUIDBCC2, datain+3, 4);
2423 _UID_LEN = 7;
2424 } else if ( (flags & FLAG_10B_UID_IN_DATA) == FLAG_10B_UID_IN_DATA) {
2425 memcpy(&rUIDBCC1[1], datain, 3);
2426 memcpy(&rUIDBCC2[1], datain+3, 3);
2427 memcpy( rUIDBCC3, datain+6, 4);
2428 _UID_LEN = 10;
2429 }
2430
2431 switch (_UID_LEN) {
2432 case 4:
2433 sak_4[0] &= 0xFB;
2434 // save CUID
2435 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC1, 4);
2436 // BCC
2437 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2438 if (MF_DBGLEVEL >= 2) {
2439 Dbprintf("4B UID: %02x%02x%02x%02x",
2440 rUIDBCC1[0],
2441 rUIDBCC1[1],
2442 rUIDBCC1[2],
2443 rUIDBCC1[3]
2444 );
2445 }
2446 break;
2447 case 7:
2448 atqa[0] |= 0x40;
2449 sak_7[0] &= 0xFB;
2450 // save CUID
2451 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC2, 4);
2452 // CascadeTag, CT
2453 rUIDBCC1[0] = 0x88;
2454 // BCC
2455 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2456 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2457 if (MF_DBGLEVEL >= 2) {
2458 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
2459 rUIDBCC1[1],
2460 rUIDBCC1[2],
2461 rUIDBCC1[3],
2462 rUIDBCC2[0],
2463 rUIDBCC2[1],
2464 rUIDBCC2[2],
2465 rUIDBCC2[3]
2466 );
2467 }
2468 break;
2469 case 10:
2470 atqa[0] |= 0x80;
2471 sak_10[0] &= 0xFB;
2472 // save CUID
2473 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC3, 4);
2474 // CascadeTag, CT
2475 rUIDBCC1[0] = 0x88;
2476 rUIDBCC2[0] = 0x88;
2477 // BCC
2478 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2479 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2480 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
2481
2482 if (MF_DBGLEVEL >= 2) {
2483 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
2484 rUIDBCC1[1],
2485 rUIDBCC1[2],
2486 rUIDBCC1[3],
2487 rUIDBCC2[1],
2488 rUIDBCC2[2],
2489 rUIDBCC2[3],
2490 rUIDBCC3[0],
2491 rUIDBCC3[1],
2492 rUIDBCC3[2],
2493 rUIDBCC3[3]
2494 );
2495 }
2496 break;
2497 default:
2498 break;
2499 }
2500 // calc some crcs
2501 ComputeCrc14443(CRC_14443_A, sak_4, 1, &sak_4[1], &sak_4[2]);
2502 ComputeCrc14443(CRC_14443_A, sak_7, 1, &sak_7[1], &sak_7[2]);
2503 ComputeCrc14443(CRC_14443_A, sak_10, 1, &sak_10[1], &sak_10[2]);
2504
2505 // We need to listen to the high-frequency, peak-detected path.
2506 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2507
2508 // free eventually allocated BigBuf memory but keep Emulator Memory
2509 BigBuf_free_keep_EM();
2510 clear_trace();
2511 set_tracing(TRUE);
2512
2513 bool finished = FALSE;
2514 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
2515 WDT_HIT();
2516
2517 // find reader field
2518 if (cardSTATE == MFEMUL_NOFIELD) {
2519 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2520 if (vHf > MF_MINFIELDV) {
2521 cardSTATE_TO_IDLE();
2522 LED_A_ON();
2523 }
2524 }
2525 if (cardSTATE == MFEMUL_NOFIELD) continue;
2526
2527 //Now, get data
2528 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2529 if (res == 2) { //Field is off!
2530 cardSTATE = MFEMUL_NOFIELD;
2531 LEDsoff();
2532 continue;
2533 } else if (res == 1) {
2534 break; //return value 1 means button press
2535 }
2536
2537 // REQ or WUP request in ANY state and WUP in HALTED state
2538 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
2539 selTimer = GetTickCount();
2540 EmSendCmdEx(atqa, sizeof(atqa), (receivedCmd[0] == ISO14443A_CMD_WUPA));
2541 cardSTATE = MFEMUL_SELECT1;
2542 crypto1_destroy(pcs);
2543 cardAUTHKEY = 0xff;
2544 LEDsoff();
2545 nonce++;
2546 continue;
2547 }
2548
2549 switch (cardSTATE) {
2550 case MFEMUL_NOFIELD:
2551 case MFEMUL_HALTED:
2552 case MFEMUL_IDLE:{
2553 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2554 break;
2555 }
2556 case MFEMUL_SELECT1:{
2557 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
2558 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2559 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2560 break;
2561 }
2562 // select card
2563 if (len == 9 &&
2564 ( receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT &&
2565 receivedCmd[1] == 0x70 &&
2566 memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2567
2568 // SAK 4b
2569 EmSendCmd(sak_4, sizeof(sak_4));
2570 switch(_UID_LEN){
2571 case 4:
2572 cardSTATE = MFEMUL_WORK;
2573 LED_B_ON();
2574 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2575 continue;
2576 case 7:
2577 case 10:
2578 cardSTATE = MFEMUL_SELECT2;
2579 continue;
2580 default:break;
2581 }
2582 } else {
2583 cardSTATE_TO_IDLE();
2584 }
2585 break;
2586 }
2587 case MFEMUL_SELECT2:{
2588 if (!len) {
2589 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2590 break;
2591 }
2592 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
2593 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2594 break;
2595 }
2596 if (len == 9 &&
2597 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 &&
2598 receivedCmd[1] == 0x70 &&
2599 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
2600
2601 EmSendCmd(sak_7, sizeof(sak_7));
2602 switch(_UID_LEN){
2603 case 7:
2604 cardSTATE = MFEMUL_WORK;
2605 LED_B_ON();
2606 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2607 continue;
2608 case 10:
2609 cardSTATE = MFEMUL_SELECT3;
2610 continue;
2611 default:break;
2612 }
2613 }
2614 cardSTATE_TO_IDLE();
2615 break;
2616 }
2617 case MFEMUL_SELECT3:{
2618 if (!len) {
2619 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2620 break;
2621 }
2622 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2623 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2624 break;
2625 }
2626 if (len == 9 &&
2627 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2628 receivedCmd[1] == 0x70 &&
2629 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2630
2631 EmSendCmd(sak_10, sizeof(sak_10));
2632 cardSTATE = MFEMUL_WORK;
2633 LED_B_ON();
2634 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2635 break;
2636 }
2637 cardSTATE_TO_IDLE();
2638 break;
2639 }
2640 case MFEMUL_AUTH1:{
2641 if( len != 8) {
2642 cardSTATE_TO_IDLE();
2643 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2644 break;
2645 }
2646
2647 uint32_t nr = bytes_to_num(receivedCmd, 4);
2648 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
2649
2650 //Collect AR/NR
2651 //if(ar_nr_collected < 2 && cardAUTHSC == 2){
2652 if(ar_nr_collected < 2) {
2653 //if(ar_nr_responses[2] != nr) {
2654 ar_nr_responses[ar_nr_collected*4] = cuid;
2655 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2656 ar_nr_responses[ar_nr_collected*4+2] = nr;
2657 ar_nr_responses[ar_nr_collected*4+3] = ar;
2658 ar_nr_collected++;
2659 //}
2660
2661 // Interactive mode flag, means we need to send ACK
2662 finished = ( ((flags & FLAG_INTERACTIVE) == FLAG_INTERACTIVE)&& ar_nr_collected == 2);
2663 }
2664 /*
2665 crypto1_word(pcs, ar , 1);
2666 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2667
2668 test if auth OK
2669 if (cardRr != prng_successor(nonce, 64)){
2670
2671 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2672 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2673 cardRr, prng_successor(nonce, 64));
2674 Shouldn't we respond anything here?
2675 Right now, we don't nack or anything, which causes the
2676 reader to do a WUPA after a while. /Martin
2677 -- which is the correct response. /piwi
2678 cardSTATE_TO_IDLE();
2679 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2680 break;
2681 }
2682 */
2683
2684 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2685 num_to_bytes(ans, 4, rAUTH_AT);
2686 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2687 LED_C_ON();
2688
2689 if (MF_DBGLEVEL >= 4) {
2690 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2691 cardAUTHSC,
2692 cardAUTHKEY == 0 ? 'A' : 'B',
2693 GetTickCount() - authTimer
2694 );
2695 }
2696 cardSTATE = MFEMUL_WORK;
2697 break;
2698 }
2699 case MFEMUL_WORK:{
2700 if (len == 0) {
2701 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2702 break;
2703 }
2704 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2705
2706 if(encrypted_data)
2707 mf_crypto1_decrypt(pcs, receivedCmd, len);
2708
2709 if (len == 4 && (receivedCmd[0] == MIFARE_AUTH_KEYA ||
2710 receivedCmd[0] == MIFARE_AUTH_KEYB) ) {
2711
2712 authTimer = GetTickCount();
2713 cardAUTHSC = receivedCmd[1] / 4; // received block num
2714 cardAUTHKEY = receivedCmd[0] - 0x60; // & 1
2715 crypto1_destroy(pcs);
2716 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2717
2718 if (!encrypted_data) {
2719 // first authentication
2720 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2721 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2722
2723 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2724
2725 } else {
2726 // nested authentication
2727 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2728 num_to_bytes(ans, 4, rAUTH_AT);
2729
2730 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2731 }
2732
2733 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2734 cardSTATE = MFEMUL_AUTH1;
2735 break;
2736 }
2737
2738 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2739 // BUT... ACK --> NACK
2740 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2741 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2742 break;
2743 }
2744
2745 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2746 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2747 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2748 break;
2749 }
2750
2751 if(len != 4) {
2752 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2753 break;
2754 }
2755
2756 if ( receivedCmd[0] == ISO14443A_CMD_READBLOCK ||
2757 receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK ||
2758 receivedCmd[0] == MIFARE_CMD_INC ||
2759 receivedCmd[0] == MIFARE_CMD_DEC ||
2760 receivedCmd[0] == MIFARE_CMD_RESTORE ||
2761 receivedCmd[0] == MIFARE_CMD_TRANSFER ) {
2762
2763 if (receivedCmd[1] >= 16 * 4) {
2764 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2765 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2766 break;
2767 }
2768
2769 if (receivedCmd[1] / 4 != cardAUTHSC) {
2770 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2771 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2772 break;
2773 }
2774 }
2775 // read block
2776 if (receivedCmd[0] == ISO14443A_CMD_READBLOCK) {
2777 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)", receivedCmd[1], receivedCmd[1]);
2778
2779 emlGetMem(response, receivedCmd[1], 1);
2780 AppendCrc14443a(response, 16);
2781 mf_crypto1_encrypt(pcs, response, 18, response_par);
2782 EmSendCmdPar(response, 18, response_par);
2783 numReads++;
2784 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
2785 Dbprintf("%d reads done, exiting", numReads);
2786 finished = true;
2787 }
2788 break;
2789 }
2790 // write block
2791 if (receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK) {
2792 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)", receivedCmd[1], receivedCmd[1]);
2793 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2794 cardSTATE = MFEMUL_WRITEBL2;
2795 cardWRBL = receivedCmd[1];
2796 break;
2797 }
2798 // increment, decrement, restore
2799 if ( receivedCmd[0] == MIFARE_CMD_INC ||
2800 receivedCmd[0] == MIFARE_CMD_DEC ||
2801 receivedCmd[0] == MIFARE_CMD_RESTORE) {
2802
2803 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2804
2805 if (emlCheckValBl(receivedCmd[1])) {
2806 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2807 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2808 break;
2809 }
2810 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2811 if (receivedCmd[0] == MIFARE_CMD_INC) cardSTATE = MFEMUL_INTREG_INC;
2812 if (receivedCmd[0] == MIFARE_CMD_DEC) cardSTATE = MFEMUL_INTREG_DEC;
2813 if (receivedCmd[0] == MIFARE_CMD_RESTORE) cardSTATE = MFEMUL_INTREG_REST;
2814 cardWRBL = receivedCmd[1];
2815 break;
2816 }
2817 // transfer
2818 if (receivedCmd[0] == MIFARE_CMD_TRANSFER) {
2819 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)", receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2820 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2821 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2822 else
2823 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2824 break;
2825 }
2826 // halt
2827 if (receivedCmd[0] == ISO14443A_CMD_HALT && receivedCmd[1] == 0x00) {
2828 LED_B_OFF();
2829 LED_C_OFF();
2830 cardSTATE = MFEMUL_HALTED;
2831 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2832 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2833 break;
2834 }
2835 // RATS
2836 if (receivedCmd[0] == ISO14443A_CMD_RATS) {
2837 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2838 break;
2839 }
2840 // command not allowed
2841 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2842 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2843 break;
2844 }
2845 case MFEMUL_WRITEBL2:{
2846 if (len == 18) {
2847 mf_crypto1_decrypt(pcs, receivedCmd, len);
2848 emlSetMem(receivedCmd, cardWRBL, 1);
2849 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2850 cardSTATE = MFEMUL_WORK;
2851 } else {
2852 cardSTATE_TO_IDLE();
2853 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2854 }
2855 break;
2856 }
2857 case MFEMUL_INTREG_INC:{
2858 mf_crypto1_decrypt(pcs, receivedCmd, len);
2859 memcpy(&ans, receivedCmd, 4);
2860 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2861 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2862 cardSTATE_TO_IDLE();
2863 break;
2864 }
2865 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2866 cardINTREG = cardINTREG + ans;
2867 cardSTATE = MFEMUL_WORK;
2868 break;
2869 }
2870 case MFEMUL_INTREG_DEC:{
2871 mf_crypto1_decrypt(pcs, receivedCmd, len);
2872 memcpy(&ans, receivedCmd, 4);
2873 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2874 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2875 cardSTATE_TO_IDLE();
2876 break;
2877 }
2878 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2879 cardINTREG = cardINTREG - ans;
2880 cardSTATE = MFEMUL_WORK;
2881 break;
2882 }
2883 case MFEMUL_INTREG_REST:{
2884 mf_crypto1_decrypt(pcs, receivedCmd, len);
2885 memcpy(&ans, receivedCmd, 4);
2886 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2887 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2888 cardSTATE_TO_IDLE();
2889 break;
2890 }
2891 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2892 cardSTATE = MFEMUL_WORK;
2893 break;
2894 }
2895 }
2896 }
2897
2898 // Interactive mode flag, means we need to send ACK
2899 if((flags & FLAG_INTERACTIVE) == FLAG_INTERACTIVE) {
2900 //May just aswell send the collected ar_nr in the response aswell
2901 uint8_t len = ar_nr_collected * 4 * 4;
2902 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
2903 }
2904
2905 if( ((flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) && MF_DBGLEVEL >= 1 ) {
2906 if(ar_nr_collected > 1 ) {
2907 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2908 Dbprintf("../tools/mfkey/mfkey32v2.exe %08x %08x %08x %08x %08x %08x %08x",
2909 ar_nr_responses[0], // CUID
2910 ar_nr_responses[1], // NT1
2911 ar_nr_responses[2], // NR1
2912 ar_nr_responses[3], // AR1
2913 //ar_nr_responses[4], // CUID2
2914 ar_nr_responses[5], // NT2
2915 ar_nr_responses[6], // NR2
2916 ar_nr_responses[7] // AR2
2917 );
2918 } else {
2919 Dbprintf("Failed to obtain two AR/NR pairs!");
2920 if(ar_nr_collected == 1 ) {
2921 Dbprintf("Only got these: UID=%08x, nonce=%08x, NR1=%08x, AR1=%08x",
2922 ar_nr_responses[0], // CUID
2923 ar_nr_responses[1], // NT
2924 ar_nr_responses[2], // NR1
2925 ar_nr_responses[3] // AR1
2926 );
2927 }
2928 }
2929 }
2930 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2931
2932 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2933 LEDsoff();
2934 set_tracing(FALSE);
2935 }
2936
2937
2938 //-----------------------------------------------------------------------------
2939 // MIFARE sniffer.
2940 //
2941 // if no activity for 2sec, it sends the collected data to the client.
2942 //-----------------------------------------------------------------------------
2943 // "hf mf sniff"
2944 void RAMFUNC SniffMifare(uint8_t param) {
2945
2946 LEDsoff();
2947
2948 // free eventually allocated BigBuf memory
2949 BigBuf_free(); BigBuf_Clear_ext(false);
2950 clear_trace();
2951 set_tracing(TRUE);
2952
2953 // The command (reader -> tag) that we're receiving.
2954 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2955 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
2956
2957 // The response (tag -> reader) that we're receiving.
2958 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
2959 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
2960
2961 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2962
2963 // allocate the DMA buffer, used to stream samples from the FPGA
2964 // [iceman] is this sniffed data unsigned?
2965 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2966 uint8_t *data = dmaBuf;
2967 uint8_t previous_data = 0;
2968 int maxDataLen = 0;
2969 int dataLen = 0;
2970 bool ReaderIsActive = FALSE;
2971 bool TagIsActive = FALSE;
2972
2973 // Set up the demodulator for tag -> reader responses.
2974 DemodInit(receivedResponse, receivedResponsePar);
2975
2976 // Set up the demodulator for the reader -> tag commands
2977 UartInit(receivedCmd, receivedCmdPar);
2978
2979 // set transfer address and number of bytes. Start transfer.
2980 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
2981
2982 LED_D_OFF();
2983
2984 MfSniffInit();
2985
2986 // And now we loop, receiving samples.
2987 for(uint32_t sniffCounter = 0;; ) {
2988
2989 LED_A_ON();
2990 WDT_HIT();
2991
2992 if(BUTTON_PRESS()) {
2993 DbpString("cancelled by button");
2994 break;
2995 }
2996
2997 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2998 // check if a transaction is completed (timeout after 2000ms).
2999 // if yes, stop the DMA transfer and send what we have so far to the client
3000 if (MfSniffSend(2000)) {
3001 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3002 sniffCounter = 0;
3003 data = dmaBuf;
3004 maxDataLen = 0;
3005 ReaderIsActive = FALSE;
3006 TagIsActive = FALSE;
3007 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
3008 }
3009 }
3010
3011 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3012 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
3013
3014 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
3015 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
3016 else
3017 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
3018
3019 // test for length of buffer
3020 if(dataLen > maxDataLen) { // we are more behind than ever...
3021 maxDataLen = dataLen;
3022 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
3023 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
3024 break;
3025 }
3026 }
3027 if(dataLen < 1) continue;
3028
3029 // primary buffer was stopped ( <-- we lost data!
3030 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3031 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3032 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
3033 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
3034 }
3035 // secondary buffer sets as primary, secondary buffer was stopped
3036 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3037 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
3038 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3039 }
3040
3041 LED_A_OFF();
3042
3043 if (sniffCounter & 0x01) {
3044
3045 // no need to try decoding tag data if the reader is sending
3046 if(!TagIsActive) {
3047 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3048 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3049 LED_C_INV();
3050
3051 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
3052
3053 UartInit(receivedCmd, receivedCmdPar);
3054 DemodReset();
3055 }
3056 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3057 }
3058
3059 // no need to try decoding tag data if the reader is sending
3060 if(!ReaderIsActive) {
3061 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3062 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3063 LED_C_INV();
3064
3065 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
3066
3067 DemodReset();
3068 UartInit(receivedCmd, receivedCmdPar);
3069 }
3070 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3071 }
3072 }
3073
3074 previous_data = *data;
3075 sniffCounter++;
3076 data++;
3077
3078 if(data == dmaBuf + DMA_BUFFER_SIZE)
3079 data = dmaBuf;
3080
3081 } // main cycle
3082
3083 if (MF_DBGLEVEL >= 1) Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3084
3085 FpgaDisableSscDma();
3086 MfSniffEnd();
3087 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3088 LEDsoff();
3089 set_tracing(FALSE);
3090 }
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