]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Added Unique Code to EM41x
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18 void AcquireRawAdcSamples125k(int divisor)
19 {
20 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
21 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
22 else if (divisor == 0)
23 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
24 else
25 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
26
27 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
28
29 // Connect the A/D to the peak-detected low-frequency path.
30 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
31
32 // Give it a bit of time for the resonant antenna to settle.
33 SpinDelay(50);
34
35 // Now set up the SSC to get the ADC samples that are now streaming at us.
36 FpgaSetupSsc();
37
38 // Now call the acquisition routine
39 DoAcquisition125k();
40 }
41
42 // split into two routines so we can avoid timing issues after sending commands //
43 void DoAcquisition125k(void)
44 {
45 uint8_t *dest = (uint8_t *)BigBuf;
46 int n = sizeof(BigBuf);
47 int i;
48
49 memset(dest, 0, n);
50 i = 0;
51 for(;;) {
52 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
53 AT91C_BASE_SSC->SSC_THR = 0x43;
54 LED_D_ON();
55 }
56 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
57 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
58 i++;
59 LED_D_OFF();
60 if (i >= n) break;
61 }
62 }
63 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
64 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
65 }
66
67 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
68 {
69 int at134khz;
70
71 /* Make sure the tag is reset */
72 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
73 SpinDelay(2500);
74
75 // see if 'h' was specified
76 if (command[strlen((char *) command) - 1] == 'h')
77 at134khz = TRUE;
78 else
79 at134khz = FALSE;
80
81 if (at134khz)
82 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
83 else
84 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
85
86 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
87
88 // Give it a bit of time for the resonant antenna to settle.
89 SpinDelay(50);
90 // And a little more time for the tag to fully power up
91 SpinDelay(2000);
92
93 // Now set up the SSC to get the ADC samples that are now streaming at us.
94 FpgaSetupSsc();
95
96 // now modulate the reader field
97 while(*command != '\0' && *command != ' ') {
98 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
99 LED_D_OFF();
100 SpinDelayUs(delay_off);
101 if (at134khz)
102 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
103 else
104 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
105
106 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
107 LED_D_ON();
108 if(*(command++) == '0')
109 SpinDelayUs(period_0);
110 else
111 SpinDelayUs(period_1);
112 }
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
114 LED_D_OFF();
115 SpinDelayUs(delay_off);
116 if (at134khz)
117 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
118 else
119 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
122
123 // now do the read
124 DoAcquisition125k();
125 }
126
127 /* blank r/w tag data stream
128 ...0000000000000000 01111111
129 1010101010101010101010101010101010101010101010101010101010101010
130 0011010010100001
131 01111111
132 101010101010101[0]000...
133
134 [5555fe852c5555555555555555fe0000]
135 */
136 void ReadTItag(void)
137 {
138 // some hardcoded initial params
139 // when we read a TI tag we sample the zerocross line at 2Mhz
140 // TI tags modulate a 1 as 16 cycles of 123.2Khz
141 // TI tags modulate a 0 as 16 cycles of 134.2Khz
142 #define FSAMPLE 2000000
143 #define FREQLO 123200
144 #define FREQHI 134200
145
146 signed char *dest = (signed char *)BigBuf;
147 int n = sizeof(BigBuf);
148 // int *dest = GraphBuffer;
149 // int n = GraphTraceLen;
150
151 // 128 bit shift register [shift3:shift2:shift1:shift0]
152 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
153
154 int i, cycles=0, samples=0;
155 // how many sample points fit in 16 cycles of each frequency
156 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
157 // when to tell if we're close enough to one freq or another
158 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
159
160 // TI tags charge at 134.2Khz
161 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
162
163 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
164 // connects to SSP_DIN and the SSP_DOUT logic level controls
165 // whether we're modulating the antenna (high)
166 // or listening to the antenna (low)
167 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
168
169 // get TI tag data into the buffer
170 AcquireTiType();
171
172 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
173
174 for (i=0; i<n-1; i++) {
175 // count cycles by looking for lo to hi zero crossings
176 if ( (dest[i]<0) && (dest[i+1]>0) ) {
177 cycles++;
178 // after 16 cycles, measure the frequency
179 if (cycles>15) {
180 cycles=0;
181 samples=i-samples; // number of samples in these 16 cycles
182
183 // TI bits are coming to us lsb first so shift them
184 // right through our 128 bit right shift register
185 shift0 = (shift0>>1) | (shift1 << 31);
186 shift1 = (shift1>>1) | (shift2 << 31);
187 shift2 = (shift2>>1) | (shift3 << 31);
188 shift3 >>= 1;
189
190 // check if the cycles fall close to the number
191 // expected for either the low or high frequency
192 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
193 // low frequency represents a 1
194 shift3 |= (1<<31);
195 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
196 // high frequency represents a 0
197 } else {
198 // probably detected a gay waveform or noise
199 // use this as gaydar or discard shift register and start again
200 shift3 = shift2 = shift1 = shift0 = 0;
201 }
202 samples = i;
203
204 // for each bit we receive, test if we've detected a valid tag
205
206 // if we see 17 zeroes followed by 6 ones, we might have a tag
207 // remember the bits are backwards
208 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
209 // if start and end bytes match, we have a tag so break out of the loop
210 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
211 cycles = 0xF0B; //use this as a flag (ugly but whatever)
212 break;
213 }
214 }
215 }
216 }
217 }
218
219 // if flag is set we have a tag
220 if (cycles!=0xF0B) {
221 DbpString("Info: No valid tag detected.");
222 } else {
223 // put 64 bit data into shift1 and shift0
224 shift0 = (shift0>>24) | (shift1 << 8);
225 shift1 = (shift1>>24) | (shift2 << 8);
226
227 // align 16 bit crc into lower half of shift2
228 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
229
230 // if r/w tag, check ident match
231 if ( shift3&(1<<15) ) {
232 DbpString("Info: TI tag is rewriteable");
233 // only 15 bits compare, last bit of ident is not valid
234 if ( ((shift3>>16)^shift0)&0x7fff ) {
235 DbpString("Error: Ident mismatch!");
236 } else {
237 DbpString("Info: TI tag ident is valid");
238 }
239 } else {
240 DbpString("Info: TI tag is readonly");
241 }
242
243 // WARNING the order of the bytes in which we calc crc below needs checking
244 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
245 // bytes in reverse or something
246 // calculate CRC
247 uint32_t crc=0;
248
249 crc = update_crc16(crc, (shift0)&0xff);
250 crc = update_crc16(crc, (shift0>>8)&0xff);
251 crc = update_crc16(crc, (shift0>>16)&0xff);
252 crc = update_crc16(crc, (shift0>>24)&0xff);
253 crc = update_crc16(crc, (shift1)&0xff);
254 crc = update_crc16(crc, (shift1>>8)&0xff);
255 crc = update_crc16(crc, (shift1>>16)&0xff);
256 crc = update_crc16(crc, (shift1>>24)&0xff);
257
258 Dbprintf("Info: Tag data: %x%08x, crc=%x",
259 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
260 if (crc != (shift2&0xffff)) {
261 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
262 } else {
263 DbpString("Info: CRC is good");
264 }
265 }
266 }
267
268 void WriteTIbyte(uint8_t b)
269 {
270 int i = 0;
271
272 // modulate 8 bits out to the antenna
273 for (i=0; i<8; i++)
274 {
275 if (b&(1<<i)) {
276 // stop modulating antenna
277 LOW(GPIO_SSC_DOUT);
278 SpinDelayUs(1000);
279 // modulate antenna
280 HIGH(GPIO_SSC_DOUT);
281 SpinDelayUs(1000);
282 } else {
283 // stop modulating antenna
284 LOW(GPIO_SSC_DOUT);
285 SpinDelayUs(300);
286 // modulate antenna
287 HIGH(GPIO_SSC_DOUT);
288 SpinDelayUs(1700);
289 }
290 }
291 }
292
293 void AcquireTiType(void)
294 {
295 int i, j, n;
296 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
297 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
298 #define TIBUFLEN 1250
299
300 // clear buffer
301 memset(BigBuf,0,sizeof(BigBuf));
302
303 // Set up the synchronous serial port
304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
306
307 // steal this pin from the SSP and use it to control the modulation
308 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
309 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
310
311 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
312 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
313
314 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
315 // 48/2 = 24 MHz clock must be divided by 12
316 AT91C_BASE_SSC->SSC_CMR = 12;
317
318 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
319 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
320 AT91C_BASE_SSC->SSC_TCMR = 0;
321 AT91C_BASE_SSC->SSC_TFMR = 0;
322
323 LED_D_ON();
324
325 // modulate antenna
326 HIGH(GPIO_SSC_DOUT);
327
328 // Charge TI tag for 50ms.
329 SpinDelay(50);
330
331 // stop modulating antenna and listen
332 LOW(GPIO_SSC_DOUT);
333
334 LED_D_OFF();
335
336 i = 0;
337 for(;;) {
338 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
339 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
340 i++; if(i >= TIBUFLEN) break;
341 }
342 WDT_HIT();
343 }
344
345 // return stolen pin to SSP
346 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
347 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
348
349 char *dest = (char *)BigBuf;
350 n = TIBUFLEN*32;
351 // unpack buffer
352 for (i=TIBUFLEN-1; i>=0; i--) {
353 for (j=0; j<32; j++) {
354 if(BigBuf[i] & (1 << j)) {
355 dest[--n] = 1;
356 } else {
357 dest[--n] = -1;
358 }
359 }
360 }
361 }
362
363 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
364 // if crc provided, it will be written with the data verbatim (even if bogus)
365 // if not provided a valid crc will be computed from the data and written.
366 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
367 {
368 if(crc == 0) {
369 crc = update_crc16(crc, (idlo)&0xff);
370 crc = update_crc16(crc, (idlo>>8)&0xff);
371 crc = update_crc16(crc, (idlo>>16)&0xff);
372 crc = update_crc16(crc, (idlo>>24)&0xff);
373 crc = update_crc16(crc, (idhi)&0xff);
374 crc = update_crc16(crc, (idhi>>8)&0xff);
375 crc = update_crc16(crc, (idhi>>16)&0xff);
376 crc = update_crc16(crc, (idhi>>24)&0xff);
377 }
378 Dbprintf("Writing to tag: %x%08x, crc=%x",
379 (unsigned int) idhi, (unsigned int) idlo, crc);
380
381 // TI tags charge at 134.2Khz
382 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
383 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
384 // connects to SSP_DIN and the SSP_DOUT logic level controls
385 // whether we're modulating the antenna (high)
386 // or listening to the antenna (low)
387 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
388 LED_A_ON();
389
390 // steal this pin from the SSP and use it to control the modulation
391 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
392 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
393
394 // writing algorithm:
395 // a high bit consists of a field off for 1ms and field on for 1ms
396 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
397 // initiate a charge time of 50ms (field on) then immediately start writing bits
398 // start by writing 0xBB (keyword) and 0xEB (password)
399 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
400 // finally end with 0x0300 (write frame)
401 // all data is sent lsb firts
402 // finish with 15ms programming time
403
404 // modulate antenna
405 HIGH(GPIO_SSC_DOUT);
406 SpinDelay(50); // charge time
407
408 WriteTIbyte(0xbb); // keyword
409 WriteTIbyte(0xeb); // password
410 WriteTIbyte( (idlo )&0xff );
411 WriteTIbyte( (idlo>>8 )&0xff );
412 WriteTIbyte( (idlo>>16)&0xff );
413 WriteTIbyte( (idlo>>24)&0xff );
414 WriteTIbyte( (idhi )&0xff );
415 WriteTIbyte( (idhi>>8 )&0xff );
416 WriteTIbyte( (idhi>>16)&0xff );
417 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
418 WriteTIbyte( (crc )&0xff ); // crc lo
419 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
420 WriteTIbyte(0x00); // write frame lo
421 WriteTIbyte(0x03); // write frame hi
422 HIGH(GPIO_SSC_DOUT);
423 SpinDelay(50); // programming time
424
425 LED_A_OFF();
426
427 // get TI tag data into the buffer
428 AcquireTiType();
429
430 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
431 DbpString("Now use tiread to check");
432 }
433
434 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
435 {
436 int i;
437 uint8_t *tab = (uint8_t *)BigBuf;
438
439 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
440
441 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
442
443 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
444 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
445
446 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
447 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
448
449 i = 0;
450 for(;;) {
451 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
452 if(BUTTON_PRESS()) {
453 DbpString("Stopped");
454 return;
455 }
456 WDT_HIT();
457 }
458
459 if (ledcontrol)
460 LED_D_ON();
461
462 if(tab[i])
463 OPEN_COIL();
464 else
465 SHORT_COIL();
466
467 if (ledcontrol)
468 LED_D_OFF();
469
470 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
471 if(BUTTON_PRESS()) {
472 DbpString("Stopped");
473 return;
474 }
475 WDT_HIT();
476 }
477
478 i++;
479 if(i == period) {
480 i = 0;
481 if (gap) {
482 SHORT_COIL();
483 SpinDelayUs(gap);
484 }
485 }
486 }
487 }
488
489 #define DEBUG_FRAME_CONTENTS 1
490 void SimulateTagLowFrequencyBidir(int divisor, int t0)
491 {
492 }
493
494 // compose fc/8 fc/10 waveform
495 static void fc(int c, int *n) {
496 uint8_t *dest = (uint8_t *)BigBuf;
497 int idx;
498
499 // for when we want an fc8 pattern every 4 logical bits
500 if(c==0) {
501 dest[((*n)++)]=1;
502 dest[((*n)++)]=1;
503 dest[((*n)++)]=0;
504 dest[((*n)++)]=0;
505 dest[((*n)++)]=0;
506 dest[((*n)++)]=0;
507 dest[((*n)++)]=0;
508 dest[((*n)++)]=0;
509 }
510 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
511 if(c==8) {
512 for (idx=0; idx<6; idx++) {
513 dest[((*n)++)]=1;
514 dest[((*n)++)]=1;
515 dest[((*n)++)]=0;
516 dest[((*n)++)]=0;
517 dest[((*n)++)]=0;
518 dest[((*n)++)]=0;
519 dest[((*n)++)]=0;
520 dest[((*n)++)]=0;
521 }
522 }
523
524 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
525 if(c==10) {
526 for (idx=0; idx<5; idx++) {
527 dest[((*n)++)]=1;
528 dest[((*n)++)]=1;
529 dest[((*n)++)]=1;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 dest[((*n)++)]=0;
534 dest[((*n)++)]=0;
535 dest[((*n)++)]=0;
536 dest[((*n)++)]=0;
537 }
538 }
539 }
540
541 // prepare a waveform pattern in the buffer based on the ID given then
542 // simulate a HID tag until the button is pressed
543 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
544 {
545 int n=0, i=0;
546 /*
547 HID tag bitstream format
548 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
549 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
550 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
551 A fc8 is inserted before every 4 bits
552 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
553 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
554 */
555
556 if (hi>0xFFF) {
557 DbpString("Tags can only have 44 bits.");
558 return;
559 }
560 fc(0,&n);
561 // special start of frame marker containing invalid bit sequences
562 fc(8, &n); fc(8, &n); // invalid
563 fc(8, &n); fc(10, &n); // logical 0
564 fc(10, &n); fc(10, &n); // invalid
565 fc(8, &n); fc(10, &n); // logical 0
566
567 WDT_HIT();
568 // manchester encode bits 43 to 32
569 for (i=11; i>=0; i--) {
570 if ((i%4)==3) fc(0,&n);
571 if ((hi>>i)&1) {
572 fc(10, &n); fc(8, &n); // low-high transition
573 } else {
574 fc(8, &n); fc(10, &n); // high-low transition
575 }
576 }
577
578 WDT_HIT();
579 // manchester encode bits 31 to 0
580 for (i=31; i>=0; i--) {
581 if ((i%4)==3) fc(0,&n);
582 if ((lo>>i)&1) {
583 fc(10, &n); fc(8, &n); // low-high transition
584 } else {
585 fc(8, &n); fc(10, &n); // high-low transition
586 }
587 }
588
589 if (ledcontrol)
590 LED_A_ON();
591 SimulateTagLowFrequency(n, 0, ledcontrol);
592
593 if (ledcontrol)
594 LED_A_OFF();
595 }
596
597
598 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
599 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
600 {
601 uint8_t *dest = (uint8_t *)BigBuf;
602 int m=0, n=0, i=0, idx=0, found=0, lastval=0;
603 uint32_t hi2=0, hi=0, lo=0;
604
605 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
606 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
607
608 // Connect the A/D to the peak-detected low-frequency path.
609 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
610
611 // Give it a bit of time for the resonant antenna to settle.
612 SpinDelay(50);
613
614 // Now set up the SSC to get the ADC samples that are now streaming at us.
615 FpgaSetupSsc();
616
617 for(;;) {
618 WDT_HIT();
619 if (ledcontrol)
620 LED_A_ON();
621 if(BUTTON_PRESS()) {
622 DbpString("Stopped");
623 if (ledcontrol)
624 LED_A_OFF();
625 return;
626 }
627
628 i = 0;
629 m = sizeof(BigBuf);
630 memset(dest,128,m);
631 for(;;) {
632 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
633 AT91C_BASE_SSC->SSC_THR = 0x43;
634 if (ledcontrol)
635 LED_D_ON();
636 }
637 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
638 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
639 // we don't care about actual value, only if it's more or less than a
640 // threshold essentially we capture zero crossings for later analysis
641 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
642 i++;
643 if (ledcontrol)
644 LED_D_OFF();
645 if(i >= m) {
646 break;
647 }
648 }
649 }
650
651 // FSK demodulator
652
653 // sync to first lo-hi transition
654 for( idx=1; idx<m; idx++) {
655 if (dest[idx-1]<dest[idx])
656 lastval=idx;
657 break;
658 }
659 WDT_HIT();
660
661 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
662 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
663 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
664 for( i=0; idx<m; idx++) {
665 if (dest[idx-1]<dest[idx]) {
666 dest[i]=idx-lastval;
667 if (dest[i] <= 8) {
668 dest[i]=1;
669 } else {
670 dest[i]=0;
671 }
672
673 lastval=idx;
674 i++;
675 }
676 }
677 m=i;
678 WDT_HIT();
679
680 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
681 lastval=dest[0];
682 idx=0;
683 i=0;
684 n=0;
685 for( idx=0; idx<m; idx++) {
686 if (dest[idx]==lastval) {
687 n++;
688 } else {
689 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
690 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
691 // swallowed up by rounding
692 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
693 // special start of frame markers use invalid manchester states (no transitions) by using sequences
694 // like 111000
695 if (dest[idx-1]) {
696 n=(n+1)/6; // fc/8 in sets of 6
697 } else {
698 n=(n+1)/5; // fc/10 in sets of 5
699 }
700 switch (n) { // stuff appropriate bits in buffer
701 case 0:
702 case 1: // one bit
703 dest[i++]=dest[idx-1];
704 break;
705 case 2: // two bits
706 dest[i++]=dest[idx-1];
707 dest[i++]=dest[idx-1];
708 break;
709 case 3: // 3 bit start of frame markers
710 dest[i++]=dest[idx-1];
711 dest[i++]=dest[idx-1];
712 dest[i++]=dest[idx-1];
713 break;
714 // When a logic 0 is immediately followed by the start of the next transmisson
715 // (special pattern) a pattern of 4 bit duration lengths is created.
716 case 4:
717 dest[i++]=dest[idx-1];
718 dest[i++]=dest[idx-1];
719 dest[i++]=dest[idx-1];
720 dest[i++]=dest[idx-1];
721 break;
722 default: // this shouldn't happen, don't stuff any bits
723 break;
724 }
725 n=0;
726 lastval=dest[idx];
727 }
728 }
729 m=i;
730 WDT_HIT();
731
732 // final loop, go over previously decoded manchester data and decode into usable tag ID
733 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
734 for( idx=0; idx<m-6; idx++) {
735 // search for a start of frame marker
736 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
737 {
738 found=1;
739 idx+=6;
740 if (found && (hi2|hi|lo)) {
741 if (hi2 != 0){
742 Dbprintf("TAG ID: %x%08x%08x (%d)",
743 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
744 }
745 else {
746 Dbprintf("TAG ID: %x%08x (%d)",
747 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
748 }
749 /* if we're only looking for one tag */
750 if (findone)
751 {
752 *high = hi;
753 *low = lo;
754 return;
755 }
756 hi2=0;
757 hi=0;
758 lo=0;
759 found=0;
760 }
761 }
762 if (found) {
763 if (dest[idx] && (!dest[idx+1]) ) {
764 hi2=(hi2<<1)|(hi>>31);
765 hi=(hi<<1)|(lo>>31);
766 lo=(lo<<1)|0;
767 } else if ( (!dest[idx]) && dest[idx+1]) {
768 hi2=(hi2<<1)|(hi>>31);
769 hi=(hi<<1)|(lo>>31);
770 lo=(lo<<1)|1;
771 } else {
772 found=0;
773 hi2=0;
774 hi=0;
775 lo=0;
776 }
777 idx++;
778 }
779 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
780 {
781 found=1;
782 idx+=6;
783 if (found && (hi|lo)) {
784 if (hi2 != 0){
785 Dbprintf("TAG ID: %x%08x%08x (%d)",
786 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
787 }
788 else {
789 Dbprintf("TAG ID: %x%08x (%d)",
790 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
791 }
792 /* if we're only looking for one tag */
793 if (findone)
794 {
795 *high = hi;
796 *low = lo;
797 return;
798 }
799 hi2=0;
800 hi=0;
801 lo=0;
802 found=0;
803 }
804 }
805 }
806 WDT_HIT();
807 }
808 }
809
810 /*------------------------------
811 * T5555/T5557/T5567 routines
812 *------------------------------
813 */
814
815 /* T55x7 configuration register definitions */
816 #define T55x7_POR_DELAY 0x00000001
817 #define T55x7_ST_TERMINATOR 0x00000008
818 #define T55x7_PWD 0x00000010
819 #define T55x7_MAXBLOCK_SHIFT 5
820 #define T55x7_AOR 0x00000200
821 #define T55x7_PSKCF_RF_2 0
822 #define T55x7_PSKCF_RF_4 0x00000400
823 #define T55x7_PSKCF_RF_8 0x00000800
824 #define T55x7_MODULATION_DIRECT 0
825 #define T55x7_MODULATION_PSK1 0x00001000
826 #define T55x7_MODULATION_PSK2 0x00002000
827 #define T55x7_MODULATION_PSK3 0x00003000
828 #define T55x7_MODULATION_FSK1 0x00004000
829 #define T55x7_MODULATION_FSK2 0x00005000
830 #define T55x7_MODULATION_FSK1a 0x00006000
831 #define T55x7_MODULATION_FSK2a 0x00007000
832 #define T55x7_MODULATION_MANCHESTER 0x00008000
833 #define T55x7_MODULATION_BIPHASE 0x00010000
834 #define T55x7_BITRATE_RF_8 0
835 #define T55x7_BITRATE_RF_16 0x00040000
836 #define T55x7_BITRATE_RF_32 0x00080000
837 #define T55x7_BITRATE_RF_40 0x000C0000
838 #define T55x7_BITRATE_RF_50 0x00100000
839 #define T55x7_BITRATE_RF_64 0x00140000
840 #define T55x7_BITRATE_RF_100 0x00180000
841 #define T55x7_BITRATE_RF_128 0x001C0000
842
843 /* T5555 (Q5) configuration register definitions */
844 #define T5555_ST_TERMINATOR 0x00000001
845 #define T5555_MAXBLOCK_SHIFT 0x00000001
846 #define T5555_MODULATION_MANCHESTER 0
847 #define T5555_MODULATION_PSK1 0x00000010
848 #define T5555_MODULATION_PSK2 0x00000020
849 #define T5555_MODULATION_PSK3 0x00000030
850 #define T5555_MODULATION_FSK1 0x00000040
851 #define T5555_MODULATION_FSK2 0x00000050
852 #define T5555_MODULATION_BIPHASE 0x00000060
853 #define T5555_MODULATION_DIRECT 0x00000070
854 #define T5555_INVERT_OUTPUT 0x00000080
855 #define T5555_PSK_RF_2 0
856 #define T5555_PSK_RF_4 0x00000100
857 #define T5555_PSK_RF_8 0x00000200
858 #define T5555_USE_PWD 0x00000400
859 #define T5555_USE_AOR 0x00000800
860 #define T5555_BITRATE_SHIFT 12
861 #define T5555_FAST_WRITE 0x00004000
862 #define T5555_PAGE_SELECT 0x00008000
863
864 /*
865 * Relevant times in microsecond
866 * To compensate antenna falling times shorten the write times
867 * and enlarge the gap ones.
868 */
869 #define START_GAP 250
870 #define WRITE_GAP 160
871 #define WRITE_0 144 // 192
872 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
873
874 // Write one bit to card
875 void T55xxWriteBit(int bit)
876 {
877 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
878 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
879 if (bit == 0)
880 SpinDelayUs(WRITE_0);
881 else
882 SpinDelayUs(WRITE_1);
883 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
884 SpinDelayUs(WRITE_GAP);
885 }
886
887 // Write one card block in page 0, no lock
888 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
889 {
890 unsigned int i;
891
892 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
893 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
894
895 // Give it a bit of time for the resonant antenna to settle.
896 // And for the tag to fully power up
897 SpinDelay(150);
898
899 // Now start writting
900 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
901 SpinDelayUs(START_GAP);
902
903 // Opcode
904 T55xxWriteBit(1);
905 T55xxWriteBit(0); //Page 0
906 if (PwdMode == 1){
907 // Pwd
908 for (i = 0x80000000; i != 0; i >>= 1)
909 T55xxWriteBit(Pwd & i);
910 }
911 // Lock bit
912 T55xxWriteBit(0);
913
914 // Data
915 for (i = 0x80000000; i != 0; i >>= 1)
916 T55xxWriteBit(Data & i);
917
918 // Block
919 for (i = 0x04; i != 0; i >>= 1)
920 T55xxWriteBit(Block & i);
921
922 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
923 // so wait a little more)
924 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
925 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
926 SpinDelay(20);
927 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
928 }
929
930 // Read one card block in page 0
931 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
932 {
933 uint8_t *dest = (uint8_t *)BigBuf;
934 int m=0, i=0;
935
936 m = sizeof(BigBuf);
937 // Clear destination buffer before sending the command
938 memset(dest, 128, m);
939 // Connect the A/D to the peak-detected low-frequency path.
940 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
941 // Now set up the SSC to get the ADC samples that are now streaming at us.
942 FpgaSetupSsc();
943
944 LED_D_ON();
945 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
946 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
947
948 // Give it a bit of time for the resonant antenna to settle.
949 // And for the tag to fully power up
950 SpinDelay(150);
951
952 // Now start writting
953 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
954 SpinDelayUs(START_GAP);
955
956 // Opcode
957 T55xxWriteBit(1);
958 T55xxWriteBit(0); //Page 0
959 if (PwdMode == 1){
960 // Pwd
961 for (i = 0x80000000; i != 0; i >>= 1)
962 T55xxWriteBit(Pwd & i);
963 }
964 // Lock bit
965 T55xxWriteBit(0);
966 // Block
967 for (i = 0x04; i != 0; i >>= 1)
968 T55xxWriteBit(Block & i);
969
970 // Turn field on to read the response
971 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
972 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
973
974 // Now do the acquisition
975 i = 0;
976 for(;;) {
977 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
978 AT91C_BASE_SSC->SSC_THR = 0x43;
979 }
980 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
981 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
982 // we don't care about actual value, only if it's more or less than a
983 // threshold essentially we capture zero crossings for later analysis
984 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
985 i++;
986 if (i >= m) break;
987 }
988 }
989
990 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
991 LED_D_OFF();
992 DbpString("DONE!");
993 }
994
995 // Read card traceability data (page 1)
996 void T55xxReadTrace(void){
997 uint8_t *dest = (uint8_t *)BigBuf;
998 int m=0, i=0;
999
1000 m = sizeof(BigBuf);
1001 // Clear destination buffer before sending the command
1002 memset(dest, 128, m);
1003 // Connect the A/D to the peak-detected low-frequency path.
1004 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1005 // Now set up the SSC to get the ADC samples that are now streaming at us.
1006 FpgaSetupSsc();
1007
1008 LED_D_ON();
1009 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1010 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1011
1012 // Give it a bit of time for the resonant antenna to settle.
1013 // And for the tag to fully power up
1014 SpinDelay(150);
1015
1016 // Now start writting
1017 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1018 SpinDelayUs(START_GAP);
1019
1020 // Opcode
1021 T55xxWriteBit(1);
1022 T55xxWriteBit(1); //Page 1
1023
1024 // Turn field on to read the response
1025 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1026 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1027
1028 // Now do the acquisition
1029 i = 0;
1030 for(;;) {
1031 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1032 AT91C_BASE_SSC->SSC_THR = 0x43;
1033 }
1034 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1035 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1036 i++;
1037 if (i >= m) break;
1038 }
1039 }
1040
1041 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1042 LED_D_OFF();
1043 DbpString("DONE!");
1044 }
1045
1046 /*-------------- Cloning routines -----------*/
1047 // Copy HID id to card and setup block 0 config
1048 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1049 {
1050 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1051 int last_block = 0;
1052
1053 if (longFMT){
1054 // Ensure no more than 84 bits supplied
1055 if (hi2>0xFFFFF) {
1056 DbpString("Tags can only have 84 bits.");
1057 return;
1058 }
1059 // Build the 6 data blocks for supplied 84bit ID
1060 last_block = 6;
1061 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1062 for (int i=0;i<4;i++) {
1063 if (hi2 & (1<<(19-i)))
1064 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1065 else
1066 data1 |= (1<<((3-i)*2)); // 0 -> 01
1067 }
1068
1069 data2 = 0;
1070 for (int i=0;i<16;i++) {
1071 if (hi2 & (1<<(15-i)))
1072 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1073 else
1074 data2 |= (1<<((15-i)*2)); // 0 -> 01
1075 }
1076
1077 data3 = 0;
1078 for (int i=0;i<16;i++) {
1079 if (hi & (1<<(31-i)))
1080 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1081 else
1082 data3 |= (1<<((15-i)*2)); // 0 -> 01
1083 }
1084
1085 data4 = 0;
1086 for (int i=0;i<16;i++) {
1087 if (hi & (1<<(15-i)))
1088 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1089 else
1090 data4 |= (1<<((15-i)*2)); // 0 -> 01
1091 }
1092
1093 data5 = 0;
1094 for (int i=0;i<16;i++) {
1095 if (lo & (1<<(31-i)))
1096 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1097 else
1098 data5 |= (1<<((15-i)*2)); // 0 -> 01
1099 }
1100
1101 data6 = 0;
1102 for (int i=0;i<16;i++) {
1103 if (lo & (1<<(15-i)))
1104 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1105 else
1106 data6 |= (1<<((15-i)*2)); // 0 -> 01
1107 }
1108 }
1109 else {
1110 // Ensure no more than 44 bits supplied
1111 if (hi>0xFFF) {
1112 DbpString("Tags can only have 44 bits.");
1113 return;
1114 }
1115
1116 // Build the 3 data blocks for supplied 44bit ID
1117 last_block = 3;
1118
1119 data1 = 0x1D000000; // load preamble
1120
1121 for (int i=0;i<12;i++) {
1122 if (hi & (1<<(11-i)))
1123 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1124 else
1125 data1 |= (1<<((11-i)*2)); // 0 -> 01
1126 }
1127
1128 data2 = 0;
1129 for (int i=0;i<16;i++) {
1130 if (lo & (1<<(31-i)))
1131 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1132 else
1133 data2 |= (1<<((15-i)*2)); // 0 -> 01
1134 }
1135
1136 data3 = 0;
1137 for (int i=0;i<16;i++) {
1138 if (lo & (1<<(15-i)))
1139 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1140 else
1141 data3 |= (1<<((15-i)*2)); // 0 -> 01
1142 }
1143 }
1144
1145 LED_D_ON();
1146 // Program the data blocks for supplied ID
1147 // and the block 0 for HID format
1148 T55xxWriteBlock(data1,1,0,0);
1149 T55xxWriteBlock(data2,2,0,0);
1150 T55xxWriteBlock(data3,3,0,0);
1151
1152 if (longFMT) { // if long format there are 6 blocks
1153 T55xxWriteBlock(data4,4,0,0);
1154 T55xxWriteBlock(data5,5,0,0);
1155 T55xxWriteBlock(data6,6,0,0);
1156 }
1157
1158 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1159 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1160 T55x7_MODULATION_FSK2a |
1161 last_block << T55x7_MAXBLOCK_SHIFT,
1162 0,0,0);
1163
1164 LED_D_OFF();
1165
1166 DbpString("DONE!");
1167 }
1168
1169 // Define 9bit header for EM410x tags
1170 #define EM410X_HEADER 0x1FF
1171 #define EM410X_ID_LENGTH 40
1172
1173 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1174 {
1175 int i, id_bit;
1176 uint64_t id = EM410X_HEADER;
1177 uint64_t rev_id = 0; // reversed ID
1178 int c_parity[4]; // column parity
1179 int r_parity = 0; // row parity
1180 uint32_t clock = 0;
1181
1182 // Reverse ID bits given as parameter (for simpler operations)
1183 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1184 if (i < 32) {
1185 rev_id = (rev_id << 1) | (id_lo & 1);
1186 id_lo >>= 1;
1187 } else {
1188 rev_id = (rev_id << 1) | (id_hi & 1);
1189 id_hi >>= 1;
1190 }
1191 }
1192
1193 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1194 id_bit = rev_id & 1;
1195
1196 if (i % 4 == 0) {
1197 // Don't write row parity bit at start of parsing
1198 if (i)
1199 id = (id << 1) | r_parity;
1200 // Start counting parity for new row
1201 r_parity = id_bit;
1202 } else {
1203 // Count row parity
1204 r_parity ^= id_bit;
1205 }
1206
1207 // First elements in column?
1208 if (i < 4)
1209 // Fill out first elements
1210 c_parity[i] = id_bit;
1211 else
1212 // Count column parity
1213 c_parity[i % 4] ^= id_bit;
1214
1215 // Insert ID bit
1216 id = (id << 1) | id_bit;
1217 rev_id >>= 1;
1218 }
1219
1220 // Insert parity bit of last row
1221 id = (id << 1) | r_parity;
1222
1223 // Fill out column parity at the end of tag
1224 for (i = 0; i < 4; ++i)
1225 id = (id << 1) | c_parity[i];
1226
1227 // Add stop bit
1228 id <<= 1;
1229
1230 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1231 LED_D_ON();
1232
1233 // Write EM410x ID
1234 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1235 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1236
1237 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1238 if (card) {
1239 // Clock rate is stored in bits 8-15 of the card value
1240 clock = (card & 0xFF00) >> 8;
1241 Dbprintf("Clock rate: %d", clock);
1242 switch (clock)
1243 {
1244 case 32:
1245 clock = T55x7_BITRATE_RF_32;
1246 break;
1247 case 16:
1248 clock = T55x7_BITRATE_RF_16;
1249 break;
1250 case 0:
1251 // A value of 0 is assumed to be 64 for backwards-compatibility
1252 // Fall through...
1253 case 64:
1254 clock = T55x7_BITRATE_RF_64;
1255 break;
1256 default:
1257 Dbprintf("Invalid clock rate: %d", clock);
1258 return;
1259 }
1260
1261 // Writing configuration for T55x7 tag
1262 T55xxWriteBlock(clock |
1263 T55x7_MODULATION_MANCHESTER |
1264 2 << T55x7_MAXBLOCK_SHIFT,
1265 0, 0, 0);
1266 }
1267 else
1268 // Writing configuration for T5555(Q5) tag
1269 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1270 T5555_MODULATION_MANCHESTER |
1271 2 << T5555_MAXBLOCK_SHIFT,
1272 0, 0, 0);
1273
1274 LED_D_OFF();
1275 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1276 (uint32_t)(id >> 32), (uint32_t)id);
1277 }
1278
1279 // Clone Indala 64-bit tag by UID to T55x7
1280 void CopyIndala64toT55x7(int hi, int lo)
1281 {
1282
1283 //Program the 2 data blocks for supplied 64bit UID
1284 // and the block 0 for Indala64 format
1285 T55xxWriteBlock(hi,1,0,0);
1286 T55xxWriteBlock(lo,2,0,0);
1287 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1288 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1289 T55x7_MODULATION_PSK1 |
1290 2 << T55x7_MAXBLOCK_SHIFT,
1291 0, 0, 0);
1292 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1293 // T5567WriteBlock(0x603E1042,0);
1294
1295 DbpString("DONE!");
1296
1297 }
1298
1299 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1300 {
1301
1302 //Program the 7 data blocks for supplied 224bit UID
1303 // and the block 0 for Indala224 format
1304 T55xxWriteBlock(uid1,1,0,0);
1305 T55xxWriteBlock(uid2,2,0,0);
1306 T55xxWriteBlock(uid3,3,0,0);
1307 T55xxWriteBlock(uid4,4,0,0);
1308 T55xxWriteBlock(uid5,5,0,0);
1309 T55xxWriteBlock(uid6,6,0,0);
1310 T55xxWriteBlock(uid7,7,0,0);
1311 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1312 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1313 T55x7_MODULATION_PSK1 |
1314 7 << T55x7_MAXBLOCK_SHIFT,
1315 0,0,0);
1316 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1317 // T5567WriteBlock(0x603E10E2,0);
1318
1319 DbpString("DONE!");
1320
1321 }
1322
1323
1324 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1325 #define max(x,y) ( x<y ? y:x)
1326
1327 int DemodPCF7931(uint8_t **outBlocks) {
1328 uint8_t BitStream[256];
1329 uint8_t Blocks[8][16];
1330 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1331 int GraphTraceLen = sizeof(BigBuf);
1332 int i, j, lastval, bitidx, half_switch;
1333 int clock = 64;
1334 int tolerance = clock / 8;
1335 int pmc, block_done;
1336 int lc, warnings = 0;
1337 int num_blocks = 0;
1338 int lmin=128, lmax=128;
1339 uint8_t dir;
1340
1341 AcquireRawAdcSamples125k(0);
1342
1343 lmin = 64;
1344 lmax = 192;
1345
1346 i = 2;
1347
1348 /* Find first local max/min */
1349 if(GraphBuffer[1] > GraphBuffer[0]) {
1350 while(i < GraphTraceLen) {
1351 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1352 break;
1353 i++;
1354 }
1355 dir = 0;
1356 }
1357 else {
1358 while(i < GraphTraceLen) {
1359 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1360 break;
1361 i++;
1362 }
1363 dir = 1;
1364 }
1365
1366 lastval = i++;
1367 half_switch = 0;
1368 pmc = 0;
1369 block_done = 0;
1370
1371 for (bitidx = 0; i < GraphTraceLen; i++)
1372 {
1373 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1374 {
1375 lc = i - lastval;
1376 lastval = i;
1377
1378 // Switch depending on lc length:
1379 // Tolerance is 1/8 of clock rate (arbitrary)
1380 if (abs(lc-clock/4) < tolerance) {
1381 // 16T0
1382 if((i - pmc) == lc) { /* 16T0 was previous one */
1383 /* It's a PMC ! */
1384 i += (128+127+16+32+33+16)-1;
1385 lastval = i;
1386 pmc = 0;
1387 block_done = 1;
1388 }
1389 else {
1390 pmc = i;
1391 }
1392 } else if (abs(lc-clock/2) < tolerance) {
1393 // 32TO
1394 if((i - pmc) == lc) { /* 16T0 was previous one */
1395 /* It's a PMC ! */
1396 i += (128+127+16+32+33)-1;
1397 lastval = i;
1398 pmc = 0;
1399 block_done = 1;
1400 }
1401 else if(half_switch == 1) {
1402 BitStream[bitidx++] = 0;
1403 half_switch = 0;
1404 }
1405 else
1406 half_switch++;
1407 } else if (abs(lc-clock) < tolerance) {
1408 // 64TO
1409 BitStream[bitidx++] = 1;
1410 } else {
1411 // Error
1412 warnings++;
1413 if (warnings > 10)
1414 {
1415 Dbprintf("Error: too many detection errors, aborting.");
1416 return 0;
1417 }
1418 }
1419
1420 if(block_done == 1) {
1421 if(bitidx == 128) {
1422 for(j=0; j<16; j++) {
1423 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1424 64*BitStream[j*8+6]+
1425 32*BitStream[j*8+5]+
1426 16*BitStream[j*8+4]+
1427 8*BitStream[j*8+3]+
1428 4*BitStream[j*8+2]+
1429 2*BitStream[j*8+1]+
1430 BitStream[j*8];
1431 }
1432 num_blocks++;
1433 }
1434 bitidx = 0;
1435 block_done = 0;
1436 half_switch = 0;
1437 }
1438 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1439 else dir = 1;
1440 }
1441 if(bitidx==255)
1442 bitidx=0;
1443 warnings = 0;
1444 if(num_blocks == 4) break;
1445 }
1446 memcpy(outBlocks, Blocks, 16*num_blocks);
1447 return num_blocks;
1448 }
1449
1450 int IsBlock0PCF7931(uint8_t *Block) {
1451 // Assume RFU means 0 :)
1452 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1453 return 1;
1454 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1455 return 1;
1456 return 0;
1457 }
1458
1459 int IsBlock1PCF7931(uint8_t *Block) {
1460 // Assume RFU means 0 :)
1461 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1462 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1463 return 1;
1464
1465 return 0;
1466 }
1467
1468 #define ALLOC 16
1469
1470 void ReadPCF7931() {
1471 uint8_t Blocks[8][17];
1472 uint8_t tmpBlocks[4][16];
1473 int i, j, ind, ind2, n;
1474 int num_blocks = 0;
1475 int max_blocks = 8;
1476 int ident = 0;
1477 int error = 0;
1478 int tries = 0;
1479
1480 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1481
1482 do {
1483 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1484 n = DemodPCF7931((uint8_t**)tmpBlocks);
1485 if(!n)
1486 error++;
1487 if(error==10 && num_blocks == 0) {
1488 Dbprintf("Error, no tag or bad tag");
1489 return;
1490 }
1491 else if (tries==20 || error==10) {
1492 Dbprintf("Error reading the tag");
1493 Dbprintf("Here is the partial content");
1494 goto end;
1495 }
1496
1497 for(i=0; i<n; i++)
1498 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1499 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1500 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1501 if(!ident) {
1502 for(i=0; i<n; i++) {
1503 if(IsBlock0PCF7931(tmpBlocks[i])) {
1504 // Found block 0 ?
1505 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1506 // Found block 1!
1507 // \o/
1508 ident = 1;
1509 memcpy(Blocks[0], tmpBlocks[i], 16);
1510 Blocks[0][ALLOC] = 1;
1511 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1512 Blocks[1][ALLOC] = 1;
1513 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1514 // Debug print
1515 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1516 num_blocks = 2;
1517 // Handle following blocks
1518 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1519 if(j==n) j=0;
1520 if(j==i) break;
1521 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1522 Blocks[ind2][ALLOC] = 1;
1523 }
1524 break;
1525 }
1526 }
1527 }
1528 }
1529 else {
1530 for(i=0; i<n; i++) { // Look for identical block in known blocks
1531 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1532 for(j=0; j<max_blocks; j++) {
1533 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1534 // Found an identical block
1535 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1536 if(ind2 < 0)
1537 ind2 = max_blocks;
1538 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1539 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1540 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1541 Blocks[ind2][ALLOC] = 1;
1542 num_blocks++;
1543 if(num_blocks == max_blocks) goto end;
1544 }
1545 }
1546 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1547 if(ind2 > max_blocks)
1548 ind2 = 0;
1549 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1550 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1551 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1552 Blocks[ind2][ALLOC] = 1;
1553 num_blocks++;
1554 if(num_blocks == max_blocks) goto end;
1555 }
1556 }
1557 }
1558 }
1559 }
1560 }
1561 }
1562 tries++;
1563 if (BUTTON_PRESS()) return;
1564 } while (num_blocks != max_blocks);
1565 end:
1566 Dbprintf("-----------------------------------------");
1567 Dbprintf("Memory content:");
1568 Dbprintf("-----------------------------------------");
1569 for(i=0; i<max_blocks; i++) {
1570 if(Blocks[i][ALLOC]==1)
1571 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1572 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1573 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1574 else
1575 Dbprintf("<missing block %d>", i);
1576 }
1577 Dbprintf("-----------------------------------------");
1578
1579 return ;
1580 }
1581
1582
1583 //-----------------------------------
1584 // EM4469 / EM4305 routines
1585 //-----------------------------------
1586 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1587 #define FWD_CMD_WRITE 0xA
1588 #define FWD_CMD_READ 0x9
1589 #define FWD_CMD_DISABLE 0x5
1590
1591
1592 uint8_t forwardLink_data[64]; //array of forwarded bits
1593 uint8_t * forward_ptr; //ptr for forward message preparation
1594 uint8_t fwd_bit_sz; //forwardlink bit counter
1595 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1596
1597 //====================================================================
1598 // prepares command bits
1599 // see EM4469 spec
1600 //====================================================================
1601 //--------------------------------------------------------------------
1602 uint8_t Prepare_Cmd( uint8_t cmd ) {
1603 //--------------------------------------------------------------------
1604
1605 *forward_ptr++ = 0; //start bit
1606 *forward_ptr++ = 0; //second pause for 4050 code
1607
1608 *forward_ptr++ = cmd;
1609 cmd >>= 1;
1610 *forward_ptr++ = cmd;
1611 cmd >>= 1;
1612 *forward_ptr++ = cmd;
1613 cmd >>= 1;
1614 *forward_ptr++ = cmd;
1615
1616 return 6; //return number of emited bits
1617 }
1618
1619 //====================================================================
1620 // prepares address bits
1621 // see EM4469 spec
1622 //====================================================================
1623
1624 //--------------------------------------------------------------------
1625 uint8_t Prepare_Addr( uint8_t addr ) {
1626 //--------------------------------------------------------------------
1627
1628 register uint8_t line_parity;
1629
1630 uint8_t i;
1631 line_parity = 0;
1632 for(i=0;i<6;i++) {
1633 *forward_ptr++ = addr;
1634 line_parity ^= addr;
1635 addr >>= 1;
1636 }
1637
1638 *forward_ptr++ = (line_parity & 1);
1639
1640 return 7; //return number of emited bits
1641 }
1642
1643 //====================================================================
1644 // prepares data bits intreleaved with parity bits
1645 // see EM4469 spec
1646 //====================================================================
1647
1648 //--------------------------------------------------------------------
1649 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1650 //--------------------------------------------------------------------
1651
1652 register uint8_t line_parity;
1653 register uint8_t column_parity;
1654 register uint8_t i, j;
1655 register uint16_t data;
1656
1657 data = data_low;
1658 column_parity = 0;
1659
1660 for(i=0; i<4; i++) {
1661 line_parity = 0;
1662 for(j=0; j<8; j++) {
1663 line_parity ^= data;
1664 column_parity ^= (data & 1) << j;
1665 *forward_ptr++ = data;
1666 data >>= 1;
1667 }
1668 *forward_ptr++ = line_parity;
1669 if(i == 1)
1670 data = data_hi;
1671 }
1672
1673 for(j=0; j<8; j++) {
1674 *forward_ptr++ = column_parity;
1675 column_parity >>= 1;
1676 }
1677 *forward_ptr = 0;
1678
1679 return 45; //return number of emited bits
1680 }
1681
1682 //====================================================================
1683 // Forward Link send function
1684 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1685 // fwd_bit_count set with number of bits to be sent
1686 //====================================================================
1687 void SendForward(uint8_t fwd_bit_count) {
1688
1689 fwd_write_ptr = forwardLink_data;
1690 fwd_bit_sz = fwd_bit_count;
1691
1692 LED_D_ON();
1693
1694 //Field on
1695 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1696 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1697
1698 // Give it a bit of time for the resonant antenna to settle.
1699 // And for the tag to fully power up
1700 SpinDelay(150);
1701
1702 // force 1st mod pulse (start gap must be longer for 4305)
1703 fwd_bit_sz--; //prepare next bit modulation
1704 fwd_write_ptr++;
1705 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1706 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1707 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1708 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
1709 SpinDelayUs(16*8); //16 cycles on (8us each)
1710
1711 // now start writting
1712 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1713 if(((*fwd_write_ptr++) & 1) == 1)
1714 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1715 else {
1716 //These timings work for 4469/4269/4305 (with the 55*8 above)
1717 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1718 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1719 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1720 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
1721 SpinDelayUs(9*8); //16 cycles on (8us each)
1722 }
1723 }
1724 }
1725
1726 void EM4xLogin(uint32_t Password) {
1727
1728 uint8_t fwd_bit_count;
1729
1730 forward_ptr = forwardLink_data;
1731 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1732 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1733
1734 SendForward(fwd_bit_count);
1735
1736 //Wait for command to complete
1737 SpinDelay(20);
1738
1739 }
1740
1741 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1742
1743 uint8_t fwd_bit_count;
1744 uint8_t *dest = (uint8_t *)BigBuf;
1745 int m=0, i=0;
1746
1747 //If password mode do login
1748 if (PwdMode == 1) EM4xLogin(Pwd);
1749
1750 forward_ptr = forwardLink_data;
1751 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1752 fwd_bit_count += Prepare_Addr( Address );
1753
1754 m = sizeof(BigBuf);
1755 // Clear destination buffer before sending the command
1756 memset(dest, 128, m);
1757 // Connect the A/D to the peak-detected low-frequency path.
1758 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1759 // Now set up the SSC to get the ADC samples that are now streaming at us.
1760 FpgaSetupSsc();
1761
1762 SendForward(fwd_bit_count);
1763
1764 // Now do the acquisition
1765 i = 0;
1766 for(;;) {
1767 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1768 AT91C_BASE_SSC->SSC_THR = 0x43;
1769 }
1770 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1771 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1772 i++;
1773 if (i >= m) break;
1774 }
1775 }
1776 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1777 LED_D_OFF();
1778 }
1779
1780 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1781
1782 uint8_t fwd_bit_count;
1783
1784 //If password mode do login
1785 if (PwdMode == 1) EM4xLogin(Pwd);
1786
1787 forward_ptr = forwardLink_data;
1788 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1789 fwd_bit_count += Prepare_Addr( Address );
1790 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1791
1792 SendForward(fwd_bit_count);
1793
1794 //Wait for write to complete
1795 SpinDelay(20);
1796 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1797 LED_D_OFF();
1798 }
Proxmark3 GIT tracking
Impressum, Datenschutz