]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
add l/h option to hw tune and optimize order of tuning
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 /**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
30 {
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40 //clear read buffer
41 BigBuf_Clear_keep_EM();
42
43 /* Make sure the tag is reset */
44 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
45 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
46 SpinDelay(2500);
47
48 LFSetupFPGAForADC(sc.divisor, 1);
49
50 // And a little more time for the tag to fully power up
51 SpinDelay(2000);
52
53 // now modulate the reader field
54 while(*command != '\0' && *command != ' ') {
55 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
56 LED_D_OFF();
57 SpinDelayUs(delay_off);
58 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
59
60 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
61 LED_D_ON();
62 if(*(command++) == '0')
63 SpinDelayUs(period_0);
64 else
65 SpinDelayUs(period_1);
66 }
67 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
68 LED_D_OFF();
69 SpinDelayUs(delay_off);
70 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
71
72 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
73
74 // now do the read
75 DoAcquisition_config(false);
76 }
77
78 /* blank r/w tag data stream
79 ...0000000000000000 01111111
80 1010101010101010101010101010101010101010101010101010101010101010
81 0011010010100001
82 01111111
83 101010101010101[0]000...
84
85 [5555fe852c5555555555555555fe0000]
86 */
87 void ReadTItag(void)
88 {
89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
180 if (shift3 & (1<<15) ) {
181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
215 }
216
217 void WriteTIbyte(uint8_t b)
218 {
219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
240 }
241
242 void AcquireTiType(void)
243 {
244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
247 #define TIBUFLEN 1250
248
249 // clear buffer
250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
251 BigBuf_Clear_ext(false);
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311 }
312
313 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314 // if crc provided, it will be written with the data verbatim (even if bogus)
315 // if not provided a valid crc will be computed from the data and written.
316 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317 {
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use tiread to check");
383 }
384
385 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386 {
387 int i;
388 uint8_t *tab = BigBuf_get_addr();
389
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
392
393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
394
395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
405 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
440 }
441
442 #define DEBUG_FRAME_CONTENTS 1
443 void SimulateTagLowFrequencyBidir(int divisor, int t0)
444 {
445 }
446
447 // compose fc/8 fc/10 waveform (FSK2)
448 static void fc(int c, int *n)
449 {
450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
494 }
495 // compose fc/X fc/Y waveform (FSKx)
496 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
497 {
498 uint8_t *dest = BigBuf_get_addr();
499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
504 // loop through clock - step field clock
505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
517 }
518 }
519 if (mod>0 && !modAdjOk){ //fsk1
520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
523 }
524 }
525
526 // prepare a waveform pattern in the buffer based on the ID given then
527 // simulate a HID tag until the button is pressed
528 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529 {
530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
580 }
581
582 // prepare a waveform pattern in the buffer based on the ID given then
583 // simulate a FSK tag until the button is pressed
584 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586 {
587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
594
595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
603 /*Dbprintf("DEBUG: First 32:");
604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
609 */
610 if (ledcontrol)
611 LED_A_ON();
612
613 SimulateTagLowFrequency(n, 0, ledcontrol);
614
615 if (ledcontrol)
616 LED_A_OFF();
617 }
618
619 // compose ask waveform for one bit(ASK)
620 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
621 {
622 uint8_t *dest = BigBuf_get_addr();
623 uint8_t halfClk = clock/2;
624 // c = current bit 1 or 0
625 if (manchester==1){
626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
628 } else {
629 memset(dest+(*n), c, clock);
630 }
631 *n += clock;
632 }
633
634 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
635 {
636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 if (c){
639 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
640 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
641 } else {
642 memset(dest+(*n), c ^ *phase, clock);
643 *phase ^= 1;
644 }
645 }
646
647 // args clock, ask/man or askraw, invert, transmission separator
648 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
649 {
650 int ledcontrol = 1;
651 int n=0, i=0;
652 uint8_t clk = (arg1 >> 8) & 0xFF;
653 uint8_t encoding = arg1 & 0xFF;
654 uint8_t separator = arg2 & 1;
655 uint8_t invert = (arg2 >> 8) & 1;
656
657 if (encoding==2){ //biphase
658 uint8_t phase=0;
659 for (i=0; i<size; i++){
660 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
661 }
662 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
663 for (i=0; i<size; i++){
664 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
665 }
666 }
667 } else { // ask/manchester || ask/raw
668 for (i=0; i<size; i++){
669 askSimBit(BitStream[i]^invert, &n, clk, encoding);
670 }
671 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
672 for (i=0; i<size; i++){
673 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
674 }
675 }
676 }
677
678 if (separator==1) Dbprintf("sorry but separator option not yet available");
679
680 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
681 //DEBUG
682 //Dbprintf("First 32:");
683 //uint8_t *dest = BigBuf_get_addr();
684 //i=0;
685 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
686 //i+=16;
687 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
688
689 if (ledcontrol) LED_A_ON();
690 SimulateTagLowFrequency(n, 0, ledcontrol);
691 if (ledcontrol) LED_A_OFF();
692 }
693
694 //carrier can be 2,4 or 8
695 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
696 {
697 uint8_t *dest = BigBuf_get_addr();
698 uint8_t halfWave = waveLen/2;
699 //uint8_t idx;
700 int i = 0;
701 if (phaseChg){
702 // write phase change
703 memset(dest+(*n), *curPhase^1, halfWave);
704 memset(dest+(*n) + halfWave, *curPhase, halfWave);
705 *n += waveLen;
706 *curPhase ^= 1;
707 i += waveLen;
708 }
709 //write each normal clock wave for the clock duration
710 for (; i < clk; i+=waveLen){
711 memset(dest+(*n), *curPhase, halfWave);
712 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
713 *n += waveLen;
714 }
715 }
716
717 // args clock, carrier, invert,
718 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
719 {
720 int ledcontrol=1;
721 int n=0, i=0;
722 uint8_t clk = arg1 >> 8;
723 uint8_t carrier = arg1 & 0xFF;
724 uint8_t invert = arg2 & 0xFF;
725 uint8_t curPhase = 0;
726 for (i=0; i<size; i++){
727 if (BitStream[i] == curPhase){
728 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
729 } else {
730 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
731 }
732 }
733 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
734 //Dbprintf("DEBUG: First 32:");
735 //uint8_t *dest = BigBuf_get_addr();
736 //i=0;
737 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
738 //i+=16;
739 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
740
741 if (ledcontrol) LED_A_ON();
742 SimulateTagLowFrequency(n, 0, ledcontrol);
743 if (ledcontrol) LED_A_OFF();
744 }
745
746 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
747 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
748 {
749 uint8_t *dest = BigBuf_get_addr();
750 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
751 size_t size;
752 uint32_t hi2=0, hi=0, lo=0;
753 int idx=0;
754 // Configure to go in 125Khz listen mode
755 LFSetupFPGAForADC(95, true);
756
757 //clear read buffer
758 BigBuf_Clear_keep_EM();
759
760 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
761
762 WDT_HIT();
763 if (ledcontrol) LED_A_ON();
764
765 DoAcquisition_default(-1,true);
766 // FSK demodulator
767 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
768 size = 50*128*2; //big enough to catch 2 sequences of largest format
769 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
770
771 if (idx>0 && lo>0 && (size==96 || size==192)){
772 // go over previously decoded manchester data and decode into usable tag ID
773 if (hi2 != 0){ //extra large HID tags 88/192 bits
774 Dbprintf("TAG ID: %x%08x%08x (%d)",
775 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
776 }else { //standard HID tags 44/96 bits
777 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
778 uint8_t bitlen = 0;
779 uint32_t fc = 0;
780 uint32_t cardnum = 0;
781 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
782 uint32_t lo2=0;
783 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
784 uint8_t idx3 = 1;
785 while(lo2 > 1){ //find last bit set to 1 (format len bit)
786 lo2=lo2 >> 1;
787 idx3++;
788 }
789 bitlen = idx3+19;
790 fc =0;
791 cardnum=0;
792 if(bitlen == 26){
793 cardnum = (lo>>1)&0xFFFF;
794 fc = (lo>>17)&0xFF;
795 }
796 if(bitlen == 37){
797 cardnum = (lo>>1)&0x7FFFF;
798 fc = ((hi&0xF)<<12)|(lo>>20);
799 }
800 if(bitlen == 34){
801 cardnum = (lo>>1)&0xFFFF;
802 fc= ((hi&1)<<15)|(lo>>17);
803 }
804 if(bitlen == 35){
805 cardnum = (lo>>1)&0xFFFFF;
806 fc = ((hi&1)<<11)|(lo>>21);
807 }
808 }
809 else { //if bit 38 is not set then 37 bit format is used
810 bitlen= 37;
811 fc =0;
812 cardnum=0;
813 if(bitlen==37){
814 cardnum = (lo>>1)&0x7FFFF;
815 fc = ((hi&0xF)<<12)|(lo>>20);
816 }
817 }
818 //Dbprintf("TAG ID: %x%08x (%d)",
819 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
820 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
821 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
822 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
823 }
824 if (findone){
825 if (ledcontrol) LED_A_OFF();
826 *high = hi;
827 *low = lo;
828 return;
829 }
830 // reset
831 }
832 hi2 = hi = lo = idx = 0;
833 WDT_HIT();
834 }
835 DbpString("Stopped");
836 if (ledcontrol) LED_A_OFF();
837 }
838
839 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
840 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
841 {
842 uint8_t *dest = BigBuf_get_addr();
843 size_t size;
844 int idx=0;
845 //clear read buffer
846 BigBuf_Clear_keep_EM();
847 // Configure to go in 125Khz listen mode
848 LFSetupFPGAForADC(95, true);
849
850 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
851
852 WDT_HIT();
853 if (ledcontrol) LED_A_ON();
854
855 DoAcquisition_default(-1,true);
856 // FSK demodulator
857 size = 50*128*2; //big enough to catch 2 sequences of largest format
858 idx = AWIDdemodFSK(dest, &size);
859
860 if (idx<=0 || size!=96) continue;
861 // Index map
862 // 0 10 20 30 40 50 60
863 // | | | | | | |
864 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
865 // -----------------------------------------------------------------------------
866 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
867 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
868 // |---26 bit---| |-----117----||-------------142-------------|
869 // b = format bit len, o = odd parity of last 3 bits
870 // f = facility code, c = card number
871 // w = wiegand parity
872 // (26 bit format shown)
873
874 //get raw ID before removing parities
875 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
876 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
877 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
878
879 size = removeParity(dest, idx+8, 4, 1, 88);
880 if (size != 66) continue;
881 // ok valid card found!
882
883 // Index map
884 // 0 10 20 30 40 50 60
885 // | | | | | | |
886 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
887 // -----------------------------------------------------------------------------
888 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
889 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
890 // |26 bit| |-117--| |-----142------|
891 // b = format bit len, o = odd parity of last 3 bits
892 // f = facility code, c = card number
893 // w = wiegand parity
894 // (26 bit format shown)
895
896 uint32_t fc = 0;
897 uint32_t cardnum = 0;
898 uint32_t code1 = 0;
899 uint32_t code2 = 0;
900 uint8_t fmtLen = bytebits_to_byte(dest,8);
901 if (fmtLen==26){
902 fc = bytebits_to_byte(dest+9, 8);
903 cardnum = bytebits_to_byte(dest+17, 16);
904 code1 = bytebits_to_byte(dest+8,fmtLen);
905 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
906 } else {
907 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
908 if (fmtLen>32){
909 code1 = bytebits_to_byte(dest+8,fmtLen-32);
910 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
911 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
912 } else{
913 code1 = bytebits_to_byte(dest+8,fmtLen);
914 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
915 }
916 }
917 if (findone){
918 if (ledcontrol) LED_A_OFF();
919 return;
920 }
921 // reset
922 idx = 0;
923 WDT_HIT();
924 }
925 DbpString("Stopped");
926 if (ledcontrol) LED_A_OFF();
927 }
928
929 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
930 {
931 uint8_t *dest = BigBuf_get_addr();
932
933 size_t size=0, idx=0;
934 int clk=0, invert=0, errCnt=0, maxErr=20;
935 uint32_t hi=0;
936 uint64_t lo=0;
937 //clear read buffer
938 BigBuf_Clear_keep_EM();
939 // Configure to go in 125Khz listen mode
940 LFSetupFPGAForADC(95, true);
941
942 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
943
944 WDT_HIT();
945 if (ledcontrol) LED_A_ON();
946
947 DoAcquisition_default(-1,true);
948 size = BigBuf_max_traceLen();
949 //askdemod and manchester decode
950 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
951 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
952 WDT_HIT();
953
954 if (errCnt<0) continue;
955
956 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
957 if (errCnt){
958 if (size>64){
959 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
960 hi,
961 (uint32_t)(lo>>32),
962 (uint32_t)lo,
963 (uint32_t)(lo&0xFFFF),
964 (uint32_t)((lo>>16LL) & 0xFF),
965 (uint32_t)(lo & 0xFFFFFF));
966 } else {
967 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
968 (uint32_t)(lo>>32),
969 (uint32_t)lo,
970 (uint32_t)(lo&0xFFFF),
971 (uint32_t)((lo>>16LL) & 0xFF),
972 (uint32_t)(lo & 0xFFFFFF));
973 }
974
975 if (findone){
976 if (ledcontrol) LED_A_OFF();
977 *high=lo>>32;
978 *low=lo & 0xFFFFFFFF;
979 return;
980 }
981 }
982 WDT_HIT();
983 hi = lo = size = idx = 0;
984 clk = invert = errCnt = 0;
985 }
986 DbpString("Stopped");
987 if (ledcontrol) LED_A_OFF();
988 }
989
990 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
991 {
992 uint8_t *dest = BigBuf_get_addr();
993 int idx=0;
994 uint32_t code=0, code2=0;
995 uint8_t version=0;
996 uint8_t facilitycode=0;
997 uint16_t number=0;
998 //clear read buffer
999 BigBuf_Clear_keep_EM();
1000 // Configure to go in 125Khz listen mode
1001 LFSetupFPGAForADC(95, true);
1002
1003 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1004 WDT_HIT();
1005 if (ledcontrol) LED_A_ON();
1006 DoAcquisition_default(-1,true);
1007 //fskdemod and get start index
1008 WDT_HIT();
1009 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1010 if (idx<0) continue;
1011 //valid tag found
1012
1013 //Index map
1014 //0 10 20 30 40 50 60
1015 //| | | | | | |
1016 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1017 //-----------------------------------------------------------------------------
1018 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
1019 //
1020 //XSF(version)facility:codeone+codetwo
1021 //Handle the data
1022 if(findone){ //only print binary if we are doing one
1023 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1024 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1025 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1026 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1027 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1028 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1029 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1030 }
1031 code = bytebits_to_byte(dest+idx,32);
1032 code2 = bytebits_to_byte(dest+idx+32,32);
1033 version = bytebits_to_byte(dest+idx+27,8); //14,4
1034 facilitycode = bytebits_to_byte(dest+idx+18,8);
1035 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1036
1037 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
1038 // if we're only looking for one tag
1039 if (findone){
1040 if (ledcontrol) LED_A_OFF();
1041 //LED_A_OFF();
1042 *high=code;
1043 *low=code2;
1044 return;
1045 }
1046 code=code2=0;
1047 version=facilitycode=0;
1048 number=0;
1049 idx=0;
1050
1051 WDT_HIT();
1052 }
1053 DbpString("Stopped");
1054 if (ledcontrol) LED_A_OFF();
1055 }
1056
1057 /*------------------------------
1058 * T5555/T5557/T5567/T5577 routines
1059 *------------------------------
1060 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1061 *
1062 * Relevant communication times in microsecond
1063 * To compensate antenna falling times shorten the write times
1064 * and enlarge the gap ones.
1065 * Q5 tags seems to have issues when these values changes.
1066 */
1067 #define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1068 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1069 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1070 #define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
1071 #define READ_GAP 15*8
1072
1073 void TurnReadLFOn(int delay) {
1074 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1075 // Give it a bit of time for the resonant antenna to settle.
1076 SpinDelayUs(delay); //155*8 //50*8
1077 }
1078
1079 // Write one bit to card
1080 void T55xxWriteBit(int bit) {
1081 if (!bit)
1082 TurnReadLFOn(WRITE_0);
1083 else
1084 TurnReadLFOn(WRITE_1);
1085 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1086 SpinDelayUs(WRITE_GAP);
1087 }
1088
1089 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1090 void T55xxResetRead(void) {
1091 LED_A_ON();
1092 //clear buffer now so it does not interfere with timing later
1093 BigBuf_Clear_keep_EM();
1094
1095 // Set up FPGA, 125kHz
1096 LFSetupFPGAForADC(95, true);
1097
1098 // Trigger T55x7 in mode.
1099 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1100 SpinDelayUs(START_GAP);
1101
1102 // reset tag - op code 00
1103 T55xxWriteBit(0);
1104 T55xxWriteBit(0);
1105
1106 // Turn field on to read the response
1107 TurnReadLFOn(READ_GAP);
1108
1109 // Acquisition
1110 doT55x7Acquisition(BigBuf_max_traceLen());
1111
1112 // Turn the field off
1113 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1114 cmd_send(CMD_ACK,0,0,0,0,0);
1115 LED_A_OFF();
1116 }
1117
1118 // Write one card block in page 0, no lock
1119 void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
1120 LED_A_ON();
1121 bool PwdMode = arg & 0x1;
1122 uint8_t Page = (arg & 0x2)>>1;
1123 uint32_t i = 0;
1124
1125 // Set up FPGA, 125kHz
1126 LFSetupFPGAForADC(95, true);
1127
1128 // Trigger T55x7 in mode.
1129 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1130 SpinDelayUs(START_GAP);
1131
1132 // Opcode 10
1133 T55xxWriteBit(1);
1134 T55xxWriteBit(Page); //Page 0
1135 if (PwdMode){
1136 // Send Pwd
1137 for (i = 0x80000000; i != 0; i >>= 1)
1138 T55xxWriteBit(Pwd & i);
1139 }
1140 // Send Lock bit
1141 T55xxWriteBit(0);
1142
1143 // Send Data
1144 for (i = 0x80000000; i != 0; i >>= 1)
1145 T55xxWriteBit(Data & i);
1146
1147 // Send Block number
1148 for (i = 0x04; i != 0; i >>= 1)
1149 T55xxWriteBit(Block & i);
1150
1151 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1152 // so wait a little more)
1153 TurnReadLFOn(20 * 1000);
1154 //could attempt to do a read to confirm write took
1155 // as the tag should repeat back the new block
1156 // until it is reset, but to confirm it we would
1157 // need to know the current block 0 config mode
1158
1159 // turn field off
1160 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1161 LED_A_OFF();
1162 }
1163
1164 // Write one card block in page 0, no lock
1165 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
1166 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1167 cmd_send(CMD_ACK,0,0,0,0,0);
1168 }
1169
1170 // Read one card block in page [page]
1171 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1172 LED_A_ON();
1173 bool PwdMode = arg0 & 0x1;
1174 uint8_t Page = (arg0 & 0x2) >> 1;
1175 uint32_t i = 0;
1176 bool RegReadMode = (Block == 0xFF);
1177
1178 //clear buffer now so it does not interfere with timing later
1179 BigBuf_Clear_ext(false);
1180
1181 //make sure block is at max 7
1182 Block &= 0x7;
1183
1184 // Set up FPGA, 125kHz to power up the tag
1185 LFSetupFPGAForADC(95, true);
1186
1187 // Trigger T55x7 Direct Access Mode with start gap
1188 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1189 SpinDelayUs(START_GAP);
1190
1191 // Opcode 1[page]
1192 T55xxWriteBit(1);
1193 T55xxWriteBit(Page); //Page 0
1194
1195 if (PwdMode){
1196 // Send Pwd
1197 for (i = 0x80000000; i != 0; i >>= 1)
1198 T55xxWriteBit(Pwd & i);
1199 }
1200 // Send a zero bit separation
1201 T55xxWriteBit(0);
1202
1203 // Send Block number (if direct access mode)
1204 if (!RegReadMode)
1205 for (i = 0x04; i != 0; i >>= 1)
1206 T55xxWriteBit(Block & i);
1207
1208 // Turn field on to read the response
1209 TurnReadLFOn(READ_GAP);
1210
1211 // Acquisition
1212 doT55x7Acquisition(12000);
1213
1214 // Turn the field off
1215 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1216 cmd_send(CMD_ACK,0,0,0,0,0);
1217 LED_A_OFF();
1218 }
1219
1220 void T55xxWakeUp(uint32_t Pwd){
1221 LED_B_ON();
1222 uint32_t i = 0;
1223
1224 // Set up FPGA, 125kHz
1225 LFSetupFPGAForADC(95, true);
1226
1227 // Trigger T55x7 Direct Access Mode
1228 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1229 SpinDelayUs(START_GAP);
1230
1231 // Opcode 10
1232 T55xxWriteBit(1);
1233 T55xxWriteBit(0); //Page 0
1234
1235 // Send Pwd
1236 for (i = 0x80000000; i != 0; i >>= 1)
1237 T55xxWriteBit(Pwd & i);
1238
1239 // Turn and leave field on to let the begin repeating transmission
1240 TurnReadLFOn(20*1000);
1241 }
1242
1243 /*-------------- Cloning routines -----------*/
1244
1245 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1246 // write last block first and config block last (if included)
1247 for (uint8_t i = numblocks+startblock; i > startblock; i--) {
1248 T55xxWriteBlockExt(blockdata[i-1],i-1,0,0);
1249 }
1250 }
1251
1252 // Copy HID id to card and setup block 0 config
1253 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1254 uint32_t data[] = {0,0,0,0,0,0,0};
1255 uint8_t last_block = 0;
1256
1257 if (longFMT) {
1258 // Ensure no more than 84 bits supplied
1259 if (hi2>0xFFFFF) {
1260 DbpString("Tags can only have 84 bits.");
1261 return;
1262 }
1263 // Build the 6 data blocks for supplied 84bit ID
1264 last_block = 6;
1265 // load preamble (1D) & long format identifier (9E manchester encoded)
1266 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1267 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1268 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1269 data[3] = manchesterEncode2Bytes(hi >> 16);
1270 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1271 data[5] = manchesterEncode2Bytes(lo >> 16);
1272 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1273 } else {
1274 // Ensure no more than 44 bits supplied
1275 if (hi>0xFFF) {
1276 DbpString("Tags can only have 44 bits.");
1277 return;
1278 }
1279 // Build the 3 data blocks for supplied 44bit ID
1280 last_block = 3;
1281 // load preamble
1282 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1283 data[2] = manchesterEncode2Bytes(lo >> 16);
1284 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1285 }
1286 // load chip config block
1287 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1288
1289 //TODO add selection of chip for Q5 or T55x7
1290 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1291
1292 LED_D_ON();
1293 // Program the data blocks for supplied ID
1294 // and the block 0 for HID format
1295 WriteT55xx(data, 0, last_block+1);
1296
1297 LED_D_OFF();
1298
1299 DbpString("DONE!");
1300 }
1301
1302 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1303 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1304 //TODO add selection of chip for Q5 or T55x7
1305 // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1306
1307 LED_D_ON();
1308 // Program the data blocks for supplied ID
1309 // and the block 0 config
1310 WriteT55xx(data, 0, 3);
1311
1312 LED_D_OFF();
1313
1314 DbpString("DONE!");
1315 }
1316
1317 // Clone Indala 64-bit tag by UID to T55x7
1318 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1319 //Program the 2 data blocks for supplied 64bit UID
1320 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1321 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1322 //TODO add selection of chip for Q5 or T55x7
1323 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1324
1325 WriteT55xx(data, 0, 3);
1326 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1327 // T5567WriteBlock(0x603E1042,0);
1328 DbpString("DONE!");
1329 }
1330 // Clone Indala 224-bit tag by UID to T55x7
1331 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1332 //Program the 7 data blocks for supplied 224bit UID
1333 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1334 // and the block 0 for Indala224 format
1335 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1336 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1337 //TODO add selection of chip for Q5 or T55x7
1338 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1339 WriteT55xx(data, 0, 8);
1340 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1341 // T5567WriteBlock(0x603E10E2,0);
1342 DbpString("DONE!");
1343 }
1344 // clone viking tag to T55xx
1345 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1346 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1347 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1348 // Program the data blocks for supplied ID and the block 0 config
1349 WriteT55xx(data, 0, 3);
1350 LED_D_OFF();
1351 cmd_send(CMD_ACK,0,0,0,0,0);
1352 }
1353
1354 // Define 9bit header for EM410x tags
1355 #define EM410X_HEADER 0x1FF
1356 #define EM410X_ID_LENGTH 40
1357
1358 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1359 int i, id_bit;
1360 uint64_t id = EM410X_HEADER;
1361 uint64_t rev_id = 0; // reversed ID
1362 int c_parity[4]; // column parity
1363 int r_parity = 0; // row parity
1364 uint32_t clock = 0;
1365
1366 // Reverse ID bits given as parameter (for simpler operations)
1367 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1368 if (i < 32) {
1369 rev_id = (rev_id << 1) | (id_lo & 1);
1370 id_lo >>= 1;
1371 } else {
1372 rev_id = (rev_id << 1) | (id_hi & 1);
1373 id_hi >>= 1;
1374 }
1375 }
1376
1377 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1378 id_bit = rev_id & 1;
1379
1380 if (i % 4 == 0) {
1381 // Don't write row parity bit at start of parsing
1382 if (i)
1383 id = (id << 1) | r_parity;
1384 // Start counting parity for new row
1385 r_parity = id_bit;
1386 } else {
1387 // Count row parity
1388 r_parity ^= id_bit;
1389 }
1390
1391 // First elements in column?
1392 if (i < 4)
1393 // Fill out first elements
1394 c_parity[i] = id_bit;
1395 else
1396 // Count column parity
1397 c_parity[i % 4] ^= id_bit;
1398
1399 // Insert ID bit
1400 id = (id << 1) | id_bit;
1401 rev_id >>= 1;
1402 }
1403
1404 // Insert parity bit of last row
1405 id = (id << 1) | r_parity;
1406
1407 // Fill out column parity at the end of tag
1408 for (i = 0; i < 4; ++i)
1409 id = (id << 1) | c_parity[i];
1410
1411 // Add stop bit
1412 id <<= 1;
1413
1414 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1415 LED_D_ON();
1416
1417 // Write EM410x ID
1418 uint32_t data[] = {0, id>>32, id & 0xFFFFFFFF};
1419
1420 clock = (card & 0xFF00) >> 8;
1421 clock = (clock == 0) ? 64 : clock;
1422 Dbprintf("Clock rate: %d", clock);
1423 if (card & 0xFF) { //t55x7
1424 clock = GetT55xxClockBit(clock);
1425 if (clock == 0) {
1426 Dbprintf("Invalid clock rate: %d", clock);
1427 return;
1428 }
1429 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1430 } else { //t5555 (Q5)
1431 clock = (clock-2)>>1; //n = (RF-2)/2
1432 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1433 }
1434
1435 WriteT55xx(data, 0, 3);
1436
1437 LED_D_OFF();
1438 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1439 (uint32_t)(id >> 32), (uint32_t)id);
1440 }
1441
1442 //-----------------------------------
1443 // EM4469 / EM4305 routines
1444 //-----------------------------------
1445 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1446 #define FWD_CMD_WRITE 0xA
1447 #define FWD_CMD_READ 0x9
1448 #define FWD_CMD_DISABLE 0x5
1449
1450 uint8_t forwardLink_data[64]; //array of forwarded bits
1451 uint8_t * forward_ptr; //ptr for forward message preparation
1452 uint8_t fwd_bit_sz; //forwardlink bit counter
1453 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1454
1455 //====================================================================
1456 // prepares command bits
1457 // see EM4469 spec
1458 //====================================================================
1459 //--------------------------------------------------------------------
1460 // VALUES TAKEN FROM EM4x function: SendForward
1461 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1462 // WRITE_GAP = 128; (16*8)
1463 // WRITE_1 = 256 32*8; (32*8)
1464
1465 // These timings work for 4469/4269/4305 (with the 55*8 above)
1466 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1467
1468 uint8_t Prepare_Cmd( uint8_t cmd ) {
1469
1470 *forward_ptr++ = 0; //start bit
1471 *forward_ptr++ = 0; //second pause for 4050 code
1472
1473 *forward_ptr++ = cmd;
1474 cmd >>= 1;
1475 *forward_ptr++ = cmd;
1476 cmd >>= 1;
1477 *forward_ptr++ = cmd;
1478 cmd >>= 1;
1479 *forward_ptr++ = cmd;
1480
1481 return 6; //return number of emited bits
1482 }
1483
1484 //====================================================================
1485 // prepares address bits
1486 // see EM4469 spec
1487 //====================================================================
1488 uint8_t Prepare_Addr( uint8_t addr ) {
1489
1490 register uint8_t line_parity;
1491
1492 uint8_t i;
1493 line_parity = 0;
1494 for(i=0;i<6;i++) {
1495 *forward_ptr++ = addr;
1496 line_parity ^= addr;
1497 addr >>= 1;
1498 }
1499
1500 *forward_ptr++ = (line_parity & 1);
1501
1502 return 7; //return number of emited bits
1503 }
1504
1505 //====================================================================
1506 // prepares data bits intreleaved with parity bits
1507 // see EM4469 spec
1508 //====================================================================
1509 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1510
1511 register uint8_t line_parity;
1512 register uint8_t column_parity;
1513 register uint8_t i, j;
1514 register uint16_t data;
1515
1516 data = data_low;
1517 column_parity = 0;
1518
1519 for(i=0; i<4; i++) {
1520 line_parity = 0;
1521 for(j=0; j<8; j++) {
1522 line_parity ^= data;
1523 column_parity ^= (data & 1) << j;
1524 *forward_ptr++ = data;
1525 data >>= 1;
1526 }
1527 *forward_ptr++ = line_parity;
1528 if(i == 1)
1529 data = data_hi;
1530 }
1531
1532 for(j=0; j<8; j++) {
1533 *forward_ptr++ = column_parity;
1534 column_parity >>= 1;
1535 }
1536 *forward_ptr = 0;
1537
1538 return 45; //return number of emited bits
1539 }
1540
1541 //====================================================================
1542 // Forward Link send function
1543 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1544 // fwd_bit_count set with number of bits to be sent
1545 //====================================================================
1546 void SendForward(uint8_t fwd_bit_count) {
1547
1548 fwd_write_ptr = forwardLink_data;
1549 fwd_bit_sz = fwd_bit_count;
1550
1551 LED_D_ON();
1552
1553 // Set up FPGA, 125kHz
1554 LFSetupFPGAForADC(95, true);
1555
1556 // force 1st mod pulse (start gap must be longer for 4305)
1557 fwd_bit_sz--; //prepare next bit modulation
1558 fwd_write_ptr++;
1559 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1560 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1561 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1562 SpinDelayUs(16*8); //16 cycles on (8us each)
1563
1564 // now start writting
1565 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1566 if(((*fwd_write_ptr++) & 1) == 1)
1567 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1568 else {
1569 //These timings work for 4469/4269/4305 (with the 55*8 above)
1570 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1571 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1572 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1573 SpinDelayUs(9*8); //16 cycles on (8us each)
1574 }
1575 }
1576 }
1577
1578 void EM4xLogin(uint32_t Password) {
1579
1580 uint8_t fwd_bit_count;
1581
1582 forward_ptr = forwardLink_data;
1583 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1584 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1585
1586 SendForward(fwd_bit_count);
1587
1588 //Wait for command to complete
1589 SpinDelay(20);
1590 }
1591
1592 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1593
1594 uint8_t fwd_bit_count;
1595 uint8_t *dest = BigBuf_get_addr();
1596 uint16_t bufferlength = BigBuf_max_traceLen();
1597 uint32_t i = 0;
1598
1599 // Clear destination buffer before sending the command
1600 BigBuf_Clear_ext(false);
1601
1602 //If password mode do login
1603 if (PwdMode == 1) EM4xLogin(Pwd);
1604
1605 forward_ptr = forwardLink_data;
1606 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1607 fwd_bit_count += Prepare_Addr( Address );
1608
1609 // Connect the A/D to the peak-detected low-frequency path.
1610 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1611 // Now set up the SSC to get the ADC samples that are now streaming at us.
1612 FpgaSetupSsc();
1613
1614 SendForward(fwd_bit_count);
1615
1616 // Now do the acquisition
1617 i = 0;
1618 for(;;) {
1619 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1620 AT91C_BASE_SSC->SSC_THR = 0x43;
1621 }
1622 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1623 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1624 i++;
1625 if (i >= bufferlength) break;
1626 }
1627 }
1628 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1629 cmd_send(CMD_ACK,0,0,0,0,0);
1630 LED_D_OFF();
1631 }
1632
1633 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1634
1635 uint8_t fwd_bit_count;
1636
1637 //If password mode do login
1638 if (PwdMode == 1) EM4xLogin(Pwd);
1639
1640 forward_ptr = forwardLink_data;
1641 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1642 fwd_bit_count += Prepare_Addr( Address );
1643 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1644
1645 SendForward(fwd_bit_count);
1646
1647 //Wait for write to complete
1648 SpinDelay(20);
1649 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1650 LED_D_OFF();
1651 }
Proxmark3 GIT tracking
Impressum, Datenschutz