iso14444a: minor FPGA bugfix

diff --git a/fpga/fpga.bit b/fpga/fpga.bit
index 55dbfb8c361b8fcb54e3cdc3991e71cd88d0ff0d..f494783311398ea66fd32529687f55b09e320fb9 100644 (file)
Binary files a/fpga/fpga.bit and b/fpga/fpga.bit differ

diff --git a/fpga/hi_iso14443a.v b/fpga/hi_iso14443a.v
index 1ad485dd91c26542b3d45d92f64a5bdeb996c75e..ec5aa75771023b75fe5b7ee0426b7aac4d5390db 100644 (file)
--- a/fpga/hi_iso14443a.v
+++ b/fpga/hi_iso14443a.v
@@ -252,8 +252,6 @@ begin
        // check timing of a falling edge in reader signal
        if (pre_after_hysteresis && ~after_hysteresis)
                reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
        // check timing of a falling edge in reader signal
        if (pre_after_hysteresis && ~after_hysteresis)
                reader_falling_edge_time[3:0] <= negedge_cnt[3:0];

-       else
-               reader_falling_edge_time[3:0] <= 4'd8;

 
 
 
 
 
 


@@ -333,7 +331,7 @@ begin
         after_hysteresis_prev3 <= after_hysteresis;
                bit3 <= curbit;
        end
         after_hysteresis_prev3 <= after_hysteresis;
                bit3 <= curbit;
        end

-    if(negedge_cnt == 7'd47)
+    if(negedge_cnt == 7'd49)

        begin
         after_hysteresis_prev4 <= after_hysteresis;
                bit4 <= curbit;
        begin
         after_hysteresis_prev4 <= after_hysteresis;
                bit4 <= curbit;