syntax suger

diff --git a/armsrc/mifarecmd.c b/armsrc/mifarecmd.c
index c18aba08d3a61d569f97939c311101990b920036..70f3d4b18a12f4d4c5ad1000d4680aafd9ad9942 100644 (file)
--- a/armsrc/mifarecmd.c
+++ b/armsrc/mifarecmd.c
@@ -4,7 +4,7 @@
 // Hagen Fritsch - June 2010\r
 // Midnitesnake - Dec 2013\r
 // Andy Davies  - Apr 2014\r
-// Iceman - May 2014\r
+// Iceman - May 2014,2015,2016\r
 //\r
 // This code is licensed to you under the terms of the GNU GPL, version 2 or,\r
 // at your option, any later version. See the LICENSE.txt file for the text of\r
@@ -235,18 +235,17 @@ void MifareReadSector(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain)
                if (MF_DBGLEVEL >= 1)   Dbprintf("Halt error");\r
        }\r
 \r
-       //  ----------------------------- crypto1 destroy\r
-       crypto1_destroy(pcs);\r
-       \r
        if (MF_DBGLEVEL >= 2) DbpString("READ SECTOR FINISHED");\r
 \r
+       crypto1_destroy(pcs);\r
+\r
        LED_B_ON();\r
        cmd_send(CMD_ACK,isOK,0,0,dataoutbuf,16*NumBlocksPerSector(sectorNo));\r
        LED_B_OFF();\r
 \r
-       // Thats it...\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
        LEDsoff();\r
+       set_tracing(FALSE);\r
 }\r
 \r
 // arg0 = blockNo (start)\r
@@ -345,6 +344,7 @@ void MifareUReadCard(uint8_t arg0, uint16_t arg1, uint8_t arg2, uint8_t *datain)
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
        LEDsoff();\r
        BigBuf_free();\r
+       set_tracing(FALSE);\r
 }\r
 \r
 //-----------------------------------------------------------------------------\r
@@ -413,10 +413,9 @@ void MifareWriteBlock(uint8_t arg0, uint8_t arg1, uint8_t arg2, uint8_t *datain)
        cmd_send(CMD_ACK,isOK,0,0,0,0);\r
        LED_B_OFF();\r
 \r
-\r
-       // Thats it...\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
        LEDsoff();\r
+       set_tracing(FALSE);\r
 }\r
 \r
 /* // Command not needed but left for future testing \r
@@ -527,6 +526,7 @@ void MifareUWriteBlock(uint8_t arg0, uint8_t arg1, uint8_t *datain)
        cmd_send(CMD_ACK,1,0,0,0,0);\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
        LEDsoff();\r
+       set_tracing(FALSE);\r
 }\r
 \r
 void MifareUSetPwd(uint8_t arg0, uint8_t *datain){\r
@@ -597,6 +597,7 @@ void MifareUSetPwd(uint8_t arg0, uint8_t *datain){
        cmd_send(CMD_ACK,1,0,0,0,0);\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
        LEDsoff();\r
+       set_tracing(FALSE);\r
 }\r
 \r
 // Return 1 if the nonce is invalid else return 0\r
@@ -735,6 +736,7 @@ void MifareAcquireEncryptedNonces(uint32_t arg0, uint32_t arg1, uint32_t flags,
        if (field_off) {\r
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
                LEDsoff();\r
+               set_tracing(FALSE);\r
        }\r
 }\r
 \r
@@ -940,7 +942,6 @@ void MifareNested(uint32_t arg0, uint32_t arg1, uint32_t calibrate, uint8_t *dat
 \r
        LED_C_OFF();\r
        \r
-       //  ----------------------------- crypto1 destroy\r
        crypto1_destroy(pcs);\r
        \r
        byte_t buf[4 + 4 * 4] = {0};\r
@@ -1400,16 +1401,10 @@ void OnErrorMagic(uint8_t reason){
        cmd_send(CMD_ACK,0,reason,0,0,0);\r
        OnSuccessMagic();\r
 }\r
-\r
-void MifareCollectNonces(uint32_t arg0, uint32_t arg1){\r
-}\r
-\r
 //\r
 // DESFIRE\r
 //\r
-\r
 void Mifare_DES_Auth1(uint8_t arg0, uint8_t *datain){\r
-\r
        byte_t dataout[12] = {0x00};\r
        uint8_t uid[10] = {0x00};\r
        uint32_t cuid = 0;\r
@@ -1432,7 +1427,7 @@ void Mifare_DES_Auth1(uint8_t arg0, uint8_t *datain){
        }\r
 \r
        if (MF_DBGLEVEL >= MF_DBG_EXTENDED) DbpString("AUTH 1 FINISHED");\r
-    cmd_send(CMD_ACK,1,cuid,0,dataout, sizeof(dataout));\r
+    cmd_send(CMD_ACK, 1, cuid, 0, dataout, sizeof(dataout));\r
 }\r
 \r
 void Mifare_DES_Auth2(uint32_t arg0, uint8_t *datain){\r
@@ -1457,4 +1452,5 @@ void Mifare_DES_Auth2(uint32_t arg0, uint8_t *datain){
        cmd_send(CMD_ACK, isOK, 0, 0, dataout, sizeof(dataout));\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
        LEDsoff();\r
+       set_tracing(FALSE);\r
 }
\ No newline at end of file

diff --git a/armsrc/mifaresniff.c b/armsrc/mifaresniff.c
index fe57f42969ca3be8fa50d1fe9877077c8506e170..53970e4451cff6fdcf4c53b1194f63a3028ab411 100644 (file)
--- a/armsrc/mifaresniff.c
+++ b/armsrc/mifaresniff.c
@@ -25,7 +25,6 @@ bool MfSniffInit(void){
        memset(sniffATQA, 0x00, 2);\r
        sniffSAK = 0;\r
        sniffUIDType = SNF_UID_4;\r
-\r
        return FALSE;\r
 }\r
 \r
@@ -33,7 +32,6 @@ bool MfSniffEnd(void){
        LED_B_ON();\r
        cmd_send(CMD_ACK,0,0,0,0,0);\r
        LED_B_OFF();\r
-\r
        return FALSE;\r
 }\r
 \r

diff --git a/armsrc/util.c b/armsrc/util.c
index 640809e068bd4719826fe2fc134a602d70f184be..120e7b44cb19de4f94ec23d64244fc35ddf547cc 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -14,8 +14,6 @@
 #include "apps.h"
 #include "BigBuf.h"
 
-
-
 void print_result(char *name, uint8_t *buf, size_t len) {
        uint8_t *p = buf;
 
@@ -400,17 +398,17 @@ void StartCountSspClk()
        AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP;                  // just count
-       
+
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
        AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
 
-       //
-       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
-       //
+       // synchronize the counter with the ssp_frame signal. 
+       // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
+
        // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
        AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
@@ -418,8 +416,9 @@ void StartCountSspClk()
        // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
        // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
        // (just started with the transfer of the 4th Bit).
-       // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
-       // we can use the counter.
+
+       // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
+       // Therefore need to wait quite some time before we can use the counter.
        while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
 }
 

diff --git a/armsrc/util.h b/armsrc/util.h
index bf5d0cc81fc01477ea2526379948a71b5ce470dd..0fb445d6885c1ac760973e38ce8ea336a68a6d05 100644 (file)
--- a/armsrc/util.h
+++ b/armsrc/util.h
@@ -49,7 +49,7 @@ uint32_t RAMFUNC GetTickCount();
 
 void StartCountUS();
 uint32_t RAMFUNC GetCountUS();
-uint32_t RAMFUNC GetDeltaCountUS();
+//uint32_t RAMFUNC GetDeltaCountUS();
 
 void StartCountSspClk();
 uint32_t RAMFUNC GetCountSspClk();