// Options for the HF reader, correlating against rx from tag
#define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0)
#define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1)
-#define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ (1<<2)
// Options for the HF simulated tag, how to modulate
#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
// every other is Q. We just want power, so abs(I) + abs(Q) is
// close to what we want.
if(getNext) {
- int8_t r = ABS(b) + ABS(prev);
+ uint8_t r = ABS(b) + ABS(prev);
dest[c++] = (uint8_t)r;
maxPos = i;
}
}
- // DbpString("SOF at %d, correlation %d", maxPos,max/(arraylen(FrameSOF)/skip));
+ // Dbprintf("SOF at %d, correlation %d", maxPos,max/(arraylen(FrameSOF)/skip));
int k = 0; // this will be our return value
corr1 *= 4;
if(corrEOF > corr1 && corrEOF > corr0) {
- // DbpString("EOF at %d", i);
+ // Dbprintf("EOF at %d", i);
break;
} else if(corr1 > corr0) {
i += arraylen(Logic1)/skip;
// every other is Q. We just want power, so abs(I) + abs(Q) is
// close to what we want.
if(getNext) {
- int8_t r = ABS(b) + ABS(prev);
+ uint8_t r = ABS(b) + ABS(prev);
dest[c++] = (uint8_t)r;
// every other is Q. We just want power, so abs(I) + abs(Q) is
// close to what we want.
if(getNext) {
- int8_t r = ABS(b) + ABS(prev);
+ uint8_t r = ABS(b) + ABS(prev);
dest[c++] = (uint8_t)r;
// every other is Q. We just want power, so abs(I) + abs(Q) is
// close to what we want.
if(getNext) {
- int8_t r = ABS(b) + ABS(prev);
+ uint8_t r = ABS(b) + ABS(prev);
dest[c++] = (uint8_t)r;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
-wire adc_clk = ck_1356megb;
-
-reg fc_div_2;
+// Clock divider
+reg [0:0] fc_divider;
always @(negedge ck_1356megb)
- fc_div_2 <= fc_div_2 + 1;
+ fc_divider <= fc_divider + 1;
+wire fc_div2 = fc_divider[0];
+
+reg adc_clk;
+always @(ck_1356megb)
+ if (xcorr_is_848)
+ adc_clk <= ck_1356megb;
+ else
+ adc_clk <= fc_div2;
// When we're a reader, we just need to do the BPSK demod; but when we're an
// eavesdropper, we also need to pick out the commands sent by the reader,
always @(negedge adc_clk)
begin
- if (xcorr_is_848 | fc_div_2)
corr_i_cnt <= corr_i_cnt + 1;
end
begin
ssp_clk <= 1'b1;
// Don't shift if we just loaded new data, obviously.
- if(corr_i_cnt != 7'd0)
+ if(corr_i_cnt != 6'd0)
begin
corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
corr_q_out[7:1] <= corr_q_out[6:0];