Add HF simulator modulation mode for 212kHz subcarrier

diff --git a/armsrc/apps.h b/armsrc/apps.h
index bf45407f0cb62b86e915f6433bef0bcb200a5fd2..040737e7d5653c5448b311209f28a9b381870ba6 100644 (file)
--- a/armsrc/apps.h
+++ b/armsrc/apps.h
@@ -56,6 +56,7 @@ void SetAdcMuxFor(DWORD whichGpio);
 // Options for the HF simulated tag, how to modulate\r
 #define FPGA_HF_SIMULATOR_NO_MODULATION                                (0<<0)\r
 #define FPGA_HF_SIMULATOR_MODULATE_BPSK                                (1<<0)\r
 // Options for the HF simulated tag, how to modulate\r
 #define FPGA_HF_SIMULATOR_NO_MODULATION                                (0<<0)\r
 #define FPGA_HF_SIMULATOR_MODULATE_BPSK                                (1<<0)\r

+#define FPGA_HF_SIMULATOR_MODULATE_212K                                (2<<0)\r

 // Options for ISO14443A\r
 #define FPGA_HF_ISO14443A_SNIFFER                                      (0<<0)\r
 #define FPGA_HF_ISO14443A_TAGSIM_LISTEN                                (1<<0)\r
 // Options for ISO14443A\r
 #define FPGA_HF_ISO14443A_SNIFFER                                      (0<<0)\r
 #define FPGA_HF_ISO14443A_TAGSIM_LISTEN                                (1<<0)\r

diff --git a/fpga/fpga.bit b/fpga/fpga.bit
index 503f041fb85c92101a5a0ae945b9d228b73ee4d0..a9b03e1382af8f88e405ff215ec90a2a9e9037f1 100644 (file)
Binary files a/fpga/fpga.bit and b/fpga/fpga.bit differ

diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v
index d0a711764abea2a729c3b2fb40d3bd3586fdff1d..05662e53aa3d830ff2e74a75dd36321e95096317 100644 (file)
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -51,7 +51,8 @@ begin
 end\r
 \r
 // Divide 13.56 MHz by 32 to produce the SSP_CLK\r
 end\r
 \r
 // Divide 13.56 MHz by 32 to produce the SSP_CLK\r

-reg [4:0] ssp_clk_divider;\r
+// The register is bigger to allow higher division factors of up to /128\r
+reg [6:0] ssp_clk_divider;\r

 always @(posedge adc_clk)\r
     ssp_clk_divider <= (ssp_clk_divider + 1);\r
 assign ssp_clk = ssp_clk_divider[4];\r
 always @(posedge adc_clk)\r
     ssp_clk_divider <= (ssp_clk_divider + 1);\r
 assign ssp_clk = ssp_clk_divider[4];\r


@@ -87,6 +88,8 @@ always @(mod_type or ssp_clk or ssp_dout)
         modulating_carrier <= 1'b0;                          // no modulation\r
     else if(mod_type == 3'b001)\r
         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK\r
         modulating_carrier <= 1'b0;                          // no modulation\r
     else if(mod_type == 3'b001)\r
         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK\r

+    else if(mod_type == 3'b010)\r
+        modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off\r

     else\r
         modulating_carrier <= 1'b0;                           // yet unused\r
 \r
     else\r
         modulating_carrier <= 1'b0;                           // yet unused\r
 \r