Added bus blaster (http://dangerousprototypes.com/docs/Bus_Blaster) configuration...

diff --git a/tools/at91sam7s512-busblaster.cfg b/tools/at91sam7s512-busblaster.cfg
new file mode 100644 (file)
index 0000000..6555936
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+++ b/tools/at91sam7s512-busblaster.cfg
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+## General OpenOCD configuration
+# Ports
+telnet_port 4444
+gdb_port 3333
+
+## Interface configuration section
+# Interface
+
+# you can use
+#source [find interface/ftdi/dp_busblaster.cfg]
+# or
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0c08 0x0f1b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
+
+adapter_khz 1000
+
+## Chipset configuration section
+# use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+jtag newtap sam7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
+
+target create sam7x.cpu arm7tdmi -endian little -chain-position sam7x.cpu
+
+sam7x.cpu configure -event reset-init {
+    soft_reset_halt
+    mww 0xfffffd00 0xa5000004   # RSTC_CR: Reset peripherals
+    mww 0xfffffd44 0x00008000   # WDT_MR: disable watchdog
+    mww 0xfffffd08 0xa5000001   # RSTC_MR enable user reset
+    mww 0xfffffc20 0x00005001   # CKGR_MOR : enable the main oscillator
+    sleep 10
+    mww 0xfffffc2c 0x000b1c02   # CKGR_PLLR: 16MHz * 12/2 = 96MHz
+    sleep 10
+    mww 0xfffffc30 0x00000007   # PMC_MCKR : MCK = PLL / 2 = 48 MHz
+    sleep 10
+    mww 0xffffff60 0x00480100   # MC_FMR: flash mode (FWS=1,FMCN=72)
+    sleep 100
+
+}
+
+# GDB can also flash my flash!
+gdb_memory_map enable
+gdb_breakpoint_override hard
+#armv4_5 core_state arm
+
+sam7x.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
+flash bank sam7x512.flash.0 at91sam7 0 0 0 0 sam7x.cpu 0 0 0 0 0 0 0 18432
+flash bank sam7x512.flash.1 at91sam7 0 0 0 0 sam7x.cpu 1 0 0 0 0 0 0 18432