[raggedstone] / dhwk / source / DATA_MUX.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: DATA_MUX.VHD\r
\r
library ieee ;\r
use ieee.std_logic_1164.all ;\r
 \r
entity DATA_MUX is\r
	port\r
	(\r
	READ_SEL		:in		std_logic_vector( 1 downto 0);\r
	ADDR_REG		:in		std_logic_vector(31 downto 0);\r
	CBE_REGn		:in		std_logic_vector( 3 downto 0);\r
	MUX_IN_XX0	:in		std_logic_vector( 7 downto 0);\r
	MUX_IN_XX1	:in		std_logic_vector( 7 downto 0);\r
	MUX_IN_XX2	:in		std_logic_vector( 7 downto 0);\r
	MUX_IN_XX3	:in		std_logic_vector( 7 downto 0);\r
	MUX_IN_XX4	:in		std_logic_vector( 7 downto 0);\r
	MUX_IN_XX5	:in		std_logic_vector( 7 downto 0);\r
	MUX_IN_XX6	:in		std_logic_vector( 7 downto 0);\r
	MUX_IN_XX7	:in		std_logic_vector( 7 downto 0);\r
	MUX_OUT			:out	std_logic_vector(31 downto 0);\r
	READ_XX1_0	:out	std_logic;	\r
	READ_XX3_2	:out	std_logic;\r
	READ_XX5_4	:out	std_logic;\r
	READ_XX7_6	:out	std_logic\r
--READ_FIFO		:out	std_logic\r
	);\r
end entity DATA_MUX ;\r
\r
architecture DATA_MUX_DESIGN of DATA_MUX is\r
\r
	signal	MUX	:std_logic_vector(31 downto 0);\r
	signal	SEL	:std_logic_vector( 7 downto 0);\r
\r
	signal	SIG_READ_XX1_0	:std_logic;\r
	signal	SIG_READ_XX3_2	:std_logic;\r
	signal	SIG_READ_XX5_4	:std_logic;\r
	signal	SIG_READ_XX7_6	:std_logic;\r
\r
begin\r
\r
	SEL	<= ADDR_REG(3 downto 2) & CBE_REGn	&	READ_SEL ;	\r
																																		\r
	SIG_READ_XX1_0	<=	'1' when	SEL	=	"00110011"	else	'0';\r
	SIG_READ_XX3_2	<=	'1' when	SEL	=	"00001111"	else	'0';\r
	SIG_READ_XX5_4	<=	'1' when	SEL	=	"01110011"	else	'0';\r
	SIG_READ_XX7_6	<=	'1' when	SEL	=	"01001111"	else	'0';\r
\r
\r
									\r
	MUX	<=	(X"00" 			& X"00" 			& MUX_IN_XX1	&	MUX_IN_XX0)	when	SIG_READ_XX1_0	=	'1' else \r
					(MUX_IN_XX3	&	MUX_IN_XX2  &	X"00"				& X"00"			)	when	SIG_READ_XX3_2	=	'1' else				\r
					(X"00" 			& X"00" 			& MUX_IN_XX5	&	MUX_IN_XX4)	when	SIG_READ_XX5_4	=	'1' else \r
					(MUX_IN_XX7	&	MUX_IN_XX6  &	X"00"				& X"00"			)	when	SIG_READ_XX7_6	=	'1' else  	\r
					(others => '0');																																				\r
\r
\r
--	MUX	<=	(X"01" 			& X"23" 			& MUX_IN_XX1	&	MUX_IN_XX0)	when	SIG_READ_XX1_0	=	'1' else \r
--					(MUX_IN_XX3	&	MUX_IN_XX2  &	X"45"				& X"67"			)	when	SIG_READ_XX3_2	=	'1' else				\r
--					(X"89" 			& X"AB" 			& MUX_IN_XX5	&	MUX_IN_XX4)	when	SIG_READ_XX5_4	=	'1' else \r
--					(MUX_IN_XX7	&	MUX_IN_XX6  &	X"CD"				& X"EF"			)	when	SIG_READ_XX7_6	=	'1' else  	\r
--					(others => '0');																																				\r
\r
\r
	MUX_OUT <= MUX ;\r
\r
\r
	READ_XX1_0	<=	SIG_READ_XX1_0;			\r
	READ_XX3_2	<=	SIG_READ_XX3_2;\r
	READ_XX5_4	<=	SIG_READ_XX5_4;\r
	READ_XX7_6	<=	SIG_READ_XX7_6;\r
\r
--READ_FIFO		<=	SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test\r
\r
end architecture DATA_MUX_DESIGN ;\r
Commit	Line	Data
377c0242	1	-- J.STELZNER\r
	2	-- INFORMATIK-3 LABOR\r
	3	-- 23.08.2006\r
	4	-- File: DATA_MUX.VHD\r
	5	\r
	6	library ieee ;\r
	7	use ieee.std_logic_1164.all ;\r
	8	\r
	9	entity DATA_MUX is\r
	10	port\r
	11	(\r
	12	READ_SEL :in std_logic_vector( 1 downto 0);\r
	13	ADDR_REG :in std_logic_vector(31 downto 0);\r
	14	CBE_REGn :in std_logic_vector( 3 downto 0);\r
	15	MUX_IN_XX0 :in std_logic_vector( 7 downto 0);\r
	16	MUX_IN_XX1 :in std_logic_vector( 7 downto 0);\r
	17	MUX_IN_XX2 :in std_logic_vector( 7 downto 0);\r
	18	MUX_IN_XX3 :in std_logic_vector( 7 downto 0);\r
	19	MUX_IN_XX4 :in std_logic_vector( 7 downto 0);\r
	20	MUX_IN_XX5 :in std_logic_vector( 7 downto 0);\r
	21	MUX_IN_XX6 :in std_logic_vector( 7 downto 0);\r
	22	MUX_IN_XX7 :in std_logic_vector( 7 downto 0);\r
	23	MUX_OUT :out std_logic_vector(31 downto 0);\r
	24	READ_XX1_0 :out std_logic; \r
	25	READ_XX3_2 :out std_logic;\r
	26	READ_XX5_4 :out std_logic;\r
	27	READ_XX7_6 :out std_logic\r
	28	--READ_FIFO :out std_logic\r
	29	);\r
	30	end entity DATA_MUX ;\r
	31	\r
	32	architecture DATA_MUX_DESIGN of DATA_MUX is\r
	33	\r
	34	signal MUX :std_logic_vector(31 downto 0);\r
	35	signal SEL :std_logic_vector( 7 downto 0);\r
	36	\r
	37	signal SIG_READ_XX1_0 :std_logic;\r
	38	signal SIG_READ_XX3_2 :std_logic;\r
	39	signal SIG_READ_XX5_4 :std_logic;\r
	40	signal SIG_READ_XX7_6 :std_logic;\r
	41	\r
	42	begin\r
	43	\r
	44	SEL <= ADDR_REG(3 downto 2) & CBE_REGn & READ_SEL ; \r
	45	\r
	46	SIG_READ_XX1_0 <= '1' when SEL = "00110011" else '0';\r
	47	SIG_READ_XX3_2 <= '1' when SEL = "00001111" else '0';\r
	48	SIG_READ_XX5_4 <= '1' when SEL = "01110011" else '0';\r
	49	SIG_READ_XX7_6 <= '1' when SEL = "01001111" else '0';\r
	50	\r
	51	\r
	52	\r
	53	MUX <= (X"00" & X"00" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else \r
	54	(MUX_IN_XX3 & MUX_IN_XX2 & X"00" & X"00" ) when SIG_READ_XX3_2 = '1' else \r
	55	(X"00" & X"00" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else \r
	56	(MUX_IN_XX7 & MUX_IN_XX6 & X"00" & X"00" ) when SIG_READ_XX7_6 = '1' else \r
	57	(others => '0'); \r
	58	\r
	59	\r
	60	-- MUX <= (X"01" & X"23" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else \r
	61	-- (MUX_IN_XX3 & MUX_IN_XX2 & X"45" & X"67" ) when SIG_READ_XX3_2 = '1' else \r
	62	-- (X"89" & X"AB" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else \r
	63	-- (MUX_IN_XX7 & MUX_IN_XX6 & X"CD" & X"EF" ) when SIG_READ_XX7_6 = '1' else \r
	64	-- (others => '0'); \r
65	\r
66	\r
67	MUX_OUT <= MUX ;\r
68	\r
69	\r
70	READ_XX1_0 <= SIG_READ_XX1_0; \r
71	READ_XX3_2 <= SIG_READ_XX3_2;\r
72	READ_XX5_4 <= SIG_READ_XX5_4;\r
73	READ_XX7_6 <= SIG_READ_XX7_6;\r
74	\r
75	--READ_FIFO <= SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test\r
76	\r
77	end architecture DATA_MUX_DESIGN ;\r