rename fifo to dhwk_fifo
authormichael <michael>
Sat, 10 Mar 2007 21:35:08 +0000 (21:35 +0000)
committermichael <michael>
Sat, 10 Mar 2007 21:35:08 +0000 (21:35 +0000)
dhwk/Makefile
dhwk/fifo.xco
dhwk/source/top.vhd

index 875f05af0c6cb860fc3f6035e730692cf3790016..dfb7422d2bb708052afcc1ff7605626d15bae8a0 100644 (file)
@@ -11,7 +11,8 @@ icon.edn: icon.arg
 ila.edn: ila.arg
        $(CHIPSCOPE)/bin/lin/generate.sh ila -f=$<
 
-fifo_generator_v3_2.ngc: fifo.xco
+dhwk_fifo.ngc: fifo.xco
        coregen -b $<
+       -rmdir -p tmp
 
 include ../common/Makefile.common
index 22c49f370cec22aa770ca6b8772bd08b9eabbc01..9b54e6720af7a31c55d05618a9cc29e86f0e3fc3 100644 (file)
@@ -23,7 +23,7 @@ SELECT Fifo_Generator family Xilinx,_Inc. 3.2
 # BEGIN Parameters
 CSET almost_empty_flag=true
 CSET almost_full_flag=true
-CSET component_name=fifo_generator_v3_2
+CSET component_name=dhwk_fifo
 CSET data_count=false
 CSET data_count_width=12
 CSET dout_reset_value=0
index 84f04dd95724c2b9c0280da536dbef1236ba1228..bf927d84931e93850197a826d2207a781a7f31c1 100644 (file)
@@ -209,7 +209,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );\r
    end component;\r
 \r
-component fifo_generator_v3_2\r
+component dhwk_fifo\r
         port (\r
         clk: IN std_logic;\r
         din: IN std_logic_VECTOR(7 downto 0);\r
@@ -364,7 +364,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                  WRITE_XX7_6=>WRITE_XX7_6 );\r
 \r
-receive_fifo : fifo_generator_v3_2\r
+receive_fifo : dhwk_fifo\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => R_FIFO_D_IN,\r
@@ -376,7 +376,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,\r
                         prog_full => R_HFn);\r
 \r
-send_fifo : fifo_generator_v3_2\r
+send_fifo : dhwk_fifo\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => S_FIFO_D_IN,\r
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