Update to EDK 9.2

[raggedstone] / dhwk / fifo.xco

# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s1500
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg456
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 3.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=true
CSET almost_full_flag=true
CSET component_name=dhwk_fifo
CSET data_count=false
CSET data_count_width=12
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_threshold_assert_value=2048
CSET full_threshold_negate_value=2047
CSET input_data_width=8
CSET input_depth=4096
CSET output_data_width=8
CSET output_depth=4096
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=100
CSET read_data_count=false
CSET read_data_count_width=12
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=100
CSET write_data_count=false
CSET write_data_count_width=12
# END Parameters
GENERATE