[raggedstone] / dhwk / source / SER_PAR_CON.vhd

-- $Id: SER_PAR_CON.vhd,v 1.2 2007-03-11 08:04:56 sithglan Exp $

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity SER_PAR_CON is
	port
	(
	PCI_CLOCK			:in	std_logic; 
	RESET				:in	std_logic; 
	SPC_ENABLE			:in	std_logic; -- Driver Enable Sender/Receiver
	SYNC_R_FIFO_FFn                	:in	std_logic; -- FIFO Full Flag (low active)
 	SERIAL_IN			:in	std_logic; -- Serial Input
	R_FIFO_WRITEn		        :out	std_logic; -- FIFO Write (low active)
	SPC_RDY_OUT			:out	std_logic; -- Ready to Receive Data
	PAR_OUT				:out	std_logic_vector(7 downto 0)
	);
end entity SER_PAR_CON ;


architecture SER_PAR_CON_DESIGN of SER_PAR_CON is

-- constant STATE_RECV            :std_logic_vector(3 downto 0) := "0001";
constant STATE_RECV_START_BIT  :std_logic_vector(3 downto 0) := "0010";
constant STATE_RECV_BIT_0      :std_logic_vector(3 downto 0) := "0011";
constant STATE_RECV_BIT_1      :std_logic_vector(3 downto 0) := "0100";
constant STATE_RECV_BIT_2      :std_logic_vector(3 downto 0) := "0101";
constant STATE_RECV_BIT_3      :std_logic_vector(3 downto 0) := "0110";
constant STATE_RECV_BIT_4      :std_logic_vector(3 downto 0) := "0111";
constant STATE_RECV_BIT_5      :std_logic_vector(3 downto 0) := "1000";
constant STATE_RECV_BIT_6      :std_logic_vector(3 downto 0) := "1001";
constant STATE_RECV_BIT_7      :std_logic_vector(3 downto 0) := "1010";
constant STATE_RECV_FIFOFULL   :std_logic_vector(3 downto 0) := "1011";

signal COUNT     :std_logic_vector (3 downto 0);
signal STATE     :std_logic_vector (3 downto 0);
signal STARTBIT  :std_logic_vector (3 downto 0);


attribute syn_state_machine:boolean;
attribute syn_state_machine of STATE: signal is false;
attribute syn_state_machine of COUNT: signal is false;

begin

process(PCI_CLOCK)
begin
        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
				    		if ("0000" < COUNT) then
                				COUNT <= COUNT - 1;
        				end if;

-- war nicht das Problem des Datenverlusts
--        if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
--            R_FIFO_WRITEn <= '1';
---      end if;

                if (RESET = '1') then
                        STATE <= STATE_RECV_START_BIT;
                        COUNT <= "0000";
                        R_FIFO_WRITEn <= '1';

                elsif (SPC_ENABLE = '1') then
                       
											 if (STATE = STATE_RECV_START_BIT) then
                              R_FIFO_WRITEn <= '1';
											        if (STARTBIT = "0011") then
																COUNT <= "0011";
                          	    STATE <= STATE_RECV_BIT_0;
                              end if;

                       elsif (STATE = STATE_RECV_FIFOFULL) then
                              if (SYNC_R_FIFO_FFn = '1') then
                                      R_FIFO_WRITEn <= '0';
                                      STATE <= STATE_RECV_START_BIT;
                              end if;

                       elsif (COUNT = "0000") then
                        COUNT <= "0011";
                        case STATE is
																
                                when STATE_RECV_BIT_0 =>
                                        PAR_OUT(0) <= STARTBIT(0);
                                        STATE <= STATE_RECV_BIT_1;

                                when STATE_RECV_BIT_1 =>
                                        PAR_OUT(1) <= STARTBIT(0);
                                        STATE <= STATE_RECV_BIT_2;
                                        
                                when STATE_RECV_BIT_2 =>
                                        PAR_OUT(2) <= STARTBIT(0);
                                        STATE <= STATE_RECV_BIT_3;
                                        
                                when STATE_RECV_BIT_3 =>
                                        PAR_OUT(3) <= STARTBIT(0);
                                        STATE <= STATE_RECV_BIT_4;
                                        
                                when STATE_RECV_BIT_4 =>
                                        PAR_OUT(4) <= STARTBIT(0);
                                        STATE <= STATE_RECV_BIT_5;
                                        
                                when STATE_RECV_BIT_5 =>
                                        PAR_OUT(5) <= STARTBIT(0);
                                        STATE <= STATE_RECV_BIT_6;
                                        
                                when STATE_RECV_BIT_6 =>
                                        PAR_OUT(6) <= STARTBIT(0);
                                        STATE <= STATE_RECV_BIT_7;
                                        
                                when STATE_RECV_BIT_7 =>
                                        PAR_OUT(7) <= STARTBIT(0);

                                        if (SYNC_R_FIFO_FFn = '1') then
                                             STATE <= STATE_RECV_START_BIT;
                                             R_FIFO_WRITEn <= '0';
                                        else 
                                             STATE <= STATE_RECV_FIFOFULL;
                                        end if;

																when others =>
																				STATE <= STATE_RECV_START_BIT;

                        end case;
                     end if; -- COUNT
                end if; -- RESET ... / SPC_ENABLE ...
        end if; -- PCI_CLOCK ...
end process;

process(PCI_CLOCK)
begin
		if (PCI_CLOCK'event and PCI_CLOCK = '1') then
      SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
		end if;
end process;


process(PCI_CLOCK)
begin
        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
					if (RESET = '1') then
 						STARTBIT <= "0000";
					else
					STARTBIT(0) <= SERIAL_IN;
					STARTBIT(1) <= STARTBIT(0);
					STARTBIT(2) <= STARTBIT(1);
					STARTBIT(3) <= STARTBIT(2);
					end if;				  
  			end if;
end process;


end architecture SER_PAR_CON_DESIGN;
Commit	Line	Data
696ded12	1	-- $Id: SER_PAR_CON.vhd,v 1.2 2007-03-11 08:04:56 sithglan Exp $
	2
	3	library ieee;
	4	use ieee.std_logic_1164.all;
	5	use ieee.std_logic_unsigned.all;
	6
	7	entity SER_PAR_CON is
	8	port
	9	(
	10	PCI_CLOCK :in std_logic;
	11	RESET :in std_logic;
	12	SPC_ENABLE :in std_logic; -- Driver Enable Sender/Receiver
	13	SYNC_R_FIFO_FFn :in std_logic; -- FIFO Full Flag (low active)
	14	SERIAL_IN :in std_logic; -- Serial Input
	15	R_FIFO_WRITEn :out std_logic; -- FIFO Write (low active)
	16	SPC_RDY_OUT :out std_logic; -- Ready to Receive Data
	17	PAR_OUT :out std_logic_vector(7 downto 0)
	18	);
	19	end entity SER_PAR_CON ;
	20
	21
	22	architecture SER_PAR_CON_DESIGN of SER_PAR_CON is
	23
	24	-- constant STATE_RECV :std_logic_vector(3 downto 0) := "0001";
	25	constant STATE_RECV_START_BIT :std_logic_vector(3 downto 0) := "0010";
	26	constant STATE_RECV_BIT_0 :std_logic_vector(3 downto 0) := "0011";
	27	constant STATE_RECV_BIT_1 :std_logic_vector(3 downto 0) := "0100";
	28	constant STATE_RECV_BIT_2 :std_logic_vector(3 downto 0) := "0101";
	29	constant STATE_RECV_BIT_3 :std_logic_vector(3 downto 0) := "0110";
	30	constant STATE_RECV_BIT_4 :std_logic_vector(3 downto 0) := "0111";
	31	constant STATE_RECV_BIT_5 :std_logic_vector(3 downto 0) := "1000";
	32	constant STATE_RECV_BIT_6 :std_logic_vector(3 downto 0) := "1001";
	33	constant STATE_RECV_BIT_7 :std_logic_vector(3 downto 0) := "1010";
	34	constant STATE_RECV_FIFOFULL :std_logic_vector(3 downto 0) := "1011";
	35
	36	signal COUNT :std_logic_vector (3 downto 0);
	37	signal STATE :std_logic_vector (3 downto 0);
	38	signal STARTBIT :std_logic_vector (3 downto 0);
	39
	40
	41	attribute syn_state_machine:boolean;
	42	attribute syn_state_machine of STATE: signal is false;
	43	attribute syn_state_machine of COUNT: signal is false;
	44
	45	begin
	46
	47	process(PCI_CLOCK)
	48	begin
	49	if (PCI_CLOCK'event and PCI_CLOCK = '1') then
	50	if ("0000" < COUNT) then
	51	COUNT <= COUNT - 1;
	52	end if;
	53
	54	-- war nicht das Problem des Datenverlusts
	55	-- if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
	56	-- R_FIFO_WRITEn <= '1';
	57	--- end if;
	58
	59	if (RESET = '1') then
	60	STATE <= STATE_RECV_START_BIT;
	61	COUNT <= "0000";
	62	R_FIFO_WRITEn <= '1';
	63
	64	elsif (SPC_ENABLE = '1') then
65
66	if (STATE = STATE_RECV_START_BIT) then
67	R_FIFO_WRITEn <= '1';
68	if (STARTBIT = "0011") then
69	COUNT <= "0011";
70	STATE <= STATE_RECV_BIT_0;
71	end if;
72
73	elsif (STATE = STATE_RECV_FIFOFULL) then
74	if (SYNC_R_FIFO_FFn = '1') then
75	R_FIFO_WRITEn <= '0';
76	STATE <= STATE_RECV_START_BIT;
77	end if;
78
79	elsif (COUNT = "0000") then
80	COUNT <= "0011";
81	case STATE is
82
83	when STATE_RECV_BIT_0 =>
84	PAR_OUT(0) <= STARTBIT(0);
85	STATE <= STATE_RECV_BIT_1;
86
87	when STATE_RECV_BIT_1 =>
88	PAR_OUT(1) <= STARTBIT(0);
89	STATE <= STATE_RECV_BIT_2;
90
91	when STATE_RECV_BIT_2 =>
92	PAR_OUT(2) <= STARTBIT(0);
93	STATE <= STATE_RECV_BIT_3;
94
95	when STATE_RECV_BIT_3 =>
96	PAR_OUT(3) <= STARTBIT(0);
97	STATE <= STATE_RECV_BIT_4;
98
99	when STATE_RECV_BIT_4 =>
100	PAR_OUT(4) <= STARTBIT(0);
101	STATE <= STATE_RECV_BIT_5;
102
103	when STATE_RECV_BIT_5 =>
104	PAR_OUT(5) <= STARTBIT(0);
105	STATE <= STATE_RECV_BIT_6;
106
107	when STATE_RECV_BIT_6 =>
108	PAR_OUT(6) <= STARTBIT(0);
109	STATE <= STATE_RECV_BIT_7;
110
111	when STATE_RECV_BIT_7 =>
112	PAR_OUT(7) <= STARTBIT(0);
113
114	if (SYNC_R_FIFO_FFn = '1') then
115	STATE <= STATE_RECV_START_BIT;
116	R_FIFO_WRITEn <= '0';
117	else
118	STATE <= STATE_RECV_FIFOFULL;
119	end if;
120
121	when others =>
122	STATE <= STATE_RECV_START_BIT;
123
124	end case;
125	end if; -- COUNT
126	end if; -- RESET ... / SPC_ENABLE ...
127	end if; -- PCI_CLOCK ...
128	end process;
129
130	process(PCI_CLOCK)
131	begin
132	if (PCI_CLOCK'event and PCI_CLOCK = '1') then
133	SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
134	end if;
135	end process;
136
137
138	process(PCI_CLOCK)
139	begin
140	if (PCI_CLOCK'event and PCI_CLOCK = '1') then
141	if (RESET = '1') then
142	STARTBIT <= "0000";
143	else
144	STARTBIT(0) <= SERIAL_IN;
145	STARTBIT(1) <= STARTBIT(0);
146	STARTBIT(2) <= STARTBIT(1);
147	STARTBIT(3) <= STARTBIT(2);
148	end if;
149	end if;
150	end process;
151
152
153
154	end architecture SER_PAR_CON_DESIGN;