dos2unix *.vhd
authorsithglan <sithglan>
Sun, 11 Mar 2007 08:04:56 +0000 (08:04 +0000)
committersithglan <sithglan>
Sun, 11 Mar 2007 08:04:56 +0000 (08:04 +0000)
42 files changed:
dhwk/source/COMM_DEC.vhd
dhwk/source/COMM_FSM.vhd
dhwk/source/CONT_FSM.vhd
dhwk/source/DATA_MUX.vhd
dhwk/source/FLAG_BUS.vhd
dhwk/source/INTERRUPT.vhd
dhwk/source/IO_RW_SEL.vhd
dhwk/source/Io_mux.vhd
dhwk/source/Io_reg.vhd
dhwk/source/MESS_1_TB.vhd
dhwk/source/PAR_SER_CON.vhd
dhwk/source/Parity_4.vhd
dhwk/source/REG.vhd
dhwk/source/SER_PAR_CON.vhd
dhwk/source/Verg_2.vhd
dhwk/source/Verg_4.vhd
dhwk/source/config_00h.vhd
dhwk/source/config_04h.vhd
dhwk/source/config_08h.vhd
dhwk/source/config_10h.vhd
dhwk/source/config_3Ch.vhd
dhwk/source/config_mux_0.vhd
dhwk/source/config_rd_0.vhd
dhwk/source/config_space_header.vhd
dhwk/source/config_wr_0.vhd
dhwk/source/connecting_fsm.vhd
dhwk/source/fifo_control.vhd
dhwk/source/fifo_io_control.vhd
dhwk/source/io_mux_reg.vhd
dhwk/source/parity.vhd
dhwk/source/parity_out.vhd
dhwk/source/pci/address_register.vhd
dhwk/source/pci_interface.vhd
dhwk/source/pci_top.vhd
dhwk/source/reg_io.vhd
dhwk/source/steuerung.vhd
dhwk/source/synplify.vhd
dhwk/source/top.vhd
dhwk/source/user_io.vhd
dhwk/source/ven_rev_id.vhd
dhwk/source/verg_8.vhd
dhwk/source/vergleich.vhd

index d2f423ab23a226fa2dd11f7486528b65ada08243..a82d7a530ac349a99caa23a850481bc78f1a3482 100644 (file)
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: COMM_DEC.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity COMM_DEC is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic; \r
-       PCI_RSTn                :in             std_logic; \r
-       MY_ADDR                 :in             std_logic;\r
-       IDSEL_REG               :in             std_logic;\r
-       FRAME_REGn      :in             std_logic;\r
-       IO_SPACE                :in             std_logic;\r
-       AD_REG                  :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
-       LAR                                     :out    std_logic;--LOAD_ADDR_REG\r
-       IO_READ                 :out    std_logic;\r
-       IO_WRITE                :out    std_logic;\r
-       CONF_READ               :out    std_logic;\r
-       CONF_WRITE      :out    std_logic;\r
-       SERR_CHECK      :out    std_logic\r
-       );\r
-end entity COMM_DEC ;\r
-\r
-architecture COMM_DEC_DESIGN of COMM_DEC is\r
-\r
-\r
---PCI Bus Commands \r
---C/BE[3..0] Command Type\r
---------------------------------------\r
---     0000            Interrupt Acknowledge\r
---     0001            Special Cycle\r
---     0010            I/O Read\r
---     0011            I/O Write\r
---     0100            Reserved\r
---     0101            Reserved\r
---     0110            Memory Read\r
---     0111            Memory Write\r
---\r
---     1000            Reserved\r
---     1001            Reserved\r
---     1010            Configuration Read\r
---     1011            Configuration Write\r
---     1100            Memory Read Multiple \r
---     1101            Dual Address Cycle\r
---     1110            Memory Read Line\r
---     1111            Memory Write and Invalidate\r
-\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
-\r
-       constant        cmd_int_ack                     :std_logic_vector(3 downto 0) := "0000";\r
-       constant        cmd_sp_cyc                      :std_logic_vector(3 downto 0) := "0001";\r
-       constant        cmd_io_read                     :std_logic_vector(3 downto 0) := "0010";\r
-       constant        cmd_io_write            :std_logic_vector(3 downto 0) := "0011";\r
-       constant        cmd_res_4                               :std_logic_vector(3 downto 0) := "0100";\r
-       constant        cmd_res_5                               :std_logic_vector(3 downto 0) := "0101";\r
-       constant        cmd_mem_read            :std_logic_vector(3 downto 0) := "0110";\r
-       constant        cmd_mem_write           :std_logic_vector(3 downto 0) := "0111";\r
-       constant        cmd_res_8                               :std_logic_vector(3 downto 0) := "1000";\r
-       constant        cmd_res_9                               :std_logic_vector(3 downto 0) := "1001";\r
-       constant        cmd_conf_read           :std_logic_vector(3 downto 0) := "1010";\r
-       constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";\r
-       constant        cmd_mem_read_m  :std_logic_vector(3 downto 0) := "1100";\r
-       constant        cmd_du_adr_cyc  :std_logic_vector(3 downto 0) := "1101";\r
-       constant        cmd_mem_read_l  :std_logic_vector(3 downto 0) := "1110";\r
-       constant        cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";\r
-\r
-       signal          START                                           :std_logic; \r
-       signal          FRAME_REG_REGn  :std_logic; \r
-\r
-       signal          SIG_IO_READ                     :std_logic; \r
-       signal          SIG_IO_WRITE            :std_logic; \r
-       signal          SIG_CONF_READ           :std_logic; \r
-       signal          SIG_CONF_WRITE  :std_logic; \r
-\r
-begin\r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    FRAME_REG_REGn  <=      '1';    \r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       FRAME_REG_REGn  <=      FRAME_REGn; \r
-\r
-               end if;\r
-       end process;\r
-\r
-\r
-       START                   <= (not FRAME_REGn) and FRAME_REG_REGn; \r
-\r
-\r
-\r
-       SIG_IO_READ             <= '1'  when    START                   = '1'\r
-                                                                                               and             IO_SPACE        = '1'\r
-                                                                                               and             CBE_REGn        = cmd_io_read   \r
-                                                                                               and             MY_ADDR         = '1'\r
-                                                       else '0'; \r
-\r
-\r
-       SIG_IO_WRITE    <= '1'  when    START                   = '1'\r
-                                                                                               and             IO_SPACE        = '1'\r
-                                                                                               and             CBE_REGn        = cmd_io_write\r
-                                                                                               and             MY_ADDR         = '1'\r
-                                                       else '0'; \r
-\r
-\r
-       SIG_CONF_READ   <= '1'  when    START                                                           = '1'\r
-                                                                                               and             AD_REG(1 downto 0)      = "00"\r
-                                                                                               and             CBE_REGn                                                = cmd_conf_read\r
-                                                                                               and             IDSEL_REG                                               = '1'\r
-                                                                                               \r
-                                               else '0'; \r
-\r
-\r
-       SIG_CONF_WRITE  <= '1'  when    START                                                           = '1'\r
-                                                                                                       and             AD_REG(1 downto 0)      = "00"\r
-                                                                                                       and             CBE_REGn                                                = cmd_conf_write\r
-                                                                                                       and             IDSEL_REG                                               = '1'\r
-                                                               else '0'; \r
-\r
-       LAR                     <=      START;\r
-\r
-       SERR_CHECK      <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE;       \r
-\r
-       IO_READ         <=      SIG_IO_READ;\r
-       IO_WRITE        <=      SIG_IO_WRITE;    \r
-       CONF_READ         <=    SIG_CONF_READ;  \r
-       CONF_WRITE      <=      SIG_CONF_WRITE;\r
-\r
-end architecture COMM_DEC_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: COMM_DEC.VHD
+
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity COMM_DEC is
+       port
+       (
+       PCI_CLOCK               :in             std_logic; 
+       PCI_RSTn                :in             std_logic; 
+       MY_ADDR                 :in             std_logic;
+       IDSEL_REG               :in             std_logic;
+       FRAME_REGn      :in             std_logic;
+       IO_SPACE                :in             std_logic;
+       AD_REG                  :in             std_logic_vector(31 downto 0);
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);
+       LAR                                     :out    std_logic;--LOAD_ADDR_REG
+       IO_READ                 :out    std_logic;
+       IO_WRITE                :out    std_logic;
+       CONF_READ               :out    std_logic;
+       CONF_WRITE      :out    std_logic;
+       SERR_CHECK      :out    std_logic
+       );
+end entity COMM_DEC ;
+
+architecture COMM_DEC_DESIGN of COMM_DEC is
+
+
+--PCI Bus Commands 
+--C/BE[3..0] Command Type
+--------------------------------------
+--     0000            Interrupt Acknowledge
+--     0001            Special Cycle
+--     0010            I/O Read
+--     0011            I/O Write
+--     0100            Reserved
+--     0101            Reserved
+--     0110            Memory Read
+--     0111            Memory Write
+--
+--     1000            Reserved
+--     1001            Reserved
+--     1010            Configuration Read
+--     1011            Configuration Write
+--     1100            Memory Read Multiple 
+--     1101            Dual Address Cycle
+--     1110            Memory Read Line
+--     1111            Memory Write and Invalidate
+
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+
+       constant        cmd_int_ack                     :std_logic_vector(3 downto 0) := "0000";
+       constant        cmd_sp_cyc                      :std_logic_vector(3 downto 0) := "0001";
+       constant        cmd_io_read                     :std_logic_vector(3 downto 0) := "0010";
+       constant        cmd_io_write            :std_logic_vector(3 downto 0) := "0011";
+       constant        cmd_res_4                               :std_logic_vector(3 downto 0) := "0100";
+       constant        cmd_res_5                               :std_logic_vector(3 downto 0) := "0101";
+       constant        cmd_mem_read            :std_logic_vector(3 downto 0) := "0110";
+       constant        cmd_mem_write           :std_logic_vector(3 downto 0) := "0111";
+       constant        cmd_res_8                               :std_logic_vector(3 downto 0) := "1000";
+       constant        cmd_res_9                               :std_logic_vector(3 downto 0) := "1001";
+       constant        cmd_conf_read           :std_logic_vector(3 downto 0) := "1010";
+       constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";
+       constant        cmd_mem_read_m  :std_logic_vector(3 downto 0) := "1100";
+       constant        cmd_du_adr_cyc  :std_logic_vector(3 downto 0) := "1101";
+       constant        cmd_mem_read_l  :std_logic_vector(3 downto 0) := "1110";
+       constant        cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";
+
+       signal          START                                           :std_logic; 
+       signal          FRAME_REG_REGn  :std_logic; 
+
+       signal          SIG_IO_READ                     :std_logic; 
+       signal          SIG_IO_WRITE            :std_logic; 
+       signal          SIG_CONF_READ           :std_logic; 
+       signal          SIG_CONF_WRITE  :std_logic; 
+
+begin
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then    FRAME_REG_REGn  <=      '1';    
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       FRAME_REG_REGn  <=      FRAME_REGn; 
+
+               end if;
+       end process;
+
+
+       START                   <= (not FRAME_REGn) and FRAME_REG_REGn; 
+
+
+
+       SIG_IO_READ             <= '1'  when    START                   = '1'
+                                                                                               and             IO_SPACE        = '1'
+                                                                                               and             CBE_REGn        = cmd_io_read   
+                                                                                               and             MY_ADDR         = '1'
+                                                       else '0'; 
+
+
+       SIG_IO_WRITE    <= '1'  when    START                   = '1'
+                                                                                               and             IO_SPACE        = '1'
+                                                                                               and             CBE_REGn        = cmd_io_write
+                                                                                               and             MY_ADDR         = '1'
+                                                       else '0'; 
+
+
+       SIG_CONF_READ   <= '1'  when    START                                                           = '1'
+                                                                                               and             AD_REG(1 downto 0)      = "00"
+                                                                                               and             CBE_REGn                                                = cmd_conf_read
+                                                                                               and             IDSEL_REG                                               = '1'
+                                                                                               
+                                               else '0'; 
+
+
+       SIG_CONF_WRITE  <= '1'  when    START                                                           = '1'
+                                                                                                       and             AD_REG(1 downto 0)      = "00"
+                                                                                                       and             CBE_REGn                                                = cmd_conf_write
+                                                                                                       and             IDSEL_REG                                               = '1'
+                                                               else '0'; 
+
+       LAR                     <=      START;
+
+       SERR_CHECK      <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE;       
+
+       IO_READ         <=      SIG_IO_READ;
+       IO_WRITE        <=      SIG_IO_WRITE;    
+       CONF_READ         <=    SIG_CONF_READ;  
+       CONF_WRITE      <=      SIG_CONF_WRITE;
+
+end architecture COMM_DEC_DESIGN ;
index 158426ef6133096fbd29e68a03bf8fe06ea6cab2..86eca013823eeda16e54efe4a8fc1bea8e658be2 100644 (file)
@@ -1,98 +1,98 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: COMM_FSM.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity COMM_FSM is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic; \r
-       PCI_RSTn                :in             std_logic; \r
-       IO_READ                 :in             std_logic;\r
-       IO_WRITE                :in             std_logic;\r
-       CONF_READ               :in             std_logic;\r
-       CONF_WRITE      :in             std_logic;\r
-       DEVSELn                 :in             std_logic;      \r
-\r
-       IO_RD_COM       :       out     std_logic;--> MUX_SEL(0)                                                      \r
-       CF_RD_COM       :out    std_logic; \r
-       IO_WR_COM               :out    std_logic;     \r
-       CF_WR_COM               :out    std_logic \r
-       );\r
-end entity COMM_FSM ;\r
-\r
-architecture COMM_FSM_DESIGN of COMM_FSM is\r
-\r
-\r
---**********************************************************\r
---***            COMMAND FSM CODIERUNG                   ***\r
---**********************************************************\r
---\r
---\r
---                                                                        |--------- IO_RD_COM                                                    \r
---                                                                        ||-------- CF_RD_COM   \r
---                                                                                    |||------- IO_WR_COM   \r
---                                                                                ||||------ CF_WR_COM   \r
---                                                                            ||||     \r
-       constant        ST_IDLE_COMM    :std_logic_vector (3 downto 0) := "0000" ;-- \r
-       constant        ST_CONF_WRITE   :std_logic_vector (3 downto 0) := "0001" ;-- \r
-       constant        ST_IO_WRITE             :std_logic_vector (3 downto 0) := "0010" ;-- \r
-       constant        ST_CONF_READ    :std_logic_vector (3 downto 0) := "0100" ;-- \r
-       constant        ST_IO_READ              :std_logic_vector (3 downto 0) := "1000" ;--\r
-\r
-       signal          COMM_STATE              :std_logic_vector (3 downto 0);\r
-\r
---************************************************************\r
---***             FSM SPEICHER-AUTOMAT                     ***\r
---************************************************************\r
-\r
-       attribute syn_state_machine : boolean;\r
-       attribute syn_state_machine of COMM_STATE : signal is false;\r
-\r
-begin\r
-\r
---**********************************************************\r
---***                   COMMAND FSM                        ***\r
---**********************************************************\r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    COMM_STATE      <= "0000";\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
\r
-                       case COMM_STATE is\r
-       \r
-                               when ST_IDLE_COMM => \r
-                                       if              IO_READ                         = '1' then                                                      COMM_STATE <= ST_IO_READ;\r
-\r
-                               elsif   CONF_READ               = '1' then                                                      COMM_STATE <= ST_CONF_READ; \r
-\r
-                                               elsif   IO_WRITE                = '1' then                                                      COMM_STATE <= ST_IO_WRITE;   \r
-  \r
-                               elsif   CONF_WRITE      = '1' then                                                      COMM_STATE <= ST_CONF_WRITE;     \r
-\r
-                   else                                                                                                                                                COMM_STATE <= ST_IDLE_COMM;\r
-                                       end if;                                                 \r
-       \r
-                               when ST_IO_READ                 => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
-                               when ST_CONF_READ               => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
-                               when ST_IO_WRITE                => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
-                               when ST_CONF_WRITE      => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;\r
-       \r
-                               when others =>                                                                                                                          COMM_STATE <= ST_IDLE_COMM; \r
-\r
-                       end case;               -- COMM_STATE    \r
-               end if;                         -- CLOCK   \r
-       end process;            -- PROCESS\r
-\r
-       IO_RD_COM       <=      COMM_STATE(3);                                                     \r
-       CF_RD_COM       <=      COMM_STATE(2);      \r
-       IO_WR_COM       <=      COMM_STATE(1);      \r
-       CF_WR_COM       <=      COMM_STATE(0);      \r
-       \r
-end architecture COMM_FSM_DESIGN ;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: COMM_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity COMM_FSM is
+       port
+       (
+       PCI_CLOCK               :in             std_logic; 
+       PCI_RSTn                :in             std_logic; 
+       IO_READ                 :in             std_logic;
+       IO_WRITE                :in             std_logic;
+       CONF_READ               :in             std_logic;
+       CONF_WRITE      :in             std_logic;
+       DEVSELn                 :in             std_logic;      
+
+       IO_RD_COM       :       out     std_logic;--> MUX_SEL(0)                                                      
+       CF_RD_COM       :out    std_logic; 
+       IO_WR_COM               :out    std_logic;     
+       CF_WR_COM               :out    std_logic 
+       );
+end entity COMM_FSM ;
+
+architecture COMM_FSM_DESIGN of COMM_FSM is
+
+
+--**********************************************************
+--***            COMMAND FSM CODIERUNG                   ***
+--**********************************************************
+--
+--
+--                                                                        |--------- IO_RD_COM                                                    
+--                                                                        ||-------- CF_RD_COM   
+--                                                                                    |||------- IO_WR_COM   
+--                                                                                ||||------ CF_WR_COM   
+--                                                                            ||||     
+       constant        ST_IDLE_COMM    :std_logic_vector (3 downto 0) := "0000" ;-- 
+       constant        ST_CONF_WRITE   :std_logic_vector (3 downto 0) := "0001" ;-- 
+       constant        ST_IO_WRITE             :std_logic_vector (3 downto 0) := "0010" ;-- 
+       constant        ST_CONF_READ    :std_logic_vector (3 downto 0) := "0100" ;-- 
+       constant        ST_IO_READ              :std_logic_vector (3 downto 0) := "1000" ;--
+
+       signal          COMM_STATE              :std_logic_vector (3 downto 0);
+
+--************************************************************
+--***             FSM SPEICHER-AUTOMAT                     ***
+--************************************************************
+
+       attribute syn_state_machine : boolean;
+       attribute syn_state_machine of COMM_STATE : signal is false;
+
+begin
+
+--**********************************************************
+--***                   COMMAND FSM                        ***
+--**********************************************************
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then    COMM_STATE      <= "0000";
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                       case COMM_STATE is
+       
+                               when ST_IDLE_COMM => 
+                                       if              IO_READ                         = '1' then                                                      COMM_STATE <= ST_IO_READ;
+
+                               elsif   CONF_READ               = '1' then                                                      COMM_STATE <= ST_CONF_READ; 
+
+                                               elsif   IO_WRITE                = '1' then                                                      COMM_STATE <= ST_IO_WRITE;   
+  
+                               elsif   CONF_WRITE      = '1' then                                                      COMM_STATE <= ST_CONF_WRITE;     
+
+                   else                                                                                                                                                COMM_STATE <= ST_IDLE_COMM;
+                                       end if;                                                 
+       
+                               when ST_IO_READ                 => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             
+                               when ST_CONF_READ               => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             
+                               when ST_IO_WRITE                => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             
+                               when ST_CONF_WRITE      => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;
+       
+                               when others =>                                                                                                                          COMM_STATE <= ST_IDLE_COMM; 
+
+                       end case;               -- COMM_STATE    
+               end if;                         -- CLOCK   
+       end process;            -- PROCESS
+
+       IO_RD_COM       <=      COMM_STATE(3);                                                     
+       CF_RD_COM       <=      COMM_STATE(2);      
+       IO_WR_COM       <=      COMM_STATE(1);      
+       CF_WR_COM       <=      COMM_STATE(0);      
+       
+end architecture COMM_FSM_DESIGN ;
+
index 025c1e7a155f82c85b60b7e8647a3614fba7bd3a..2527c8ad31a0450a8a9cdba9815f674ab951cedb 100644 (file)
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONT_FSM.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity CONT_FSM is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic; \r
-       PCI_RSTn                :in             std_logic; \r
-       IO_READ                 :in             std_logic;\r
-       IO_WRITE                :in             std_logic;\r
-       CONF_READ               :in             std_logic;\r
-       CONF_WRITE      :in             std_logic;\r
-       FIFO_READ               :in             std_logic;\r
-       READ                            :out    std_logic;--> MUX_SEL(1) , OE_PCI_AD \r
-       PERR_CHECK      :out    std_logic;              \r
-       DEVSELn                 :out    std_logic;\r
-       OE_PCI_PAR      :out    std_logic;\r
-       OE_PCI_PERR     :out    std_logic;\r
-       TRDYn                           :out    std_logic;\r
-       PCI_TRDYn               :out    std_logic;      --      s/t/s\r
-       PCI_STOPn               :out    std_logic;      --      s/t/s   \r
-       PCI_DEVSELn     :out    std_logic;      --      s/t/s   \r
-       FIFO_RDn                :out    std_logic\r
-       );\r
-end entity CONT_FSM ;\r
-\r
-architecture CONT_FSM_DESIGN of CONT_FSM is\r
-\r
-\r
-\r
---**********************************************************\r
---***              CONTROL FSM CODIERUNG                 ***\r
---**********************************************************\r
---\r
---\r
---\r
---                                                           |----------- HELP\r
---                                                           ||---------- FIFO_READn\r
---                                                           |||--------- OE_PCI_PERR          \r
---                                                                                                      ||||-------- PERR_CHECK  \r
---                                                                                                              |||||------- TRDYn   \r
---                                                                                                                ||||||------ STOPn                                                    \r
---                                                                                                              |||||||----- DEVSELn   \r
---                                                                                        ||||||||---- OE_PCI_PAR   \r
---                                                                                                                                                                                                                              |||||||||--- OE_CONTROL   \r
---                                                                                                                                                                                                                                ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD \r
---                                                                                                                                                                                                                                      ||||||||||               \r
-       constant        ST_IDLE :std_logic_vector (9 downto 0) := "0100111000" ;-- 138\r
-\r
-       constant        ST_READ_1                       :std_logic_vector (9 downto 0) := "0100110011" ;-- 133\r
-       constant        ST_READ_2                       :std_logic_vector (9 downto 0) := "0100000111" ;-- 107\r
-       constant        ST_READ_3                       :std_logic_vector (9 downto 0) := "0100111111" ;-- 13F\r
-\r
-       constant        ST_RD_FIFO_1    :std_logic_vector (9 downto 0) := "0000110011" ;-- 033\r
-       constant        ST_RD_FIFO_2    :std_logic_vector (9 downto 0) := "1100110011" ;-- 233\r
-\r
-\r
-       constant        ST_WRITE_1              :std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2\r
-       constant        ST_WRITE_2              :std_logic_vector (9 downto 0) := "0110000010" ;-- 182\r
-       constant        ST_WRITE_3              :std_logic_vector (9 downto 0) := "0110111010" ;-- 1BA\r
-\r
-       signal          CONTROL_STATE   :std_logic_vector (9 downto 0);\r
-\r
-\r
---signal               DEVSELn                 :std_logic;\r
-       signal          STOPn                   :std_logic;\r
---signal               TRDYn                   :std_logic;\r
-\r
---************************************************************\r
---***             FSM SPEICHER-AUTOMAT                     ***\r
---************************************************************\r
-\r
-       attribute syn_state_machine : boolean;\r
-       attribute syn_state_machine of CONTROL_STATE : signal is false;\r
-\r
-begin\r
-\r
---**********************************************************\r
---***                  CONTROL FSM                       ***\r
---**********************************************************\r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    CONTROL_STATE   <= ST_IDLE;\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
\r
-                       case CONTROL_STATE is\r
-       \r
-                               when ST_IDLE => \r
-                                       if                      IO_READ         = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_READ_1;\r
-\r
-                               elsif   CONF_READ       = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_READ_1; \r
-\r
-                                               elsif   IO_WRITE        = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_WRITE_1;   \r
-  \r
-                               elsif   CONF_WRITE      = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_WRITE_1;\r
-     \r
-                       else                                            CONTROL_STATE <= ST_IDLE;\r
-                                       end if; \r
-\r
---                     when    ST_READ_1               =>      CONTROL_STATE   <=      ST_READ_2;\r
-                               when    ST_READ_1               =>      \r
-                                       if                      FIFO_READ       = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_RD_FIFO_1;\r
-                                               else                                            CONTROL_STATE <= ST_READ_2;\r
-                                       end if; \r
-\r
-\r
-                               when    ST_READ_2               =>      CONTROL_STATE   <=      ST_READ_3;\r
-                               when    ST_READ_3               =>      CONTROL_STATE   <=      ST_IDLE;\r
-\r
-                               when    ST_RD_FIFO_1=>  CONTROL_STATE   <=      ST_RD_FIFO_2;\r
-                               when    ST_RD_FIFO_2=>  CONTROL_STATE   <=      ST_READ_2;\r
-\r
-\r
-        \r
-                               when    ST_WRITE_1      =>      CONTROL_STATE   <=      ST_WRITE_2;\r
-                               when    ST_WRITE_2      =>      CONTROL_STATE   <=      ST_WRITE_3;\r
-                               when    ST_WRITE_3      =>      CONTROL_STATE   <=      ST_IDLE;\r
-\r
-               \r
-                               when others                             =>      CONTROL_STATE   <=      ST_IDLE; \r
-\r
-                       end case;               -- COMM_STATE    \r
-               end if;                         -- CLOCK   \r
-       end process;                    -- PROCESS\r
-\r
-\r
-       READ                            <=      CONTROL_STATE(0);\r
---OE_CONTROL   <=      CONTROL_STATE(1);\r
-       OE_PCI_PAR      <=      CONTROL_STATE(2);\r
-       DEVSELn                 <=      CONTROL_STATE(3);\r
-       STOPn                           <=      CONTROL_STATE(4);\r
-       TRDYn                           <=      CONTROL_STATE(5);\r
-       PERR_CHECK      <=      CONTROL_STATE(6);\r
-       OE_PCI_PERR     <=      CONTROL_STATE(7);\r
-\r
-       FIFO_RDn                <=      CONTROL_STATE(8);\r
-\r
-\r
-       PCI_DEVSELn     <=      CONTROL_STATE(3)        when    CONTROL_STATE(1) = '1' else 'Z';\r
-       PCI_STOPn       <=      STOPn                                   when    CONTROL_STATE(1) = '1' else 'Z';                                                                      \r
-       PCI_TRDYn         <=    CONTROL_STATE(5)        when    CONTROL_STATE(1) = '1' else 'Z';        \r
-\r
-end architecture CONT_FSM_DESIGN ;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONT_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity CONT_FSM is
+       port
+       (
+       PCI_CLOCK               :in             std_logic; 
+       PCI_RSTn                :in             std_logic; 
+       IO_READ                 :in             std_logic;
+       IO_WRITE                :in             std_logic;
+       CONF_READ               :in             std_logic;
+       CONF_WRITE      :in             std_logic;
+       FIFO_READ               :in             std_logic;
+       READ                            :out    std_logic;--> MUX_SEL(1) , OE_PCI_AD 
+       PERR_CHECK      :out    std_logic;              
+       DEVSELn                 :out    std_logic;
+       OE_PCI_PAR      :out    std_logic;
+       OE_PCI_PERR     :out    std_logic;
+       TRDYn                           :out    std_logic;
+       PCI_TRDYn               :out    std_logic;      --      s/t/s
+       PCI_STOPn               :out    std_logic;      --      s/t/s   
+       PCI_DEVSELn     :out    std_logic;      --      s/t/s   
+       FIFO_RDn                :out    std_logic
+       );
+end entity CONT_FSM ;
+
+architecture CONT_FSM_DESIGN of CONT_FSM is
+
+
+
+--**********************************************************
+--***              CONTROL FSM CODIERUNG                 ***
+--**********************************************************
+--
+--
+--
+--                                                           |----------- HELP
+--                                                           ||---------- FIFO_READn
+--                                                           |||--------- OE_PCI_PERR          
+--                                                                                                      ||||-------- PERR_CHECK  
+--                                                                                                              |||||------- TRDYn   
+--                                                                                                                ||||||------ STOPn                                                    
+--                                                                                                              |||||||----- DEVSELn   
+--                                                                                        ||||||||---- OE_PCI_PAR   
+--                                                                                                                                                                                                                              |||||||||--- OE_CONTROL   
+--                                                                                                                                                                                                                                ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD 
+--                                                                                                                                                                                                                                      ||||||||||               
+       constant        ST_IDLE :std_logic_vector (9 downto 0) := "0100111000" ;-- 138
+
+       constant        ST_READ_1                       :std_logic_vector (9 downto 0) := "0100110011" ;-- 133
+       constant        ST_READ_2                       :std_logic_vector (9 downto 0) := "0100000111" ;-- 107
+       constant        ST_READ_3                       :std_logic_vector (9 downto 0) := "0100111111" ;-- 13F
+
+       constant        ST_RD_FIFO_1    :std_logic_vector (9 downto 0) := "0000110011" ;-- 033
+       constant        ST_RD_FIFO_2    :std_logic_vector (9 downto 0) := "1100110011" ;-- 233
+
+
+       constant        ST_WRITE_1              :std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2
+       constant        ST_WRITE_2              :std_logic_vector (9 downto 0) := "0110000010" ;-- 182
+       constant        ST_WRITE_3              :std_logic_vector (9 downto 0) := "0110111010" ;-- 1BA
+
+       signal          CONTROL_STATE   :std_logic_vector (9 downto 0);
+
+
+--signal               DEVSELn                 :std_logic;
+       signal          STOPn                   :std_logic;
+--signal               TRDYn                   :std_logic;
+
+--************************************************************
+--***             FSM SPEICHER-AUTOMAT                     ***
+--************************************************************
+
+       attribute syn_state_machine : boolean;
+       attribute syn_state_machine of CONTROL_STATE : signal is false;
+
+begin
+
+--**********************************************************
+--***                  CONTROL FSM                       ***
+--**********************************************************
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then    CONTROL_STATE   <= ST_IDLE;
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                       case CONTROL_STATE is
+       
+                               when ST_IDLE => 
+                                       if                      IO_READ         = '1' then
+                                                                                                                       CONTROL_STATE <= ST_READ_1;
+
+                               elsif   CONF_READ       = '1' then
+                                                                                                                       CONTROL_STATE <= ST_READ_1; 
+
+                                               elsif   IO_WRITE        = '1' then
+                                                                                                                       CONTROL_STATE <= ST_WRITE_1;   
+  
+                               elsif   CONF_WRITE      = '1' then
+                                                                                                                       CONTROL_STATE <= ST_WRITE_1;
+     
+                       else                                            CONTROL_STATE <= ST_IDLE;
+                                       end if; 
+
+--                     when    ST_READ_1               =>      CONTROL_STATE   <=      ST_READ_2;
+                               when    ST_READ_1               =>      
+                                       if                      FIFO_READ       = '1' then
+                                                                                                                       CONTROL_STATE <= ST_RD_FIFO_1;
+                                               else                                            CONTROL_STATE <= ST_READ_2;
+                                       end if; 
+
+
+                               when    ST_READ_2               =>      CONTROL_STATE   <=      ST_READ_3;
+                               when    ST_READ_3               =>      CONTROL_STATE   <=      ST_IDLE;
+
+                               when    ST_RD_FIFO_1=>  CONTROL_STATE   <=      ST_RD_FIFO_2;
+                               when    ST_RD_FIFO_2=>  CONTROL_STATE   <=      ST_READ_2;
+
+
+        
+                               when    ST_WRITE_1      =>      CONTROL_STATE   <=      ST_WRITE_2;
+                               when    ST_WRITE_2      =>      CONTROL_STATE   <=      ST_WRITE_3;
+                               when    ST_WRITE_3      =>      CONTROL_STATE   <=      ST_IDLE;
+
+               
+                               when others                             =>      CONTROL_STATE   <=      ST_IDLE; 
+
+                       end case;               -- COMM_STATE    
+               end if;                         -- CLOCK   
+       end process;                    -- PROCESS
+
+
+       READ                            <=      CONTROL_STATE(0);
+--OE_CONTROL   <=      CONTROL_STATE(1);
+       OE_PCI_PAR      <=      CONTROL_STATE(2);
+       DEVSELn                 <=      CONTROL_STATE(3);
+       STOPn                           <=      CONTROL_STATE(4);
+       TRDYn                           <=      CONTROL_STATE(5);
+       PERR_CHECK      <=      CONTROL_STATE(6);
+       OE_PCI_PERR     <=      CONTROL_STATE(7);
+
+       FIFO_RDn                <=      CONTROL_STATE(8);
+
+
+       PCI_DEVSELn     <=      CONTROL_STATE(3)        when    CONTROL_STATE(1) = '1' else 'Z';
+       PCI_STOPn       <=      STOPn                                   when    CONTROL_STATE(1) = '1' else 'Z';                                                                      
+       PCI_TRDYn         <=    CONTROL_STATE(5)        when    CONTROL_STATE(1) = '1' else 'Z';        
+
+end architecture CONT_FSM_DESIGN ;
+
index 46632e2a830c7fac63bc5443146b95af7521e9bf..092f12bdf28c9af8d915318e33acc3253a72bde4 100644 (file)
@@ -1,77 +1,77 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: DATA_MUX.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
\r
-entity DATA_MUX is\r
-       port\r
-       (\r
-       READ_SEL                :in             std_logic_vector( 1 downto 0);\r
-       ADDR_REG                :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
-       MUX_IN_XX0      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX1      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX2      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX3      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX4      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX5      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX6      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX7      :in             std_logic_vector( 7 downto 0);\r
-       MUX_OUT                 :out    std_logic_vector(31 downto 0);\r
-       READ_XX1_0      :out    std_logic;      \r
-       READ_XX3_2      :out    std_logic;\r
-       READ_XX5_4      :out    std_logic;\r
-       READ_XX7_6      :out    std_logic\r
---READ_FIFO            :out    std_logic\r
-       );\r
-end entity DATA_MUX ;\r
-\r
-architecture DATA_MUX_DESIGN of DATA_MUX is\r
-\r
-       signal  MUX     :std_logic_vector(31 downto 0);\r
-       signal  SEL     :std_logic_vector( 7 downto 0);\r
-\r
-       signal  SIG_READ_XX1_0  :std_logic;\r
-       signal  SIG_READ_XX3_2  :std_logic;\r
-       signal  SIG_READ_XX5_4  :std_logic;\r
-       signal  SIG_READ_XX7_6  :std_logic;\r
-\r
-begin\r
-\r
-       SEL     <= ADDR_REG(3 downto 2) & CBE_REGn      &       READ_SEL ;      \r
-                                                                                                                                                                                                                                                                               \r
-       SIG_READ_XX1_0  <=      '1' when        SEL     =       "00110011"      else    '0';\r
-       SIG_READ_XX3_2  <=      '1' when        SEL     =       "00001111"      else    '0';\r
-       SIG_READ_XX5_4  <=      '1' when        SEL     =       "01110011"      else    '0';\r
-       SIG_READ_XX7_6  <=      '1' when        SEL     =       "01001111"      else    '0';\r
-\r
-\r
-                                                                       \r
-       MUX     <=      (X"00"                  & X"00"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else \r
-                                       (MUX_IN_XX3     &       MUX_IN_XX2  &   X"00"                           & X"00"                 )       when    SIG_READ_XX3_2  =       '1' else                                \r
-                                       (X"00"                  & X"00"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else \r
-                                       (MUX_IN_XX7     &       MUX_IN_XX6  &   X"00"                           & X"00"                 )       when    SIG_READ_XX7_6  =       '1' else        \r
-                                       (others => '0');                                                                                                                                                                                                                                                                                                \r
-\r
-\r
---     MUX     <=      (X"01"                  & X"23"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else \r
---                                     (MUX_IN_XX3     &       MUX_IN_XX2  &   X"45"                           & X"67"                 )       when    SIG_READ_XX3_2  =       '1' else                                \r
---                                     (X"89"                  & X"AB"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else \r
---                                     (MUX_IN_XX7     &       MUX_IN_XX6  &   X"CD"                           & X"EF"                 )       when    SIG_READ_XX7_6  =       '1' else        \r
---                                     (others => '0');                                                                                                                                                                                                                                                                                                \r
-\r
-\r
-       MUX_OUT <= MUX ;\r
-\r
-\r
-       READ_XX1_0      <=      SIG_READ_XX1_0;                 \r
-       READ_XX3_2      <=      SIG_READ_XX3_2;\r
-       READ_XX5_4      <=      SIG_READ_XX5_4;\r
-       READ_XX7_6      <=      SIG_READ_XX7_6;\r
-\r
---READ_FIFO            <=      SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test\r
-\r
-end architecture DATA_MUX_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: DATA_MUX.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+entity DATA_MUX is
+       port
+       (
+       READ_SEL                :in             std_logic_vector( 1 downto 0);
+       ADDR_REG                :in             std_logic_vector(31 downto 0);
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);
+       MUX_IN_XX0      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX1      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX2      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX3      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX4      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX5      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX6      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX7      :in             std_logic_vector( 7 downto 0);
+       MUX_OUT                 :out    std_logic_vector(31 downto 0);
+       READ_XX1_0      :out    std_logic;      
+       READ_XX3_2      :out    std_logic;
+       READ_XX5_4      :out    std_logic;
+       READ_XX7_6      :out    std_logic
+--READ_FIFO            :out    std_logic
+       );
+end entity DATA_MUX ;
+
+architecture DATA_MUX_DESIGN of DATA_MUX is
+
+       signal  MUX     :std_logic_vector(31 downto 0);
+       signal  SEL     :std_logic_vector( 7 downto 0);
+
+       signal  SIG_READ_XX1_0  :std_logic;
+       signal  SIG_READ_XX3_2  :std_logic;
+       signal  SIG_READ_XX5_4  :std_logic;
+       signal  SIG_READ_XX7_6  :std_logic;
+
+begin
+
+       SEL     <= ADDR_REG(3 downto 2) & CBE_REGn      &       READ_SEL ;      
+                                                                                                                                                                                                                                                                               
+       SIG_READ_XX1_0  <=      '1' when        SEL     =       "00110011"      else    '0';
+       SIG_READ_XX3_2  <=      '1' when        SEL     =       "00001111"      else    '0';
+       SIG_READ_XX5_4  <=      '1' when        SEL     =       "01110011"      else    '0';
+       SIG_READ_XX7_6  <=      '1' when        SEL     =       "01001111"      else    '0';
+
+
+                                                                       
+       MUX     <=      (X"00"                  & X"00"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else 
+                                       (MUX_IN_XX3     &       MUX_IN_XX2  &   X"00"                           & X"00"                 )       when    SIG_READ_XX3_2  =       '1' else                                
+                                       (X"00"                  & X"00"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else 
+                                       (MUX_IN_XX7     &       MUX_IN_XX6  &   X"00"                           & X"00"                 )       when    SIG_READ_XX7_6  =       '1' else        
+                                       (others => '0');                                                                                                                                                                                                                                                                                                
+
+
+--     MUX     <=      (X"01"                  & X"23"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else 
+--                                     (MUX_IN_XX3     &       MUX_IN_XX2  &   X"45"                           & X"67"                 )       when    SIG_READ_XX3_2  =       '1' else                                
+--                                     (X"89"                  & X"AB"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else 
+--                                     (MUX_IN_XX7     &       MUX_IN_XX6  &   X"CD"                           & X"EF"                 )       when    SIG_READ_XX7_6  =       '1' else        
+--                                     (others => '0');                                                                                                                                                                                                                                                                                                
+
+
+       MUX_OUT <= MUX ;
+
+
+       READ_XX1_0      <=      SIG_READ_XX1_0;                 
+       READ_XX3_2      <=      SIG_READ_XX3_2;
+       READ_XX5_4      <=      SIG_READ_XX5_4;
+       READ_XX7_6      <=      SIG_READ_XX7_6;
+
+--READ_FIFO            <=      SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test
+
+end architecture DATA_MUX_DESIGN ;
index dd95bb256fd2d77db99dad61fce58f57f3517293..480f48407ef75ac98422cc9fe05ef220f05379f6 100644 (file)
@@ -1,98 +1,98 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: FLAG_BUS.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity FLAG_BUS is\r
-       port\r
-       (\r
-       PCI_CLOCK       :in             std_logic;\r
-       KONS_1          :in             std_logic;\r
-       FLAG_IN_0       :in             std_logic;\r
-       R_EFn                   :in             std_logic;\r
-       R_HFn                   :in             std_logic;\r
-       R_FFn                   :in             std_logic;\r
-       FLAG_IN_4       :in             std_logic;\r
-       S_EFn                   :in             std_logic;\r
-       S_HFn                   :in             std_logic;\r
-       S_FFn                   :in             std_logic;\r
-       HOLD                    :in             std_logic;\r
-       SYNC_FLAG       :out    std_logic_vector (7 downto 0)\r
-       );      \r
-end entity FLAG_BUS;\r
-\r
-architecture FLAG_BUS_DESIGN of FLAG_BUS is\r
-\r
-\r
-signal FF1_S_EFn       :std_logic;     \r
-signal FF1_S_HFn       :std_logic;\r
-signal FF1_S_FFn       :std_logic;\r
-signal FF1_R_EFn       :std_logic;\r
-signal FF1_R_HFn       :std_logic;\r
-signal FF1_R_FFn       :std_logic;\r
-\r
-signal FF2_S_EFn       :std_logic;     \r
-signal FF2_S_HFn       :std_logic;\r
-signal FF2_S_FFn       :std_logic;\r
-signal FF2_R_EFn       :std_logic;\r
-signal FF2_R_HFn       :std_logic;\r
-signal FF2_R_FFn       :std_logic;\r
-\r
-begin\r
-\r
-\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then \r
-\r
-               FF1_S_EFn       <=      not S_EFn;\r
-               FF1_S_HFn       <=      not S_HFn;\r
-               FF1_S_FFn       <=      not S_FFn;\r
-               FF1_R_EFn       <=      not R_EFn;\r
-               FF1_R_HFn       <=      not R_HFn;\r
-               FF1_R_FFn       <=      not R_FFn;\r
-\r
-               end if;\r
-       end process;    \r
-\r
-\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then  \r
-\r
-                       if                      HOLD    =       '0'     then\r
-\r
-                                       FF2_S_EFn       <=      FF1_S_EFn;      \r
-                                       FF2_S_HFn       <=      FF1_S_HFn;\r
-                                       FF2_S_FFn       <=      FF1_S_FFn;\r
-                                       FF2_R_EFn       <=      FF1_R_EFn;\r
-                                       FF2_R_HFn       <=      FF1_R_HFn;\r
-                                       FF2_R_FFn       <=      FF1_R_FFn;\r
-\r
-                               elsif   HOLD    =       '1'     then\r
-\r
-                                       FF2_S_EFn       <=      FF2_S_EFn;      \r
-                                       FF2_S_HFn       <=      FF2_S_HFn;\r
-                                       FF2_S_FFn       <=      FF2_S_FFn;\r
-                                       FF2_R_EFn       <=      FF2_R_EFn;\r
-                                       FF2_R_HFn       <=      FF2_R_HFn;\r
-                                       FF2_R_FFn       <=      FF2_R_FFn;\r
-\r
-                       end if;\r
-               end if;\r
-       end process;    \r
-\r
-       SYNC_FLAG(0)    <=      FLAG_IN_0;              \r
-       SYNC_FLAG(1)    <=      FF2_R_EFn;      \r
-       SYNC_FLAG(2)    <=      FF2_R_HFn;\r
-       SYNC_FLAG(3)    <=      FF2_R_FFn;\r
-       SYNC_FLAG(4)    <=      FLAG_IN_4;              \r
-       SYNC_FLAG(5)    <=      FF2_S_EFn;      \r
-       SYNC_FLAG(6)    <=      FF2_S_HFn;\r
-       SYNC_FLAG(7)    <=      FF2_S_FFn;\r
-\r
-end architecture FLAG_BUS_DESIGN;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: FLAG_BUS.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FLAG_BUS is
+       port
+       (
+       PCI_CLOCK       :in             std_logic;
+       KONS_1          :in             std_logic;
+       FLAG_IN_0       :in             std_logic;
+       R_EFn                   :in             std_logic;
+       R_HFn                   :in             std_logic;
+       R_FFn                   :in             std_logic;
+       FLAG_IN_4       :in             std_logic;
+       S_EFn                   :in             std_logic;
+       S_HFn                   :in             std_logic;
+       S_FFn                   :in             std_logic;
+       HOLD                    :in             std_logic;
+       SYNC_FLAG       :out    std_logic_vector (7 downto 0)
+       );      
+end entity FLAG_BUS;
+
+architecture FLAG_BUS_DESIGN of FLAG_BUS is
+
+
+signal FF1_S_EFn       :std_logic;     
+signal FF1_S_HFn       :std_logic;
+signal FF1_S_FFn       :std_logic;
+signal FF1_R_EFn       :std_logic;
+signal FF1_R_HFn       :std_logic;
+signal FF1_R_FFn       :std_logic;
+
+signal FF2_S_EFn       :std_logic;     
+signal FF2_S_HFn       :std_logic;
+signal FF2_S_FFn       :std_logic;
+signal FF2_R_EFn       :std_logic;
+signal FF2_R_HFn       :std_logic;
+signal FF2_R_FFn       :std_logic;
+
+begin
+
+
+       process (PCI_CLOCK) 
+       begin 
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then 
+
+               FF1_S_EFn       <=      not S_EFn;
+               FF1_S_HFn       <=      not S_HFn;
+               FF1_S_FFn       <=      not S_FFn;
+               FF1_R_EFn       <=      not R_EFn;
+               FF1_R_HFn       <=      not R_HFn;
+               FF1_R_FFn       <=      not R_FFn;
+
+               end if;
+       end process;    
+
+
+       process (PCI_CLOCK) 
+       begin 
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then  
+
+                       if                      HOLD    =       '0'     then
+
+                                       FF2_S_EFn       <=      FF1_S_EFn;      
+                                       FF2_S_HFn       <=      FF1_S_HFn;
+                                       FF2_S_FFn       <=      FF1_S_FFn;
+                                       FF2_R_EFn       <=      FF1_R_EFn;
+                                       FF2_R_HFn       <=      FF1_R_HFn;
+                                       FF2_R_FFn       <=      FF1_R_FFn;
+
+                               elsif   HOLD    =       '1'     then
+
+                                       FF2_S_EFn       <=      FF2_S_EFn;      
+                                       FF2_S_HFn       <=      FF2_S_HFn;
+                                       FF2_S_FFn       <=      FF2_S_FFn;
+                                       FF2_R_EFn       <=      FF2_R_EFn;
+                                       FF2_R_HFn       <=      FF2_R_HFn;
+                                       FF2_R_FFn       <=      FF2_R_FFn;
+
+                       end if;
+               end if;
+       end process;    
+
+       SYNC_FLAG(0)    <=      FLAG_IN_0;              
+       SYNC_FLAG(1)    <=      FF2_R_EFn;      
+       SYNC_FLAG(2)    <=      FF2_R_HFn;
+       SYNC_FLAG(3)    <=      FF2_R_FFn;
+       SYNC_FLAG(4)    <=      FLAG_IN_4;              
+       SYNC_FLAG(5)    <=      FF2_S_EFn;      
+       SYNC_FLAG(6)    <=      FF2_S_HFn;
+       SYNC_FLAG(7)    <=      FF2_S_FFn;
+
+end architecture FLAG_BUS_DESIGN;
+
index cba393572b11e86209eef3a04c5a51d9fc0ffe94..04136588e3beff7900a39a150a54cf409077cdda 100644 (file)
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: INTERRUPT.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity INTERRUPT is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic;\r
-       PCI_RSTn                :in     std_logic; -- PCI reset is asynchron (low active)\r
-       RESET                           :in     std_logic;\r
-       TAST_SETn               :in     std_logic;\r
-       TAST_RESn               :in     std_logic;\r
-       INT_IN_0                :in             std_logic;\r
-       INT_IN_1                :in             std_logic;\r
-       INT_IN_2                :in             std_logic;\r
-       INT_IN_3                :in             std_logic;\r
-       INT_IN_4                :in             std_logic;\r
-       INT_IN_5                :in             std_logic;\r
-       INT_IN_6                :in             std_logic;\r
-       INT_IN_7                :in             std_logic;\r
-       TRDYn                           :in     std_logic;  -- event 1 after read of Interrupt status register (low active)\r
-       READ_XX5_4      :in     std_logic;      -- event 2 after read of Interrupt status register\r
-       INT_RES                 :in             std_logic_vector(7 downto 0); -- clear selected interrupts\r
-       INT_MASKE               :in             std_logic_vector(7 downto 0);   -- interrupt mask register\r
-       INT_REG                 :out    std_logic_vector(7 downto 0); -- interrupt status register\r
-       INTAn                           :out    std_logic;      -- second interrupt line for PCI analyzer\r
-       PCI_INTAn               :out    std_logic               -- PCI interrupt line \r
-       );\r
-\r
-end entity INTERRUPT;\r
-\r
-architecture INTERRUPT_DESIGN of INTERRUPT is\r
-\r
-       signal  SIG_TAST_Q              :std_logic;\r
-       signal  SIG_TAST_Qn             :std_logic;\r
-\r
-\r
-       signal  SIG_INTA                        :std_logic; \r
-\r
-       signal FF_A                     :std_logic_vector(7 downto 0);\r
-       signal FF_B                     :std_logic_vector(7 downto 0);  \r
-       signal SET                      :std_logic_vector(7 downto 0);  \r
-\r
-       signal  SIG_PROPAGATE_INT :std_logic;\r
-       signal  SIG_PROPAGATE_INT_SECOND :std_logic;\r
-       signal  REG :std_logic_vector(7 downto 0);\r
-\r
-begin\r
-\r
-\r
-\r
-\r
-------------------------------------------------------\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
-\r
-                        -- THIS IS BROKEN (it cycles the interrupt)\r
-                       SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);\r
-                       SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);\r
-       \r
-               end if;\r
-       end process;    \r
-\r
-------------------------------------------------------\r
-\r
-       process (PCI_CLOCK)\r
-       begin\r
-    if (PCI_RSTn = '0') then\r
-                                       SET <= "00000000";\r
-          FF_A <= "00000000";\r
-          FF_B <= "00000000";\r
-\r
-               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
-               if(RESET = '1') then\r
-                                               SET <= "00000000";\r
-            FF_A       <= "00000000";\r
-            FF_B       <= "00000000";\r
-      else     \r
-\r
-                       FF_A(0) <=                      INT_IN_0 ;  -- Receive FIFO Empty Flag\r
-\r
-                       FF_A(1) <=                      INT_IN_1 ;  -- Send FIFO Half Full\r
-                       FF_A(2) <=                      INT_IN_2 ; \r
-                       FF_A(3) <=                      INT_IN_3 ; \r
-\r
-                       FF_A(4) <=                      INT_IN_4 ; \r
-\r
-                       FF_A(5) <=                      INT_IN_5 ; \r
-                       FF_A(6) <=                      INT_IN_6 ; \r
-                       FF_A(7) <=                      INT_IN_7 ; \r
-\r
-                       FF_B    <= FF_A ;\r
-\r
-                       SET <= FF_A AND not FF_B;\r
-               end if;\r
-               end if;\r
-       end process;\r
-\r
-       process (PCI_CLOCK,PCI_RSTn)\r
-       begin\r
-               if (PCI_RSTn = '0') then\r
-                       REG <= "00000000";\r
-\r
-               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
-                               if(RESET = '1') then\r
-                                       REG <= "00000000";\r
-\r
-               -- elsif(SIG_TAST_Q = '1') then\r
-               --      REG <= "00000000" or SET;\r
-               \r
-\r
-        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
-            REG <= (REG AND NOT INT_RES) OR SET;\r
-        else\r
-            REG <= REG OR SET;\r
-        end if;\r
-    end if;\r
-       end process;\r
-\r
-       SIG_PROPAGATE_INT <=\r
-            (REG(0) AND INT_MASKE(0)) \r
-            OR (REG(1) AND INT_MASKE(1))\r
-            OR (REG(2) AND INT_MASKE(2))\r
-            OR (REG(3) AND INT_MASKE(3))\r
-            OR (REG(4) AND INT_MASKE(4))\r
-            OR (REG(5) AND INT_MASKE(5))\r
-            OR (REG(6) AND INT_MASKE(6))\r
-            OR (REG(7) AND INT_MASKE(7));\r
-\r
-       process (PCI_CLOCK)\r
-       begin\r
-               if(PCI_CLOCK'event      and     PCI_CLOCK       =       '1')    then\r
-       SIG_PROPAGATE_INT_SECOND        <= not SIG_PROPAGATE_INT;\r
-    end if;\r
-  end process;\r
-\r
-\r
-         INTAn <= not SIG_PROPAGATE_INT_SECOND;\r
-       PCI_INTAn       <= '0'  when SIG_PROPAGATE_INT_SECOND = '0'     else    'Z';\r
-\r
-       INT_REG <= REG;\r
-\r
-end architecture INTERRUPT_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: INTERRUPT.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity INTERRUPT is
+       port
+       (
+       PCI_CLOCK               :in             std_logic;
+       PCI_RSTn                :in     std_logic; -- PCI reset is asynchron (low active)
+       RESET                           :in     std_logic;
+       TAST_SETn               :in     std_logic;
+       TAST_RESn               :in     std_logic;
+       INT_IN_0                :in             std_logic;
+       INT_IN_1                :in             std_logic;
+       INT_IN_2                :in             std_logic;
+       INT_IN_3                :in             std_logic;
+       INT_IN_4                :in             std_logic;
+       INT_IN_5                :in             std_logic;
+       INT_IN_6                :in             std_logic;
+       INT_IN_7                :in             std_logic;
+       TRDYn                           :in     std_logic;  -- event 1 after read of Interrupt status register (low active)
+       READ_XX5_4      :in     std_logic;      -- event 2 after read of Interrupt status register
+       INT_RES                 :in             std_logic_vector(7 downto 0); -- clear selected interrupts
+       INT_MASKE               :in             std_logic_vector(7 downto 0);   -- interrupt mask register
+       INT_REG                 :out    std_logic_vector(7 downto 0); -- interrupt status register
+       INTAn                           :out    std_logic;      -- second interrupt line for PCI analyzer
+       PCI_INTAn               :out    std_logic               -- PCI interrupt line 
+       );
+
+end entity INTERRUPT;
+
+architecture INTERRUPT_DESIGN of INTERRUPT is
+
+       signal  SIG_TAST_Q              :std_logic;
+       signal  SIG_TAST_Qn             :std_logic;
+
+
+       signal  SIG_INTA                        :std_logic; 
+
+       signal FF_A                     :std_logic_vector(7 downto 0);
+       signal FF_B                     :std_logic_vector(7 downto 0);  
+       signal SET                      :std_logic_vector(7 downto 0);  
+
+       signal  SIG_PROPAGATE_INT :std_logic;
+       signal  SIG_PROPAGATE_INT_SECOND :std_logic;
+       signal  REG :std_logic_vector(7 downto 0);
+
+begin
+
+
+
+
+------------------------------------------------------
+       process (PCI_CLOCK) 
+       begin 
+               if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  
+
+                        -- THIS IS BROKEN (it cycles the interrupt)
+                       SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);
+                       SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);
+       
+               end if;
+       end process;    
+
+------------------------------------------------------
+
+       process (PCI_CLOCK)
+       begin
+    if (PCI_RSTn = '0') then
+                                       SET <= "00000000";
+          FF_A <= "00000000";
+          FF_B <= "00000000";
+
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then
+               if(RESET = '1') then
+                                               SET <= "00000000";
+            FF_A       <= "00000000";
+            FF_B       <= "00000000";
+      else     
+
+                       FF_A(0) <=                      INT_IN_0 ;  -- Receive FIFO Empty Flag
+
+                       FF_A(1) <=                      INT_IN_1 ;  -- Send FIFO Half Full
+                       FF_A(2) <=                      INT_IN_2 ; 
+                       FF_A(3) <=                      INT_IN_3 ; 
+
+                       FF_A(4) <=                      INT_IN_4 ; 
+
+                       FF_A(5) <=                      INT_IN_5 ; 
+                       FF_A(6) <=                      INT_IN_6 ; 
+                       FF_A(7) <=                      INT_IN_7 ; 
+
+                       FF_B    <= FF_A ;
+
+                       SET <= FF_A AND not FF_B;
+               end if;
+               end if;
+       end process;
+
+       process (PCI_CLOCK,PCI_RSTn)
+       begin
+               if (PCI_RSTn = '0') then
+                       REG <= "00000000";
+
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then
+                               if(RESET = '1') then
+                                       REG <= "00000000";
+
+               -- elsif(SIG_TAST_Q = '1') then
+               --      REG <= "00000000" or SET;
+               
+
+        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
+            REG <= (REG AND NOT INT_RES) OR SET;
+        else
+            REG <= REG OR SET;
+        end if;
+    end if;
+       end process;
+
+       SIG_PROPAGATE_INT <=
+            (REG(0) AND INT_MASKE(0)) 
+            OR (REG(1) AND INT_MASKE(1))
+            OR (REG(2) AND INT_MASKE(2))
+            OR (REG(3) AND INT_MASKE(3))
+            OR (REG(4) AND INT_MASKE(4))
+            OR (REG(5) AND INT_MASKE(5))
+            OR (REG(6) AND INT_MASKE(6))
+            OR (REG(7) AND INT_MASKE(7));
+
+       process (PCI_CLOCK)
+       begin
+               if(PCI_CLOCK'event      and     PCI_CLOCK       =       '1')    then
+       SIG_PROPAGATE_INT_SECOND        <= not SIG_PROPAGATE_INT;
+    end if;
+  end process;
+
+
+         INTAn <= not SIG_PROPAGATE_INT_SECOND;
+       PCI_INTAn       <= '0'  when SIG_PROPAGATE_INT_SECOND = '0'     else    'Z';
+
+       INT_REG <= REG;
+
+end architecture INTERRUPT_DESIGN;
index 44419d8b181a5b63832fb4a90489a1276b202da8..283e4030d611d1fe0b70eef2231456a8adf951f1 100644 (file)
@@ -1,54 +1,54 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_WR_SEL.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity IO_WR_SEL is\r
-       port\r
-       (\r
-       IO_WR_COM               :in             std_logic;\r
-       IRDY_REGn               :in             std_logic;\r
-       TRDYn                           :in             std_logic;\r
-       ADDR_REG                :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
-       WRITE_XX1_0     :out    std_logic;\r
-       WRITE_XX3_2     :out    std_logic;\r
-       WRITE_XX5_4     :out    std_logic;\r
-       WRITE_XX7_6     :out    std_logic \r
-       );\r
-end entity IO_WR_SEL;\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
---     0011            AD 31..16\r
-\r
-architecture IO_WR_SEL_DESIGN of IO_WR_SEL is\r
-\r
-       signal  WR_ENA  :std_logic;\r
-       signal  ADDR            :std_logic_vector( 5 downto 0); \r
-\r
-begin\r
-\r
-               WR_ENA  <=      '1' when\r
-                                                                               IO_WR_COM = '1' and\r
-                                                                               IRDY_REGn       =       '0' and\r
-                                                                               TRDYn                   =       '0'     else    '0';\r
-\r
-\r
-               ADDR    <=       ADDR_REG(3) &  ADDR_REG(2)     &       CBE_REGn;\r
-\r
-\r
-               WRITE_XX1_0     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "001100"        else '0';        \r
-               WRITE_XX3_2     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "000011"        else '0';\r
-               WRITE_XX5_4     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "011100"        else '0';        \r
-               WRITE_XX7_6     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "010011"        else '0';\r
-       \r
-end architecture IO_WR_SEL_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_WR_SEL.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity IO_WR_SEL is
+       port
+       (
+       IO_WR_COM               :in             std_logic;
+       IRDY_REGn               :in             std_logic;
+       TRDYn                           :in             std_logic;
+       ADDR_REG                :in             std_logic_vector(31 downto 0);
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);
+       WRITE_XX1_0     :out    std_logic;
+       WRITE_XX3_2     :out    std_logic;
+       WRITE_XX5_4     :out    std_logic;
+       WRITE_XX7_6     :out    std_logic 
+       );
+end entity IO_WR_SEL;
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+--     0011            AD 31..16
+
+architecture IO_WR_SEL_DESIGN of IO_WR_SEL is
+
+       signal  WR_ENA  :std_logic;
+       signal  ADDR            :std_logic_vector( 5 downto 0); 
+
+begin
+
+               WR_ENA  <=      '1' when
+                                                                               IO_WR_COM = '1' and
+                                                                               IRDY_REGn       =       '0' and
+                                                                               TRDYn                   =       '0'     else    '0';
+
+
+               ADDR    <=       ADDR_REG(3) &  ADDR_REG(2)     &       CBE_REGn;
+
+
+               WRITE_XX1_0     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "001100"        else '0';        
+               WRITE_XX3_2     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "000011"        else '0';
+               WRITE_XX5_4     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "011100"        else '0';        
+               WRITE_XX7_6     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "010011"        else '0';
+       
+end architecture IO_WR_SEL_DESIGN;
index ba27f4a4395565b5dd89faf75f4fcc48a3742649..5c9537d508cca619a97dd32244a9802d06b602a3 100644 (file)
@@ -1,36 +1,36 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: IO_MUX.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity IO_MUX is\r
-       port\r
-       (\r
-       READ_SEL                        :in             std_logic_vector ( 1 downto 0);\r
-       USER_DATA                       :in             std_logic_vector (31 downto 0);\r
-       CONFIG_DATA             :in             std_logic_vector (31 downto 0);\r
-       PCI_AD                          :in             std_logic_vector (31 downto 0);\r
-       IO_DATA                         :out    std_logic_vector (31 downto 0)\r
-       );\r
-end entity IO_MUX;\r
-\r
-architecture IO_MUX_DESIGN of IO_MUX is\r
-\r
-       signal  MUX             :std_logic_vector (31 downto 0); \r
-\r
-begin \r
-\r
-       MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG \r
-                                       PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO\r
-                                       CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG \r
-                                       USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO      \r
-                                       CONFIG_DATA;\r
-\r
---                                     MUX;\r
-\r
-       IO_DATA <= MUX;\r
-\r
-end architecture IO_MUX_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity IO_MUX is
+       port
+       (
+       READ_SEL                        :in             std_logic_vector ( 1 downto 0);
+       USER_DATA                       :in             std_logic_vector (31 downto 0);
+       CONFIG_DATA             :in             std_logic_vector (31 downto 0);
+       PCI_AD                          :in             std_logic_vector (31 downto 0);
+       IO_DATA                         :out    std_logic_vector (31 downto 0)
+       );
+end entity IO_MUX;
+
+architecture IO_MUX_DESIGN of IO_MUX is
+
+       signal  MUX             :std_logic_vector (31 downto 0); 
+
+begin 
+
+       MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG 
+                                       PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO
+                                       CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG 
+                                       USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO      
+                                       CONFIG_DATA;
+
+--                                     MUX;
+
+       IO_DATA <= MUX;
+
+end architecture IO_MUX_DESIGN;
index f56df31169a6910ee33ee1f3aa217ddbd27b772f..8b50c2e7543159cf4bf8440f6743579475813fdf 100644 (file)
@@ -1,74 +1,74 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: IO_MUX.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity IO_REG is\r
-    port\r
-       (\r
-       PCI_CLOCK               :in             std_logic;\r
-       PCI_RSTn                :in             std_logic;\r
-       PCI_FRAMEn      :in             std_logic;\r
-       PCI_IRDYn               :in             std_logic;\r
-       PCI_IDSEL               :in             std_logic;\r
-       PCI_PAR                 :in             std_logic;\r
-       PCI_CBEn                :in             std_logic_vector ( 3 downto 0);\r
-       OE_PCI_AD               :in             std_logic;\r
-       IO_DATA                 :in             std_logic_vector (31 downto 0);\r
-       AD_REG                  :out    std_logic_vector (31 downto 0);\r
-       CBE_REGn                :out    std_logic_vector ( 3 downto 0);\r
-       FRAME_REGn      :out    std_logic;      \r
-       IRDY_REGn               :out    std_logic;      \r
-       IDSEL_REG               :out    std_logic;\r
-       PAR_REG                 :out    std_logic;              \r
-       PCI_AD                  :out    std_logic_vector (31 downto 0)  --      t/s\r
-    );\r
-end entity IO_REG;\r
-\r
-architecture IO_REG_DESIGN of IO_REG is\r
-\r
-       signal  REG_AD                  :std_logic_vector (31 downto 0); \r
-       signal  REG_CBEn                :std_logic_vector ( 3 downto 0);\r
-       signal  REG_FRAMEn      :std_logic;\r
-       signal  REG_IRDYn               :std_logic;\r
-       signal  REG_IDSEL               :std_logic;\r
-       signal  REG_PAR                 :std_logic;\r
-\r
-begin \r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then\r
-\r
-                       REG_AD                  <= X"00000000";\r
-                       REG_CBEn                <= "0000";\r
-                       REG_FRAMEn      <= '1';\r
-                       REG_IRDYn               <= '1';\r
-                       REG_IDSEL               <= '0';\r
-                       REG_PAR                 <= '0';\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       REG_AD                  <=      IO_DATA;\r
-                       REG_CBEn                <=      PCI_CBEn;\r
-                       REG_FRAMEn      <=      PCI_FRAMEn;\r
-                       REG_IRDYn               <=      PCI_IRDYn;\r
-                       REG_IDSEL               <=      PCI_IDSEL;\r
-                       REG_PAR                 <=      PCI_PAR;\r
-\r
-               end if;\r
-       end process;\r
-\r
-       PCI_AD                  <=      REG_AD when OE_PCI_AD ='1' else (others => 'Z');\r
-\r
-       AD_REG                  <=      REG_AD;\r
-       CBE_REGn                <=      REG_CBEn;\r
-       FRAME_REGn      <=      REG_FRAMEn;\r
-       IRDY_REGn               <=      REG_IRDYn;\r
-       IDSEL_REG               <=      REG_IDSEL;\r
-       PAR_REG                 <=      REG_PAR;\r
-\r
-end architecture IO_REG_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity IO_REG is
+    port
+       (
+       PCI_CLOCK               :in             std_logic;
+       PCI_RSTn                :in             std_logic;
+       PCI_FRAMEn      :in             std_logic;
+       PCI_IRDYn               :in             std_logic;
+       PCI_IDSEL               :in             std_logic;
+       PCI_PAR                 :in             std_logic;
+       PCI_CBEn                :in             std_logic_vector ( 3 downto 0);
+       OE_PCI_AD               :in             std_logic;
+       IO_DATA                 :in             std_logic_vector (31 downto 0);
+       AD_REG                  :out    std_logic_vector (31 downto 0);
+       CBE_REGn                :out    std_logic_vector ( 3 downto 0);
+       FRAME_REGn      :out    std_logic;      
+       IRDY_REGn               :out    std_logic;      
+       IDSEL_REG               :out    std_logic;
+       PAR_REG                 :out    std_logic;              
+       PCI_AD                  :out    std_logic_vector (31 downto 0)  --      t/s
+    );
+end entity IO_REG;
+
+architecture IO_REG_DESIGN of IO_REG is
+
+       signal  REG_AD                  :std_logic_vector (31 downto 0); 
+       signal  REG_CBEn                :std_logic_vector ( 3 downto 0);
+       signal  REG_FRAMEn      :std_logic;
+       signal  REG_IRDYn               :std_logic;
+       signal  REG_IDSEL               :std_logic;
+       signal  REG_PAR                 :std_logic;
+
+begin 
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then
+
+                       REG_AD                  <= X"00000000";
+                       REG_CBEn                <= "0000";
+                       REG_FRAMEn      <= '1';
+                       REG_IRDYn               <= '1';
+                       REG_IDSEL               <= '0';
+                       REG_PAR                 <= '0';
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       REG_AD                  <=      IO_DATA;
+                       REG_CBEn                <=      PCI_CBEn;
+                       REG_FRAMEn      <=      PCI_FRAMEn;
+                       REG_IRDYn               <=      PCI_IRDYn;
+                       REG_IDSEL               <=      PCI_IDSEL;
+                       REG_PAR                 <=      PCI_PAR;
+
+               end if;
+       end process;
+
+       PCI_AD                  <=      REG_AD when OE_PCI_AD ='1' else (others => 'Z');
+
+       AD_REG                  <=      REG_AD;
+       CBE_REGn                <=      REG_CBEn;
+       FRAME_REGn      <=      REG_FRAMEn;
+       IRDY_REGn               <=      REG_IRDYn;
+       IDSEL_REG               <=      REG_IDSEL;
+       PAR_REG                 <=      REG_PAR;
+
+end architecture IO_REG_DESIGN;
index dbe1f78354e6d36494688b7a3c342853d12f2f06..4476632a8d29d973cf50eb5d5a5ea6b72e132d65 100644 (file)
@@ -1,33 +1,33 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 29.08.2006\r
--- File: MESS_1_TB.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity MESS_1_TB is\r
-       port\r
-       (\r
-       KONST_1                         :in             std_logic;\r
-       PCI_IDSEL                       :in             std_logic;\r
-       DEVSELn                         :in             std_logic;\r
-       INTAn                                   :in             std_logic;\r
-       REG_OUT_XX7             :in             std_logic_vector(7 downto 0);\r
-       TB_PCI_IDSEL    :out    std_logic;\r
-       TB_DEVSELn              :out    std_logic;\r
-       TB_INTAn                        :out    std_logic\r
-       );\r
-end entity MESS_1_TB;\r
-\r
-architecture MESS_1_TB_DESIGN of MESS_1_TB is\r
\r
-begin\r
-\r
-       TB_PCI_IDSEL    <=      PCI_IDSEL       and     KONST_1;\r
-\r
-       TB_INTAn                        <=      INTAn                   and     KONST_1;                \r
-        \r
-       TB_DEVSELn              <=      DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));\r
-\r
-end architecture MESS_1_TB_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 29.08.2006
+-- File: MESS_1_TB.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity MESS_1_TB is
+       port
+       (
+       KONST_1                         :in             std_logic;
+       PCI_IDSEL                       :in             std_logic;
+       DEVSELn                         :in             std_logic;
+       INTAn                                   :in             std_logic;
+       REG_OUT_XX7             :in             std_logic_vector(7 downto 0);
+       TB_PCI_IDSEL    :out    std_logic;
+       TB_DEVSELn              :out    std_logic;
+       TB_INTAn                        :out    std_logic
+       );
+end entity MESS_1_TB;
+
+architecture MESS_1_TB_DESIGN of MESS_1_TB is
+begin
+
+       TB_PCI_IDSEL    <=      PCI_IDSEL       and     KONST_1;
+
+       TB_INTAn                        <=      INTAn                   and     KONST_1;                
+        
+       TB_DEVSELn              <=      DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
+
+end architecture MESS_1_TB_DESIGN;
index 9d78b2b1deba6732a9e8f437868c9a5e6eaa59d0..2544f682b1d4a3b7f9bb693273a0a93dbd2f02a8 100644 (file)
--- $Id: PAR_SER_CON.vhd,v 1.2 2007-03-10 16:08:48 michael Exp $\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-\r
-entity PAR_SER_CON     is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in     std_logic; \r
-       RESET                           :in     std_logic; \r
-       PSC_ENABLE                      :in     std_logic; -- Parallel Serial Converter Enable\r
-       SYNC_S_FIFO_EFn                 :in     std_logic; -- Empty Flag (low active)\r
-       SPC_RDY_IN                      :in     std_logic; -- Ready to receive data\r
-       PAR_IN                          :in     std_logic_vector(7 downto 0);\r
-       SER_OUT                         :out    std_logic; -- Serial Output\r
-       S_FIFO_READn                    :out    std_logic  -- FIFO Read (low active)\r
-       );                      \r
-end entity     PAR_SER_CON ;\r
-\r
-architecture PAR_SER_CON_DESIGN        of PAR_SER_CON is\r
-\r
-constant STATE_END        :std_logic_vector(3 downto 0) := "0001";\r
-constant STATE_SEND       :std_logic_vector(3 downto 0) := "0010";\r
-constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";\r
-constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";\r
-constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";\r
-constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";\r
-constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";\r
-constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";\r
-constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";\r
-constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";\r
-\r
-signal COUNT     :std_logic_vector (3 downto 0);\r
-signal STATE     :std_logic_vector (3 downto 0); \r
-signal DATUM     :std_logic_vector (7 downto 0);\r
-signal SYNC                     :std_logic; -- make SPC_RDY_IN stable\r
-\r
-attribute syn_state_machine:boolean;\r
-attribute syn_state_machine of STATE: signal is false;\r
-attribute syn_state_machine of COUNT: signal is false;\r
-begin\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                       if ("0000" < COUNT) then\r
-                                               COUNT <= COUNT - 1;\r
-                                       end if;\r
-\r
-                if (RESET = '1') then\r
-                        STATE <= STATE_SEND;\r
-                        COUNT <= "0000";\r
-                        SER_OUT <= '0';\r
-                        S_FIFO_READn <= '1';\r
-\r
-                elsif (PSC_ENABLE = '1') then\r
-               if (COUNT = "0000") then\r
-                        COUNT <= "0011";\r
-                        case STATE is\r
-                                when STATE_SEND =>\r
-                                        if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then\r
-                                                SER_OUT <= '1';\r
-                                                S_FIFO_READn <= '0';\r
-                                                STATE <= STATE_SEND_BIT_0;\r
-                                        end if;\r
-\r
-                                when STATE_SEND_BIT_0 =>\r
-                                                DATUM     <= PAR_IN;\r
-                                                S_FIFO_READn <= '1';\r
-                                                SER_OUT <= PAR_IN(0); \r
-                                                STATE <= STATE_SEND_BIT_1;\r
-                                  \r
-                                when STATE_SEND_BIT_1 =>\r
-                                        SER_OUT <= DATUM(1); \r
-                                        STATE <= STATE_SEND_BIT_2;\r
-\r
-                                when STATE_SEND_BIT_2 =>\r
-                                        SER_OUT <= DATUM(2); \r
-                                        STATE <= STATE_SEND_BIT_3;\r
-\r
-                                when STATE_SEND_BIT_3 =>\r
-                                        SER_OUT <= DATUM(3); \r
-                                        STATE <= STATE_SEND_BIT_4;\r
-\r
-                                when STATE_SEND_BIT_4 =>\r
-                                        SER_OUT <= DATUM(4); \r
-                                        STATE <= STATE_SEND_BIT_5;\r
-                                        \r
-                                when STATE_SEND_BIT_5 =>\r
-                                        SER_OUT <= DATUM(5); \r
-                                        STATE <= STATE_SEND_BIT_6;\r
-\r
-                                when STATE_SEND_BIT_6 =>\r
-                                        SER_OUT <= DATUM(6); \r
-                                        STATE <= STATE_SEND_BIT_7;\r
-                                        \r
-                                when STATE_SEND_BIT_7 =>\r
-                                        SER_OUT <= DATUM(7); \r
-                                        STATE <= STATE_END;\r
-\r
-                                when STATE_END =>\r
-                                        SER_OUT <= '0';\r
-                                        STATE <= STATE_SEND;\r
-\r
-                                when others => STATE <= STATE_END;\r
-                        end case;\r
-                   else\r
-                       S_FIFO_READn <= '1';\r
-                    end if; -- COUNT\r
-                end if; -- RESET ... / PSC_ENABLE ...\r
-        end if; -- PCI_CLOCK ...\r
-end process;\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                               SYNC <= SPC_RDY_IN;\r
-                               end if;\r
-end process;\r
-\r
-\r
-end architecture PAR_SER_CON_DESIGN;\r
+-- $Id: PAR_SER_CON.vhd,v 1.3 2007-03-11 08:04:56 sithglan Exp $
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity PAR_SER_CON     is
+       port
+       (
+       PCI_CLOCK               :in     std_logic; 
+       RESET                           :in     std_logic; 
+       PSC_ENABLE                      :in     std_logic; -- Parallel Serial Converter Enable
+       SYNC_S_FIFO_EFn                 :in     std_logic; -- Empty Flag (low active)
+       SPC_RDY_IN                      :in     std_logic; -- Ready to receive data
+       PAR_IN                          :in     std_logic_vector(7 downto 0);
+       SER_OUT                         :out    std_logic; -- Serial Output
+       S_FIFO_READn                    :out    std_logic  -- FIFO Read (low active)
+       );                      
+end entity     PAR_SER_CON ;
+
+architecture PAR_SER_CON_DESIGN        of PAR_SER_CON is
+
+constant STATE_END        :std_logic_vector(3 downto 0) := "0001";
+constant STATE_SEND       :std_logic_vector(3 downto 0) := "0010";
+constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";
+constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";
+constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";
+constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";
+constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";
+constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";
+constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";
+constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";
+
+signal COUNT     :std_logic_vector (3 downto 0);
+signal STATE     :std_logic_vector (3 downto 0); 
+signal DATUM     :std_logic_vector (7 downto 0);
+signal SYNC                     :std_logic; -- make SPC_RDY_IN stable
+
+attribute syn_state_machine:boolean;
+attribute syn_state_machine of STATE: signal is false;
+attribute syn_state_machine of COUNT: signal is false;
+begin
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                       if ("0000" < COUNT) then
+                                               COUNT <= COUNT - 1;
+                                       end if;
+
+                if (RESET = '1') then
+                        STATE <= STATE_SEND;
+                        COUNT <= "0000";
+                        SER_OUT <= '0';
+                        S_FIFO_READn <= '1';
+
+                elsif (PSC_ENABLE = '1') then
+               if (COUNT = "0000") then
+                        COUNT <= "0011";
+                        case STATE is
+                                when STATE_SEND =>
+                                        if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then
+                                                SER_OUT <= '1';
+                                                S_FIFO_READn <= '0';
+                                                STATE <= STATE_SEND_BIT_0;
+                                        end if;
+
+                                when STATE_SEND_BIT_0 =>
+                                                DATUM     <= PAR_IN;
+                                                S_FIFO_READn <= '1';
+                                                SER_OUT <= PAR_IN(0); 
+                                                STATE <= STATE_SEND_BIT_1;
+                                  
+                                when STATE_SEND_BIT_1 =>
+                                        SER_OUT <= DATUM(1); 
+                                        STATE <= STATE_SEND_BIT_2;
+
+                                when STATE_SEND_BIT_2 =>
+                                        SER_OUT <= DATUM(2); 
+                                        STATE <= STATE_SEND_BIT_3;
+
+                                when STATE_SEND_BIT_3 =>
+                                        SER_OUT <= DATUM(3); 
+                                        STATE <= STATE_SEND_BIT_4;
+
+                                when STATE_SEND_BIT_4 =>
+                                        SER_OUT <= DATUM(4); 
+                                        STATE <= STATE_SEND_BIT_5;
+                                        
+                                when STATE_SEND_BIT_5 =>
+                                        SER_OUT <= DATUM(5); 
+                                        STATE <= STATE_SEND_BIT_6;
+
+                                when STATE_SEND_BIT_6 =>
+                                        SER_OUT <= DATUM(6); 
+                                        STATE <= STATE_SEND_BIT_7;
+                                        
+                                when STATE_SEND_BIT_7 =>
+                                        SER_OUT <= DATUM(7); 
+                                        STATE <= STATE_END;
+
+                                when STATE_END =>
+                                        SER_OUT <= '0';
+                                        STATE <= STATE_SEND;
+
+                                when others => STATE <= STATE_END;
+                        end case;
+                   else
+                       S_FIFO_READn <= '1';
+                    end if; -- COUNT
+                end if; -- RESET ... / PSC_ENABLE ...
+        end if; -- PCI_CLOCK ...
+end process;
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                               SYNC <= SPC_RDY_IN;
+                               end if;
+end process;
+
+
+end architecture PAR_SER_CON_DESIGN;
index 768816038e74c2d2dde11280e46f8cdd43be63da..4f06bd623c9203b7d6accd0df6e0508e546fdf3d 100644 (file)
@@ -1,23 +1,23 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: PARITY_4.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity PARITY_4 is\r
-       port\r
-       (\r
-       PAR_IN  :in             std_logic_vector(3 downto 0);   \r
-       PAR_OUT :out    std_logic\r
-       );\r
-end entity PARITY_4 ; \r
-\r
-architecture PARITY_4_DESIGN of PARITY_4 is\r
-\r
-begin\r
-\r
-       PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;\r
-\r
-end architecture PARITY_4_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: PARITY_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity PARITY_4 is
+       port
+       (
+       PAR_IN  :in             std_logic_vector(3 downto 0);   
+       PAR_OUT :out    std_logic
+       );
+end entity PARITY_4 ; 
+
+architecture PARITY_4_DESIGN of PARITY_4 is
+
+begin
+
+       PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;
+
+end architecture PARITY_4_DESIGN;
index 0c91d25e33050060b1e9cbe122a01c1e839f73c7..10a25a8268f6885cff15c86fd5867be7cd5c25d7 100644 (file)
@@ -1,38 +1,38 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: REG.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity REG is\r
-       port\r
-       (\r
-       CLOCK           :in             std_logic; \r
-       RESET           :in             std_logic; \r
-       WRITE           :in             std_logic;   \r
-       REG_IN  :in             std_logic_vector(7 downto 0);\r
-       REG_OUT :out    std_logic_vector(7 downto 0) \r
-       );\r
-end entity REG ;\r
-\r
-architecture REG_DESIGN of REG is\r
-\r
-       signal SIG_REG  :std_logic_vector (7 downto 0);\r
-\r
-begin\r
-\r
-       process (CLOCK) \r
-       begin\r
-               if (CLOCK'event and CLOCK = '1') then\r
-                       if                      RESET   =       '1'     then    SIG_REG <= X"00";\r
-                               elsif   WRITE   =       '1'     then    SIG_REG <= REG_IN;\r
-                               else                                                                            SIG_REG <= SIG_REG;\r
-               end if;\r
-               end if;\r
-       end process;\r
-\r
-       REG_OUT <= SIG_REG;\r
-\r
-end architecture REG_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: REG.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity REG is
+       port
+       (
+       CLOCK           :in             std_logic; 
+       RESET           :in             std_logic; 
+       WRITE           :in             std_logic;   
+       REG_IN  :in             std_logic_vector(7 downto 0);
+       REG_OUT :out    std_logic_vector(7 downto 0) 
+       );
+end entity REG ;
+
+architecture REG_DESIGN of REG is
+
+       signal SIG_REG  :std_logic_vector (7 downto 0);
+
+begin
+
+       process (CLOCK) 
+       begin
+               if (CLOCK'event and CLOCK = '1') then
+                       if                      RESET   =       '1'     then    SIG_REG <= X"00";
+                               elsif   WRITE   =       '1'     then    SIG_REG <= REG_IN;
+                               else                                                                            SIG_REG <= SIG_REG;
+               end if;
+               end if;
+       end process;
+
+       REG_OUT <= SIG_REG;
+
+end architecture REG_DESIGN;
index a030eaa6a63775e4e9690075e524be0819610419..a6a2606a6db5f71fe2b9fc61676c54ab66b5a5fe 100644 (file)
--- $Id: SER_PAR_CON.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-\r
-entity SER_PAR_CON is\r
-       port\r
-       (\r
-       PCI_CLOCK                       :in     std_logic; \r
-       RESET                           :in     std_logic; \r
-       SPC_ENABLE                      :in     std_logic; -- Driver Enable Sender/Receiver\r
-       SYNC_R_FIFO_FFn                 :in     std_logic; -- FIFO Full Flag (low active)\r
-       SERIAL_IN                       :in     std_logic; -- Serial Input\r
-       R_FIFO_WRITEn                   :out    std_logic; -- FIFO Write (low active)\r
-       SPC_RDY_OUT                     :out    std_logic; -- Ready to Receive Data\r
-       PAR_OUT                         :out    std_logic_vector(7 downto 0)\r
-       );\r
-end entity SER_PAR_CON ;\r
-\r
-\r
-architecture SER_PAR_CON_DESIGN of SER_PAR_CON is\r
-\r
--- constant STATE_RECV            :std_logic_vector(3 downto 0) := "0001";\r
-constant STATE_RECV_START_BIT  :std_logic_vector(3 downto 0) := "0010";\r
-constant STATE_RECV_BIT_0      :std_logic_vector(3 downto 0) := "0011";\r
-constant STATE_RECV_BIT_1      :std_logic_vector(3 downto 0) := "0100";\r
-constant STATE_RECV_BIT_2      :std_logic_vector(3 downto 0) := "0101";\r
-constant STATE_RECV_BIT_3      :std_logic_vector(3 downto 0) := "0110";\r
-constant STATE_RECV_BIT_4      :std_logic_vector(3 downto 0) := "0111";\r
-constant STATE_RECV_BIT_5      :std_logic_vector(3 downto 0) := "1000";\r
-constant STATE_RECV_BIT_6      :std_logic_vector(3 downto 0) := "1001";\r
-constant STATE_RECV_BIT_7      :std_logic_vector(3 downto 0) := "1010";\r
-constant STATE_RECV_FIFOFULL   :std_logic_vector(3 downto 0) := "1011";\r
-\r
-signal COUNT     :std_logic_vector (3 downto 0);\r
-signal STATE     :std_logic_vector (3 downto 0);\r
-signal STARTBIT  :std_logic_vector (3 downto 0);\r
-\r
-\r
-attribute syn_state_machine:boolean;\r
-attribute syn_state_machine of STATE: signal is false;\r
-attribute syn_state_machine of COUNT: signal is false;\r
-\r
-begin\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                               if ("0000" < COUNT) then\r
-                                               COUNT <= COUNT - 1;\r
-                                       end if;\r
-\r
--- war nicht das Problem des Datenverlusts\r
---        if (R_FIFO_WRITEn = '0' and COUNT = "0000") then\r
---            R_FIFO_WRITEn <= '1';\r
----      end if;\r
-\r
-                if (RESET = '1') then\r
-                        STATE <= STATE_RECV_START_BIT;\r
-                        COUNT <= "0000";\r
-                        R_FIFO_WRITEn <= '1';\r
-\r
-                elsif (SPC_ENABLE = '1') then\r
-                       \r
-                                                                                        if (STATE = STATE_RECV_START_BIT) then\r
-                              R_FIFO_WRITEn <= '1';\r
-                                                                                               if (STARTBIT = "0011") then\r
-                                                                                                                               COUNT <= "0011";\r
-                                   STATE <= STATE_RECV_BIT_0;\r
-                              end if;\r
-\r
-                       elsif (STATE = STATE_RECV_FIFOFULL) then\r
-                              if (SYNC_R_FIFO_FFn = '1') then\r
-                                      R_FIFO_WRITEn <= '0';\r
-                                      STATE <= STATE_RECV_START_BIT;\r
-                              end if;\r
-\r
-                       elsif (COUNT = "0000") then\r
-                        COUNT <= "0011";\r
-                        case STATE is\r
-                                                                                                                               \r
-                                when STATE_RECV_BIT_0 =>\r
-                                        PAR_OUT(0) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_1;\r
-\r
-                                when STATE_RECV_BIT_1 =>\r
-                                        PAR_OUT(1) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_2;\r
-                                        \r
-                                when STATE_RECV_BIT_2 =>\r
-                                        PAR_OUT(2) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_3;\r
-                                        \r
-                                when STATE_RECV_BIT_3 =>\r
-                                        PAR_OUT(3) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_4;\r
-                                        \r
-                                when STATE_RECV_BIT_4 =>\r
-                                        PAR_OUT(4) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_5;\r
-                                        \r
-                                when STATE_RECV_BIT_5 =>\r
-                                        PAR_OUT(5) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_6;\r
-                                        \r
-                                when STATE_RECV_BIT_6 =>\r
-                                        PAR_OUT(6) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_7;\r
-                                        \r
-                                when STATE_RECV_BIT_7 =>\r
-                                        PAR_OUT(7) <= STARTBIT(0);\r
-\r
-                                        if (SYNC_R_FIFO_FFn = '1') then\r
-                                             STATE <= STATE_RECV_START_BIT;\r
-                                             R_FIFO_WRITEn <= '0';\r
-                                        else \r
-                                             STATE <= STATE_RECV_FIFOFULL;\r
-                                        end if;\r
-\r
-                                                                                                                               when others =>\r
-                                                                                                                                                               STATE <= STATE_RECV_START_BIT;\r
-\r
-                        end case;\r
-                     end if; -- COUNT\r
-                end if; -- RESET ... / SPC_ENABLE ...\r
-        end if; -- PCI_CLOCK ...\r
-end process;\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-               if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-      SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;\r
-               end if;\r
-end process;\r
-\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                       if (RESET = '1') then\r
-                                               STARTBIT <= "0000";\r
-                                       else\r
-                                       STARTBIT(0) <= SERIAL_IN;\r
-                                       STARTBIT(1) <= STARTBIT(0);\r
-                                       STARTBIT(2) <= STARTBIT(1);\r
-                                       STARTBIT(3) <= STARTBIT(2);\r
-                                       end if;                           \r
-                       end if;\r
-end process;\r
-\r
-\r
-\r
-end architecture SER_PAR_CON_DESIGN;\r
+-- $Id: SER_PAR_CON.vhd,v 1.2 2007-03-11 08:04:56 sithglan Exp $
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity SER_PAR_CON is
+       port
+       (
+       PCI_CLOCK                       :in     std_logic; 
+       RESET                           :in     std_logic; 
+       SPC_ENABLE                      :in     std_logic; -- Driver Enable Sender/Receiver
+       SYNC_R_FIFO_FFn                 :in     std_logic; -- FIFO Full Flag (low active)
+       SERIAL_IN                       :in     std_logic; -- Serial Input
+       R_FIFO_WRITEn                   :out    std_logic; -- FIFO Write (low active)
+       SPC_RDY_OUT                     :out    std_logic; -- Ready to Receive Data
+       PAR_OUT                         :out    std_logic_vector(7 downto 0)
+       );
+end entity SER_PAR_CON ;
+
+
+architecture SER_PAR_CON_DESIGN of SER_PAR_CON is
+
+-- constant STATE_RECV            :std_logic_vector(3 downto 0) := "0001";
+constant STATE_RECV_START_BIT  :std_logic_vector(3 downto 0) := "0010";
+constant STATE_RECV_BIT_0      :std_logic_vector(3 downto 0) := "0011";
+constant STATE_RECV_BIT_1      :std_logic_vector(3 downto 0) := "0100";
+constant STATE_RECV_BIT_2      :std_logic_vector(3 downto 0) := "0101";
+constant STATE_RECV_BIT_3      :std_logic_vector(3 downto 0) := "0110";
+constant STATE_RECV_BIT_4      :std_logic_vector(3 downto 0) := "0111";
+constant STATE_RECV_BIT_5      :std_logic_vector(3 downto 0) := "1000";
+constant STATE_RECV_BIT_6      :std_logic_vector(3 downto 0) := "1001";
+constant STATE_RECV_BIT_7      :std_logic_vector(3 downto 0) := "1010";
+constant STATE_RECV_FIFOFULL   :std_logic_vector(3 downto 0) := "1011";
+
+signal COUNT     :std_logic_vector (3 downto 0);
+signal STATE     :std_logic_vector (3 downto 0);
+signal STARTBIT  :std_logic_vector (3 downto 0);
+
+
+attribute syn_state_machine:boolean;
+attribute syn_state_machine of STATE: signal is false;
+attribute syn_state_machine of COUNT: signal is false;
+
+begin
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                               if ("0000" < COUNT) then
+                                               COUNT <= COUNT - 1;
+                                       end if;
+
+-- war nicht das Problem des Datenverlusts
+--        if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
+--            R_FIFO_WRITEn <= '1';
+---      end if;
+
+                if (RESET = '1') then
+                        STATE <= STATE_RECV_START_BIT;
+                        COUNT <= "0000";
+                        R_FIFO_WRITEn <= '1';
+
+                elsif (SPC_ENABLE = '1') then
+                       
+                                                                                        if (STATE = STATE_RECV_START_BIT) then
+                              R_FIFO_WRITEn <= '1';
+                                                                                               if (STARTBIT = "0011") then
+                                                                                                                               COUNT <= "0011";
+                                   STATE <= STATE_RECV_BIT_0;
+                              end if;
+
+                       elsif (STATE = STATE_RECV_FIFOFULL) then
+                              if (SYNC_R_FIFO_FFn = '1') then
+                                      R_FIFO_WRITEn <= '0';
+                                      STATE <= STATE_RECV_START_BIT;
+                              end if;
+
+                       elsif (COUNT = "0000") then
+                        COUNT <= "0011";
+                        case STATE is
+                                                                                                                               
+                                when STATE_RECV_BIT_0 =>
+                                        PAR_OUT(0) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_1;
+
+                                when STATE_RECV_BIT_1 =>
+                                        PAR_OUT(1) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_2;
+                                        
+                                when STATE_RECV_BIT_2 =>
+                                        PAR_OUT(2) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_3;
+                                        
+                                when STATE_RECV_BIT_3 =>
+                                        PAR_OUT(3) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_4;
+                                        
+                                when STATE_RECV_BIT_4 =>
+                                        PAR_OUT(4) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_5;
+                                        
+                                when STATE_RECV_BIT_5 =>
+                                        PAR_OUT(5) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_6;
+                                        
+                                when STATE_RECV_BIT_6 =>
+                                        PAR_OUT(6) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_7;
+                                        
+                                when STATE_RECV_BIT_7 =>
+                                        PAR_OUT(7) <= STARTBIT(0);
+
+                                        if (SYNC_R_FIFO_FFn = '1') then
+                                             STATE <= STATE_RECV_START_BIT;
+                                             R_FIFO_WRITEn <= '0';
+                                        else 
+                                             STATE <= STATE_RECV_FIFOFULL;
+                                        end if;
+
+                                                                                                                               when others =>
+                                                                                                                                                               STATE <= STATE_RECV_START_BIT;
+
+                        end case;
+                     end if; -- COUNT
+                end if; -- RESET ... / SPC_ENABLE ...
+        end if; -- PCI_CLOCK ...
+end process;
+
+process(PCI_CLOCK)
+begin
+               if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+      SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
+               end if;
+end process;
+
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                       if (RESET = '1') then
+                                               STARTBIT <= "0000";
+                                       else
+                                       STARTBIT(0) <= SERIAL_IN;
+                                       STARTBIT(1) <= STARTBIT(0);
+                                       STARTBIT(2) <= STARTBIT(1);
+                                       STARTBIT(3) <= STARTBIT(2);
+                                       end if;                           
+                       end if;
+end process;
+
+
+
+end architecture SER_PAR_CON_DESIGN;
index 39d51acc147504371f2b2156232c049cf4107a74..94aa714cee8b6e863dbaf10f7e27899a6eff6f95 100644 (file)
@@ -1,31 +1,31 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_2.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity VERG_2  is\r
-       port\r
-       (\r
-       IN_A            :in             std_logic_vector(1 downto 0);\r
-       IN_B            :in             std_logic_vector(1 downto 0);\r
-       GLEICH  :out    std_logic\r
-       );\r
-end entity VERG_2 ;\r
-\r
-architecture VERG_2_DESIGN of VERG_2 is\r
-\r
-begin\r
-\r
-       process (IN_A,IN_B) \r
-       begin \r
-\r
-               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
-                       else                                                                                    GLEICH  <=      '0';   \r
-               end if;\r
-\r
-       end process;\r
-\r
-end architecture VERG_2_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_2.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity VERG_2  is
+       port
+       (
+       IN_A            :in             std_logic_vector(1 downto 0);
+       IN_B            :in             std_logic_vector(1 downto 0);
+       GLEICH  :out    std_logic
+       );
+end entity VERG_2 ;
+
+architecture VERG_2_DESIGN of VERG_2 is
+
+begin
+
+       process (IN_A,IN_B) 
+       begin 
+
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
+                       else                                                                                    GLEICH  <=      '0';   
+               end if;
+
+       end process;
+
+end architecture VERG_2_DESIGN ;
index 6aafdad19588f8994e3f138db2439a959cf02e4c..e3900cf4e2703a75d638ea7fcf679d72332c6155 100644 (file)
@@ -1,32 +1,32 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_4.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity VERG_4 is\r
-       port\r
-       (\r
-       IN_A            :in             std_logic_vector(3 downto 0);\r
-       IN_B            :in             std_logic_vector(3 downto 0);\r
-       GLEICH  :out    std_logic\r
-       );\r
-end entity VERG_4 ;\r
-\r
-architecture VERG_4_DESIGN of VERG_4 is\r
-\r
-begin\r
-\r
-       process (IN_A,IN_B) \r
-       begin \r
-\r
-               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
-                       else                                                                                    GLEICH  <=      '0';   \r
-               end if;\r
-\r
-       end process;\r
-\r
-end architecture VERG_4_DESIGN;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_4 is
+       port
+       (
+       IN_A            :in             std_logic_vector(3 downto 0);
+       IN_B            :in             std_logic_vector(3 downto 0);
+       GLEICH  :out    std_logic
+       );
+end entity VERG_4 ;
+
+architecture VERG_4_DESIGN of VERG_4 is
+
+begin
+
+       process (IN_A,IN_B) 
+       begin 
+
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
+                       else                                                                                    GLEICH  <=      '0';   
+               end if;
+
+       end process;
+
+end architecture VERG_4_DESIGN;
+
index 0346aebac03047add609be4c693b09e5db7d3f10..a0c6ea4fe7775d1e378f8f6b36aab9edd29ab1a2 100644 (file)
@@ -1,28 +1,28 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_00H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_00H is\r
-       port\r
-       (\r
-       VENDOR_ID                       :in             std_logic_vector (15 downto 0);\r
-       CONF_DATA_00H   :out    std_logic_vector (31 downto 0)\r
-       );\r
-end entity CONFIG_00H;\r
-\r
-architecture CONFIG_00H_DESIGN of CONFIG_00H is\r
-\r
--- PCI Configuration Space Header Addr : HEX 00 --\r
-\r
-       constant        CONF_DEVICE_ID          :std_logic_vector(31 downto 16) := X"AFFE";--???? \r
---constant     CONF_VENDOR_ID          :std_logic_vector(15 downto  0) := X"BAFF";--???? \r
-\r
-begin\r
-\r
-       CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;\r
-\r
-end architecture CONFIG_00H_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_00H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_00H is
+       port
+       (
+       VENDOR_ID                       :in             std_logic_vector (15 downto 0);
+       CONF_DATA_00H   :out    std_logic_vector (31 downto 0)
+       );
+end entity CONFIG_00H;
+
+architecture CONFIG_00H_DESIGN of CONFIG_00H is
+
+-- PCI Configuration Space Header Addr : HEX 00 --
+
+       constant        CONF_DEVICE_ID          :std_logic_vector(31 downto 16) := X"AFFE";--???? 
+--constant     CONF_VENDOR_ID          :std_logic_vector(15 downto  0) := X"BAFF";--???? 
+
+begin
+
+       CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
+
+end architecture CONFIG_00H_DESIGN;
index 2dbacf1152e66ecce76eb09a6c3f01adbfec3328..906a9ca21f65244d6d8488cfe3e0256b82578c71 100644 (file)
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_04H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_04H is\r
-       port\r
-       (\r
-       PCI_CLOCK                       :in             std_logic;\r
-       PCI_RSTn                        :in             std_logic;\r
-       SERR                                    :in             std_logic;\r
-       PERR                                    :in             std_logic;\r
-       AD_REG                          :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                        :in             std_logic_vector( 3 downto 0);\r
-       CONF_WR_04H             :in             std_logic;\r
-       CONF_DATA_04H   :out    std_logic_vector(31 downto 0)\r
-       );\r
-end entity CONFIG_04H;\r
-\r
-architecture CONFIG_04H_DESIGN of CONFIG_04H is\r
-\r
-       signal          CONF_STATUS             :std_logic_vector(31 downto 16);\r
-       signal          CONF_COMMAND    :std_logic_vector(15 downto  0);\r
-\r
-\r
-begin\r
-\r
---*******************************************************************\r
---************* PCI Configuration Space Header "STATUS" *************\r
---*******************************************************************\r
-\r
-       CONF_STATUS(20 downto 16)       <= "00000"      ;-- Reserved\r
-       CONF_STATUS(21          )       <= '0'                  ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz\r
-       CONF_STATUS(22                                  )       <= '0'                  ;-- MAS/TAR: "R_O" \r
-       CONF_STATUS(23          )       <= '0'                  ;-- ???/???: "R_O" : fast back-to-back\r
-       CONF_STATUS(24          )       <= '0'                  ;-- Master :\r
---CONF_STATUS(26 downto 25)    <= "00"                 ;-- Mas/Tar: "R_O" : timing fast   for "DEVSEL"\r
-       CONF_STATUS(26 downto 25)       <= "01"                 ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"\r
---CONF_STATUS(26 downto 25)    <= "10"                 ;-- Mas/Tar: "R_O" : timing slow   for "DEVSEL"\r
---CONF_STATUS(26 downto 25)    <= "11"                 ;-- Mas/Tar: "R_O" : reserved\r
-       CONF_STATUS(27          )       <= '0'                  ;-- Target : "R_W" : Taget-Abort\r
-       CONF_STATUS(28                                  )       <= '0'                  ;-- Master : "R_W" : Taget-Abort\r
-       CONF_STATUS(29          )       <= '0'                  ;-- Master : "R_W" : Master-Abort\r
---CONF_STATUS(30                                       )       <= SERR                 ;-- Mas/Tar: "R_W" : SERR\r
---CONF_STATUS(31                                       )       <= PERR                 ;-- Mas/Tar: "R_W" : PERR\r
-\r
-       process (PCI_CLOCK,PCI_RSTn) \r
-       begin\r
-               if PCI_RSTn = '0' then  CONF_STATUS(30) <= '0';\r
-                                                                                                               CONF_STATUS(31) <= '0';\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       if                      CONF_WR_04H     = '1' and CBE_REGn(3) = '0' then \r
-\r
-                                                       CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); \r
-                                                       CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));\r
-\r
-                               else    CONF_STATUS(30) <= SERR or CONF_STATUS(30);\r
-                                                       CONF_STATUS(31) <= PERR or CONF_STATUS(31);\r
-\r
-                       end if; \r
-               end if; \r
-       end process;\r
-\r
---*******************************************************************\r
---*********** PCI Configuration Space Header "COMMAND" **************\r
---*******************************************************************\r
-\r
---     CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???\r
---     CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???\r
---     CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus \r
---     CONF_COMMAND( 3) <= '0';-- Special Cycle ???\r
---     CONF_COMMAND( 4) <= '0';-- Master ??? \r
---     CONF_COMMAND( 5) <= '0';-- VGA    ???\r
---     CONF_COMMAND( 6) <= '0';-- Party checking enable/disable\r
-               CONF_COMMAND( 7) <= '0';-- address/data stepping ???\r
---     CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"\r
---     CONF_COMMAND( 9) <= '0';-- fast back-to-back\r
---     CONF_COMMAND(10) <= '0';-- Reserved\r
---     CONF_COMMAND(11) <= '0';-- Reserved\r
---     CONF_COMMAND(12) <= '0';-- Reserved\r
---     CONF_COMMAND(13) <= '0';-- Reserved\r
---     CONF_COMMAND(14) <= '0';-- Reserved\r
---     CONF_COMMAND(15) <= '0';-- Reserved\r
-\r
-       process (PCI_CLOCK,PCI_RSTn) \r
-       begin\r
-               if PCI_RSTn = '0' then  CONF_COMMAND(15 downto 8) <= (others =>'0');\r
-                                                                                                               CONF_COMMAND( 6 downto 0) <= (others =>'0');\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       if              CONF_WR_04H      = '1'and CBE_REGn(1) = '0' then \r
-\r
-                                                       CONF_COMMAND(15 downto 8)       <=                              AD_REG(15 downto 8);\r
-                               else    CONF_COMMAND(15 downto 8)       <=      CONF_COMMAND(15 downto 8);\r
-                       end if;\r
-\r
-\r
-                       if              CONF_WR_04H      = '1'and CBE_REGn(0) = '0' then \r
-\r
-                                                       CONF_COMMAND( 6 downto 0) <=                            AD_REG( 6 downto 0);\r
-                               else    CONF_COMMAND( 6 downto 0) <=    CONF_COMMAND( 6 downto 0);\r
-                       end if;\r
-\r
-               end if;\r
-       end process;\r
-\r
-       CONF_DATA_04H   <= CONF_STATUS & CONF_COMMAND;  \r
-\r
-end architecture CONFIG_04H_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_04H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_04H is
+       port
+       (
+       PCI_CLOCK                       :in             std_logic;
+       PCI_RSTn                        :in             std_logic;
+       SERR                                    :in             std_logic;
+       PERR                                    :in             std_logic;
+       AD_REG                          :in             std_logic_vector(31 downto 0);
+       CBE_REGn                        :in             std_logic_vector( 3 downto 0);
+       CONF_WR_04H             :in             std_logic;
+       CONF_DATA_04H   :out    std_logic_vector(31 downto 0)
+       );
+end entity CONFIG_04H;
+
+architecture CONFIG_04H_DESIGN of CONFIG_04H is
+
+       signal          CONF_STATUS             :std_logic_vector(31 downto 16);
+       signal          CONF_COMMAND    :std_logic_vector(15 downto  0);
+
+
+begin
+
+--*******************************************************************
+--************* PCI Configuration Space Header "STATUS" *************
+--*******************************************************************
+
+       CONF_STATUS(20 downto 16)       <= "00000"      ;-- Reserved
+       CONF_STATUS(21          )       <= '0'                  ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
+       CONF_STATUS(22                                  )       <= '0'                  ;-- MAS/TAR: "R_O" 
+       CONF_STATUS(23          )       <= '0'                  ;-- ???/???: "R_O" : fast back-to-back
+       CONF_STATUS(24          )       <= '0'                  ;-- Master :
+--CONF_STATUS(26 downto 25)    <= "00"                 ;-- Mas/Tar: "R_O" : timing fast   for "DEVSEL"
+       CONF_STATUS(26 downto 25)       <= "01"                 ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
+--CONF_STATUS(26 downto 25)    <= "10"                 ;-- Mas/Tar: "R_O" : timing slow   for "DEVSEL"
+--CONF_STATUS(26 downto 25)    <= "11"                 ;-- Mas/Tar: "R_O" : reserved
+       CONF_STATUS(27          )       <= '0'                  ;-- Target : "R_W" : Taget-Abort
+       CONF_STATUS(28                                  )       <= '0'                  ;-- Master : "R_W" : Taget-Abort
+       CONF_STATUS(29          )       <= '0'                  ;-- Master : "R_W" : Master-Abort
+--CONF_STATUS(30                                       )       <= SERR                 ;-- Mas/Tar: "R_W" : SERR
+--CONF_STATUS(31                                       )       <= PERR                 ;-- Mas/Tar: "R_W" : PERR
+
+       process (PCI_CLOCK,PCI_RSTn) 
+       begin
+               if PCI_RSTn = '0' then  CONF_STATUS(30) <= '0';
+                                                                                                               CONF_STATUS(31) <= '0';
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       if                      CONF_WR_04H     = '1' and CBE_REGn(3) = '0' then 
+
+                                                       CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); 
+                                                       CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
+
+                               else    CONF_STATUS(30) <= SERR or CONF_STATUS(30);
+                                                       CONF_STATUS(31) <= PERR or CONF_STATUS(31);
+
+                       end if; 
+               end if; 
+       end process;
+
+--*******************************************************************
+--*********** PCI Configuration Space Header "COMMAND" **************
+--*******************************************************************
+
+--     CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
+--     CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
+--     CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus 
+--     CONF_COMMAND( 3) <= '0';-- Special Cycle ???
+--     CONF_COMMAND( 4) <= '0';-- Master ??? 
+--     CONF_COMMAND( 5) <= '0';-- VGA    ???
+--     CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
+               CONF_COMMAND( 7) <= '0';-- address/data stepping ???
+--     CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
+--     CONF_COMMAND( 9) <= '0';-- fast back-to-back
+--     CONF_COMMAND(10) <= '0';-- Reserved
+--     CONF_COMMAND(11) <= '0';-- Reserved
+--     CONF_COMMAND(12) <= '0';-- Reserved
+--     CONF_COMMAND(13) <= '0';-- Reserved
+--     CONF_COMMAND(14) <= '0';-- Reserved
+--     CONF_COMMAND(15) <= '0';-- Reserved
+
+       process (PCI_CLOCK,PCI_RSTn) 
+       begin
+               if PCI_RSTn = '0' then  CONF_COMMAND(15 downto 8) <= (others =>'0');
+                                                                                                               CONF_COMMAND( 6 downto 0) <= (others =>'0');
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       if              CONF_WR_04H      = '1'and CBE_REGn(1) = '0' then 
+
+                                                       CONF_COMMAND(15 downto 8)       <=                              AD_REG(15 downto 8);
+                               else    CONF_COMMAND(15 downto 8)       <=      CONF_COMMAND(15 downto 8);
+                       end if;
+
+
+                       if              CONF_WR_04H      = '1'and CBE_REGn(0) = '0' then 
+
+                                                       CONF_COMMAND( 6 downto 0) <=                            AD_REG( 6 downto 0);
+                               else    CONF_COMMAND( 6 downto 0) <=    CONF_COMMAND( 6 downto 0);
+                       end if;
+
+               end if;
+       end process;
+
+       CONF_DATA_04H   <= CONF_STATUS & CONF_COMMAND;  
+
+end architecture CONFIG_04H_DESIGN;
index b400eabaefcf316dbae8cb3a4a1670cbe7625dd8..fe9e6c456a3d14d94bb39a5429159ef732e4cb34 100644 (file)
@@ -1,28 +1,28 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_08H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_08H is\r
-       port\r
-       (\r
-       REVISION_ID             :in             std_logic_vector ( 7 downto 0);\r
-       CONF_DATA_08H   :out    std_logic_vector (31 downto 0)\r
-       );\r
-end entity CONFIG_08H;\r
-\r
-architecture CONFIG_08H_DESIGN of CONFIG_08H is\r
-\r
--- PCI Configuration Space Header Addr : HEX 08 --\r
-\r
-       constant        CONF_CLASS_CODE         :std_logic_vector (31 downto  8) := X"078000";--other comm. device              \r
---constant     CONF_REVISION_ID        :std_logic_vector ( 7 downto  0) := X"00";                      \r
-\r
-begin\r
-\r
-       CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;\r
-\r
-end architecture CONFIG_08H_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_08H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_08H is
+       port
+       (
+       REVISION_ID             :in             std_logic_vector ( 7 downto 0);
+       CONF_DATA_08H   :out    std_logic_vector (31 downto 0)
+       );
+end entity CONFIG_08H;
+
+architecture CONFIG_08H_DESIGN of CONFIG_08H is
+
+-- PCI Configuration Space Header Addr : HEX 08 --
+
+       constant        CONF_CLASS_CODE         :std_logic_vector (31 downto  8) := X"078000";--other comm. device              
+--constant     CONF_REVISION_ID        :std_logic_vector ( 7 downto  0) := X"00";                      
+
+begin
+
+       CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
+
+end architecture CONFIG_08H_DESIGN;
index 6621607092f9ac8d2463fb9eb4852c6a9699f3f3..9e807fa51342a4b1f7c22f1f97b5d98fde126acc 100644 (file)
@@ -1,87 +1,87 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_10H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_10H is\r
-       port\r
-       (\r
-       PCI_CLOCK                       :in             std_logic;\r
-       PCI_RSTn                        :in             std_logic;\r
-       AD_REG                          :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                        :in             std_logic_vector( 3 downto 0);\r
-       CONF_WR_10H             :in             std_logic;\r
-       CONF_DATA_10H   :out    std_logic_vector(31 downto 0)\r
-       );\r
-end entity CONFIG_10H;\r
-\r
-architecture CONFIG_10H_DESIGN of CONFIG_10H is\r
-\r
-       signal          CONF_BAS_ADDR_REG       :std_logic_vector(31 downto  0);\r
-\r
-begin\r
-\r
---*******************************************************************\r
---***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******\r
---*******************************************************************\r
-\r
-       CONF_BAS_ADDR_REG(1 downto 0) <= "01"   ;-- Base Address Register for "I/O"\r
-       CONF_BAS_ADDR_REG(3 downto 2)   <= "00" ;-- IO Bereich = 16 BYTE\r
-\r
-       process (PCI_CLOCK,PCI_RSTn) \r
-       begin\r
-\r
---     if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');\r
-               if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');\r
-                                                               \r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(3) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);\r
-\r
-                               else    CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);\r
-                       end if;\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(2) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);\r
-\r
-                               else    CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);\r
-                       end if;\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(1) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG(15 downto  8) <= AD_REG(15 downto  8);\r
-\r
-                               else    CONF_BAS_ADDR_REG(15 downto  8) <= CONF_BAS_ADDR_REG(15 downto  8);\r
-                       end if;\r
-\r
---                     if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
---\r
---                                                     CONF_BAS_ADDR_REG( 7 downto  2) <= AD_REG( 7 downto  2);\r
---\r
---                             else    CONF_BAS_ADDR_REG( 7 downto  2) <= CONF_BAS_ADDR_REG( 7 downto  2);\r
---                     end if;\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG( 7 downto  4) <= AD_REG( 7 downto  4);\r
-\r
-                               else    CONF_BAS_ADDR_REG( 7 downto  4) <= CONF_BAS_ADDR_REG( 7 downto  4);\r
-                       end if;\r
-\r
-\r
-               end if;\r
-\r
-       end process;\r
-\r
-       CONF_DATA_10H   <= CONF_BAS_ADDR_REG;\r
-\r
-end architecture CONFIG_10H_DESIGN;\r
-\r
-\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_10H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_10H is
+       port
+       (
+       PCI_CLOCK                       :in             std_logic;
+       PCI_RSTn                        :in             std_logic;
+       AD_REG                          :in             std_logic_vector(31 downto 0);
+       CBE_REGn                        :in             std_logic_vector( 3 downto 0);
+       CONF_WR_10H             :in             std_logic;
+       CONF_DATA_10H   :out    std_logic_vector(31 downto 0)
+       );
+end entity CONFIG_10H;
+
+architecture CONFIG_10H_DESIGN of CONFIG_10H is
+
+       signal          CONF_BAS_ADDR_REG       :std_logic_vector(31 downto  0);
+
+begin
+
+--*******************************************************************
+--***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******
+--*******************************************************************
+
+       CONF_BAS_ADDR_REG(1 downto 0) <= "01"   ;-- Base Address Register for "I/O"
+       CONF_BAS_ADDR_REG(3 downto 2)   <= "00" ;-- IO Bereich = 16 BYTE
+
+       process (PCI_CLOCK,PCI_RSTn) 
+       begin
+
+--     if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
+               if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
+                                                               
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(3) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
+
+                               else    CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
+                       end if;
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(2) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
+
+                               else    CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
+                       end if;
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(1) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG(15 downto  8) <= AD_REG(15 downto  8);
+
+                               else    CONF_BAS_ADDR_REG(15 downto  8) <= CONF_BAS_ADDR_REG(15 downto  8);
+                       end if;
+
+--                     if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then 
+--
+--                                                     CONF_BAS_ADDR_REG( 7 downto  2) <= AD_REG( 7 downto  2);
+--
+--                             else    CONF_BAS_ADDR_REG( 7 downto  2) <= CONF_BAS_ADDR_REG( 7 downto  2);
+--                     end if;
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG( 7 downto  4) <= AD_REG( 7 downto  4);
+
+                               else    CONF_BAS_ADDR_REG( 7 downto  4) <= CONF_BAS_ADDR_REG( 7 downto  4);
+                       end if;
+
+
+               end if;
+
+       end process;
+
+       CONF_DATA_10H   <= CONF_BAS_ADDR_REG;
+
+end architecture CONFIG_10H_DESIGN;
+
+
+
index 1cc7f8077a3a34ac966c59e656475f3ac2ba2cf2..fd71b59e5084176c5ad61ded4214d9a6ac448ba9 100644 (file)
@@ -1,59 +1,59 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_3CH.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_3CH is\r
-        port (\r
-                PCI_CLOCK      :in std_logic;\r
-                PCI_RSTn       :in std_logic;\r
-                AD_REG         :in std_logic_vector (31 downto 0);\r
-                CBE_REGn       :in std_logic_vector ( 3 downto 0);\r
-                CONF_WR_3CH    :in std_logic;\r
-                CONF_DATA_3CH  :out std_logic_vector (31 downto 0)\r
-        );\r
-end entity CONFIG_3CH;\r
-\r
-architecture CONFIG_3CH_DESIGN of CONFIG_3CH is\r
-\r
--- PCI Configuration Space Header Addr : HEX 3C --\r
-\r
-       signal CONF_MAX_LAT :std_logic_vector (31 downto 24);\r
-       signal CONF_MIN_GNT :std_logic_vector (23 downto 16);  \r
-       signal CONF_INT_PIN :std_logic_vector (15 downto  8);\r
-       signal CONF_INT_LINE :std_logic_vector ( 7 downto  0);  \r
-\r
-       constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";\r
-begin \r
-\r
---*******************************************************************\r
---*********** PCI Configuration Space Header "INTERRUPT" ************\r
---*******************************************************************\r
-\r
-               CONF_MAX_LAT    <= X"00";\r
-               CONF_MIN_GNT    <= X"00";\r
---     CONF_INT_PIN    <= X"00";                               -- Interrupt -\r
-               CONF_INT_PIN    <= X"01";                               -- Interrupt A\r
---     CONF_INT_PIN    <= X"02";                               -- Interrupt B\r
---     CONF_INT_PIN    <= X"03";                               -- Interrupt C \r
---     CONF_INT_PIN    <= X"04";                               -- Interrupt D\r
---     CONF_INT_PIN    <= X"05 - FF0"; -- Reserviert\r
-\r
-process (PCI_CLOCK,PCI_RSTn) \r
-begin\r
-        if PCI_RSTn = '0' then\r
-                CONF_INT_LINE <= (others => '0');\r
-\r
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then \r
-                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);\r
-                end if;\r
-        end if;\r
-end process;\r
-\r
-CONF_DATA_3CH  <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;\r
-\r
-end architecture CONFIG_3CH_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_3CH.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_3CH is
+        port (
+                PCI_CLOCK      :in std_logic;
+                PCI_RSTn       :in std_logic;
+                AD_REG         :in std_logic_vector (31 downto 0);
+                CBE_REGn       :in std_logic_vector ( 3 downto 0);
+                CONF_WR_3CH    :in std_logic;
+                CONF_DATA_3CH  :out std_logic_vector (31 downto 0)
+        );
+end entity CONFIG_3CH;
+
+architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
+
+-- PCI Configuration Space Header Addr : HEX 3C --
+
+       signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
+       signal CONF_MIN_GNT :std_logic_vector (23 downto 16);  
+       signal CONF_INT_PIN :std_logic_vector (15 downto  8);
+       signal CONF_INT_LINE :std_logic_vector ( 7 downto  0);  
+
+       constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
+begin 
+
+--*******************************************************************
+--*********** PCI Configuration Space Header "INTERRUPT" ************
+--*******************************************************************
+
+               CONF_MAX_LAT    <= X"00";
+               CONF_MIN_GNT    <= X"00";
+--     CONF_INT_PIN    <= X"00";                               -- Interrupt -
+               CONF_INT_PIN    <= X"01";                               -- Interrupt A
+--     CONF_INT_PIN    <= X"02";                               -- Interrupt B
+--     CONF_INT_PIN    <= X"03";                               -- Interrupt C 
+--     CONF_INT_PIN    <= X"04";                               -- Interrupt D
+--     CONF_INT_PIN    <= X"05 - FF0"; -- Reserviert
+
+process (PCI_CLOCK,PCI_RSTn) 
+begin
+        if PCI_RSTn = '0' then
+                CONF_INT_LINE <= (others => '0');
+
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then 
+                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
+                end if;
+        end if;
+end process;
+
+CONF_DATA_3CH  <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
+
+end architecture CONFIG_3CH_DESIGN;
index 64e2560bc1ff786977651c383372193cbeb3f3fc..771b3d702eafae12b83f5e38a89f6d7382a9c898 100644 (file)
@@ -1,44 +1,44 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_MUX_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_MUX_0 is\r
-       port\r
-       (\r
-       READ_SEL                        :in             std_logic_vector( 2 downto 0);\r
-       CONF_DATA_00H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_04H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_08H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_10H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_3CH   :in             std_logic_vector(31 downto 0);\r
---CONF_DATA_40H        :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA                       :out    std_logic_vector(31 downto 0)\r
-    );\r
-end entity CONFIG_MUX_0;\r
-\r
-architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is\r
-\r
-       signal  MUX     :std_logic_vector (31 downto  0); \r
-\r
-begin\r
-\r
---*******************************************************************\r
---******************* PCI Read  Config-MUX **************************\r
---*******************************************************************\r
-\r
-       MUX <=  CONF_DATA_00H   when READ_SEL <= "000" else \r
-                                       CONF_DATA_04H   when READ_SEL <= "001" else\r
-                                       CONF_DATA_08H   when READ_SEL <= "010" else\r
-                                       CONF_DATA_10H   when READ_SEL <= "011" else\r
-                                       CONF_DATA_3CH   when READ_SEL <= "100" else\r
---                             CONF_DATA_40H   when READ_SEL <= "101" else\r
-                                       X"00000000"     ;\r
-\r
-       CONF_DATA <= MUX ;\r
-\r
-\r
-end architecture CONFIG_MUX_0_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_MUX_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_MUX_0 is
+       port
+       (
+       READ_SEL                        :in             std_logic_vector( 2 downto 0);
+       CONF_DATA_00H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_04H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_08H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_10H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_3CH   :in             std_logic_vector(31 downto 0);
+--CONF_DATA_40H        :in             std_logic_vector(31 downto 0);
+       CONF_DATA                       :out    std_logic_vector(31 downto 0)
+    );
+end entity CONFIG_MUX_0;
+
+architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is
+
+       signal  MUX     :std_logic_vector (31 downto  0); 
+
+begin
+
+--*******************************************************************
+--******************* PCI Read  Config-MUX **************************
+--*******************************************************************
+
+       MUX <=  CONF_DATA_00H   when READ_SEL <= "000" else 
+                                       CONF_DATA_04H   when READ_SEL <= "001" else
+                                       CONF_DATA_08H   when READ_SEL <= "010" else
+                                       CONF_DATA_10H   when READ_SEL <= "011" else
+                                       CONF_DATA_3CH   when READ_SEL <= "100" else
+--                             CONF_DATA_40H   when READ_SEL <= "101" else
+                                       X"00000000"     ;
+
+       CONF_DATA <= MUX ;
+
+
+end architecture CONFIG_MUX_0_DESIGN;
index 1b19b633ffc988b74af151ab70e7a31225b46d4c..42f9d247adeac63ed880d5555b8d9e75b54835a0 100644 (file)
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_RD_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_RD_0 is\r
-    port\r
-       (\r
-       ADDR_REG        :in             std_logic_vector (31 downto 0);\r
-       CF_RD_COM       :in             std_logic;\r
-       READ_SEL        :out    std_logic_vector ( 2 downto 0)\r
-    );\r
-end entity CONFIG_RD_0;\r
-\r
-architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is\r
-\r
---\r
---\r
---\r
---\r
---\r
---                            PCI Configuration Space Header\r
---\r
---            \                        Bit\r
---                        \\r
---Address              |31               24|23           16|15            8|7             0|      \r
------------------------------------------------------------------\r
---00                   |Device ID                              |Vendor ID                              |                                       \r
---04                   |Status                                 |Command                                |\r
---08                   |Class Code                                                     |Revision ID|\r
---0C                   |BIST           |Header Type|Latency T. |Cache L.S.     |\r
---10-24                        |Base Address Register                                                  |\r
---28                   |Cardbus CIS Pointer                                                    |\r
---2C                   |Subsystem ID                   |Subsystem Vendor ID    |\r
---30                   |Expansion ROM Base Address                                             |\r
---34                   |Reserved                                                                               |\r
---38                   |Reserved                                                                               |\r
---3C                   |Max_Lat        |Min_Gnt        |Int_Pin        |Int_Line       |\r
---40-FF                        |                                                                                               |\r
------------------------------------------------------------------\r
-\r
-\r
---PCI Bus Commands \r
---C/BE[3..0] Command Type\r
---------------------------------------\r
---     0000            Interrupt Acknowledge\r
---     0001            Special Cycle\r
---     0010            I/O Read\r
---     0011            I/O Write\r
---     0100            Reserved\r
---     0101            Reserved\r
---     0110            Memory Read\r
---     0111            Memory Write\r
---\r
---     1000            Reserved\r
---     1001            Reserved\r
---     1010            Configuration Read\r
---     1011            Configuration Write\r
---     1100            Memory Read Multiple \r
---     1101            Dual Address Cycle\r
---     1110            Memory Read Line\r
---     1111            Memory Write and Invalidate\r
-\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
-\r
-       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";\r
-       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";\r
-       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";\r
-       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";\r
-       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";\r
-       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";\r
-       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";\r
-       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";\r
-       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";\r
-       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";\r
-       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";\r
-       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";\r
-       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";\r
-       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";\r
-       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";\r
-       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
-\r
-       signal          MUX                                                     :std_logic_vector(31 downto 0); \r
-       signal          CONFIG_ADDR                     :std_logic_vector( 7 downto 0); \r
-\r
-begin\r
-\r
-       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
-\r
---*******************************************************************\r
---*********************** PCI Read Address **************************\r
---*******************************************************************\r
-\r
-       process (CF_RD_COM, CONFIG_ADDR) \r
-       begin\r
-\r
-               if      CF_RD_COM = '1' then\r
-\r
-                       if              CONFIG_ADDR = X"00"     then    READ_SEL <= "000";\r
-                       elsif   CONFIG_ADDR = X"04"     then    READ_SEL <= "001";\r
-                       elsif   CONFIG_ADDR = X"08"     then    READ_SEL <= "010";\r
-                       elsif   CONFIG_ADDR = X"10"     then    READ_SEL <= "011";\r
-                       elsif   CONFIG_ADDR = X"3C"     then    READ_SEL <= "100";\r
-                       elsif   CONFIG_ADDR = X"40"     then    READ_SEL <= "101";\r
-                       else                                                            READ_SEL <= "111";\r
-                       end if;\r
-               else                                                                    READ_SEL <= "111";\r
-               end if;\r
-       end process;\r
-\r
-end architecture CONFIG_RD_0_DESIGN;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_RD_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_RD_0 is
+    port
+       (
+       ADDR_REG        :in             std_logic_vector (31 downto 0);
+       CF_RD_COM       :in             std_logic;
+       READ_SEL        :out    std_logic_vector ( 2 downto 0)
+    );
+end entity CONFIG_RD_0;
+
+architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is
+
+--
+--
+--
+--
+--
+--                            PCI Configuration Space Header
+--
+--            \                        Bit
+--                        \
+--Address              |31               24|23           16|15            8|7             0|      
+-----------------------------------------------------------------
+--00                   |Device ID                              |Vendor ID                              |                                       
+--04                   |Status                                 |Command                                |
+--08                   |Class Code                                                     |Revision ID|
+--0C                   |BIST           |Header Type|Latency T. |Cache L.S.     |
+--10-24                        |Base Address Register                                                  |
+--28                   |Cardbus CIS Pointer                                                    |
+--2C                   |Subsystem ID                   |Subsystem Vendor ID    |
+--30                   |Expansion ROM Base Address                                             |
+--34                   |Reserved                                                                               |
+--38                   |Reserved                                                                               |
+--3C                   |Max_Lat        |Min_Gnt        |Int_Pin        |Int_Line       |
+--40-FF                        |                                                                                               |
+-----------------------------------------------------------------
+
+
+--PCI Bus Commands 
+--C/BE[3..0] Command Type
+--------------------------------------
+--     0000            Interrupt Acknowledge
+--     0001            Special Cycle
+--     0010            I/O Read
+--     0011            I/O Write
+--     0100            Reserved
+--     0101            Reserved
+--     0110            Memory Read
+--     0111            Memory Write
+--
+--     1000            Reserved
+--     1001            Reserved
+--     1010            Configuration Read
+--     1011            Configuration Write
+--     1100            Memory Read Multiple 
+--     1101            Dual Address Cycle
+--     1110            Memory Read Line
+--     1111            Memory Write and Invalidate
+
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+
+       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";
+       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";
+       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";
+       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";
+       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";
+       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";
+       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";
+       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";
+       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";
+       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";
+       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";
+       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";
+       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";
+       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";
+       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";
+       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+       signal          MUX                                                     :std_logic_vector(31 downto 0); 
+       signal          CONFIG_ADDR                     :std_logic_vector( 7 downto 0); 
+
+begin
+
+       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+--*******************************************************************
+--*********************** PCI Read Address **************************
+--*******************************************************************
+
+       process (CF_RD_COM, CONFIG_ADDR) 
+       begin
+
+               if      CF_RD_COM = '1' then
+
+                       if              CONFIG_ADDR = X"00"     then    READ_SEL <= "000";
+                       elsif   CONFIG_ADDR = X"04"     then    READ_SEL <= "001";
+                       elsif   CONFIG_ADDR = X"08"     then    READ_SEL <= "010";
+                       elsif   CONFIG_ADDR = X"10"     then    READ_SEL <= "011";
+                       elsif   CONFIG_ADDR = X"3C"     then    READ_SEL <= "100";
+                       elsif   CONFIG_ADDR = X"40"     then    READ_SEL <= "101";
+                       else                                                            READ_SEL <= "111";
+                       end if;
+               else                                                                    READ_SEL <= "111";
+               end if;
+       end process;
+
+end architecture CONFIG_RD_0_DESIGN;
+
index 8f6160209568aaf71fa6384af07674f722a04296..4e3092d158440fc9ef089321ca2f4bb5b6bc83e5 100644 (file)
--- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity CONFIG_SPACE_HEADER is\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CF_RD_COM : In    std_logic;\r
-             CF_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-                PERR : In    std_logic;\r
-             REVISION_ID : In    std_logic_vector (7 downto 0);\r
-                SERR : In    std_logic;\r
-               TRDYn : In    std_logic;\r
-             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-             CONF_DATA : Out   std_logic_vector (31 downto 0);\r
-             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);\r
-             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
-end CONFIG_SPACE_HEADER;\r
-\r
-architecture SCHEMATIC of CONFIG_SPACE_HEADER is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal CONF_WR_04H : std_logic;\r
-   signal CONF_WR_10H : std_logic;\r
-   signal CONF_WR_3CH : std_logic;\r
-   signal CONF_READ_SEL : std_logic_vector (2 downto 0);\r
-   signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_3CH : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_08H : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_00H : std_logic_vector (31 downto 0);\r
-\r
-   component CONFIG_MUX_0\r
-      Port ( CONF_DATA_00H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_04H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_08H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_10H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_3CH : In    std_logic_vector (31 downto 0);\r
-             READ_SEL : In    std_logic_vector (2 downto 0);\r
-             CONF_DATA : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_RD_0\r
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CF_RD_COM : In    std_logic;\r
-             READ_SEL : Out   std_logic_vector (2 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_WR_0\r
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CF_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-               TRDYn : In    std_logic;\r
-             CONF_WR_04H : Out   std_logic;\r
-             CONF_WR_10H : Out   std_logic;\r
-             CONF_WR_3CH : Out   std_logic );\r
-   end component;\r
-\r
-   component CONFIG_3CH\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CONF_WR_3CH : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             CONF_DATA_3CH : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_10H\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CONF_WR_10H : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_08H\r
-      Port ( REVISION_ID : In    std_logic_vector (7 downto 0);\r
-             CONF_DATA_08H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_00H\r
-      Port ( VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-             CONF_DATA_00H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_04H\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CONF_WR_04H : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-                PERR : In    std_logic;\r
-                SERR : In    std_logic;\r
-             CONF_DATA_04H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   CONF_DATA_04H <= CONF_DATA_04H_DUMMY;\r
-   CONF_DATA_10H <= CONF_DATA_10H_DUMMY;\r
-\r
-   I10 : CONFIG_MUX_0\r
-      Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),\r
-                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),\r
-                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),\r
-                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),\r
-                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),\r
-                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),\r
-                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );\r
-   I9 : CONFIG_RD_0\r
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CF_RD_COM=>CF_RD_COM,\r
-                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );\r
-   I8 : CONFIG_WR_0\r
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,\r
-                 TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,\r
-                 CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );\r
-   I6 : CONFIG_3CH\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn,\r
-                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );\r
-   I5 : CONFIG_10H\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn,\r
-                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );\r
-   I4 : CONFIG_08H\r
-      Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),\r
-                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );\r
-   I3 : CONFIG_00H\r
-      Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
-                 CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );\r
-   I2 : CONFIG_04H\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,\r
-                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity CONFIG_SPACE_HEADER is
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             ADDR_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CF_RD_COM : In    std_logic;
+             CF_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+                PERR : In    std_logic;
+             REVISION_ID : In    std_logic_vector (7 downto 0);
+                SERR : In    std_logic;
+               TRDYn : In    std_logic;
+             VENDOR_ID : In    std_logic_vector (15 downto 0);
+             CONF_DATA : Out   std_logic_vector (31 downto 0);
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
+end CONFIG_SPACE_HEADER;
+
+architecture SCHEMATIC of CONFIG_SPACE_HEADER is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal CONF_WR_04H : std_logic;
+   signal CONF_WR_10H : std_logic;
+   signal CONF_WR_3CH : std_logic;
+   signal CONF_READ_SEL : std_logic_vector (2 downto 0);
+   signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
+   signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
+   signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
+   signal CONF_DATA_08H : std_logic_vector (31 downto 0);
+   signal CONF_DATA_00H : std_logic_vector (31 downto 0);
+
+   component CONFIG_MUX_0
+      Port ( CONF_DATA_00H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_04H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_08H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_10H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_3CH : In    std_logic_vector (31 downto 0);
+             READ_SEL : In    std_logic_vector (2 downto 0);
+             CONF_DATA : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_RD_0
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
+             CF_RD_COM : In    std_logic;
+             READ_SEL : Out   std_logic_vector (2 downto 0) );
+   end component;
+
+   component CONFIG_WR_0
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
+             CF_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+               TRDYn : In    std_logic;
+             CONF_WR_04H : Out   std_logic;
+             CONF_WR_10H : Out   std_logic;
+             CONF_WR_3CH : Out   std_logic );
+   end component;
+
+   component CONFIG_3CH
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CONF_WR_3CH : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             CONF_DATA_3CH : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_10H
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CONF_WR_10H : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_08H
+      Port ( REVISION_ID : In    std_logic_vector (7 downto 0);
+             CONF_DATA_08H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_00H
+      Port ( VENDOR_ID : In    std_logic_vector (15 downto 0);
+             CONF_DATA_00H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_04H
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CONF_WR_04H : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+                PERR : In    std_logic;
+                SERR : In    std_logic;
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+begin
+
+   CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
+   CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
+
+   I10 : CONFIG_MUX_0
+      Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
+                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
+                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
+                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
+                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
+   I9 : CONFIG_RD_0
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CF_RD_COM=>CF_RD_COM,
+                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
+   I8 : CONFIG_WR_0
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
+                 TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
+                 CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
+   I6 : CONFIG_3CH
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn,
+                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
+   I5 : CONFIG_10H
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn,
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
+   I4 : CONFIG_08H
+      Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
+                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
+   I3 : CONFIG_00H
+      Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+                 CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
+   I2 : CONFIG_04H
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
+
+end SCHEMATIC;
index 4c7b96c195a631479553ce4e3e8581ebfe4bb3ed..2df596dd694b4f463cde436c5b3817f1cec8bc5f 100644 (file)
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_WR_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_WR_0 is\r
-    port\r
-       (\r
-       ADDR_REG                        :in             std_logic_vector(31 downto 0);\r
-       CF_WR_COM                       :in             std_logic;\r
-       IRDY_REGn                       :in             std_logic;\r
-       TRDYn                                   :in             std_logic;\r
-       CONF_WR_04H             :out    std_logic; \r
-       CONF_WR_10H             :out    std_logic; \r
-       CONF_WR_3CH             :out    std_logic\r
---CONF_WR_40H          :out    std_logic \r
-    );\r
-end entity CONFIG_WR_0;\r
-\r
-architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is\r
-\r
---\r
---\r
---\r
---\r
---\r
---                            PCI Configuration Space Header\r
---\r
---       \                        Bit\r
---                       \\r
---Address      |31                                     24|23                             16|15                    8|7                           0|      \r
------------------------------------------------------------------\r
---00                   |Device ID                                                                      |Vendor ID                                                      |                                       \r
---04                   |Status                                                                                 |Command                                                                |\r
---08                   |Class Code                                                                     |Revision ID                                            |\r
---0C                   |BIST                           |Header Type            |Latency T.     |Cache L.S.     |\r
---10-24                |Base Address Register                                                                                                                  |\r
---28                   |Cardbus CIS Pointer                                                                                                                            |\r
---2C                   |Subsystem ID                                                           |Subsystem Vendor ID            |\r
---30                   |Expansion ROM Base Address                                                                                                     |\r
---34                   |Reserved                                                                                                                                                                               |\r
---38                   |Reserved                                                                                                                                                                               |\r
---3C                   |Max_Lat                |Min_Gnt                                |Int_Pin                |Int_Line               |\r
---40-FF                |                                                                                                                                                                                                               |\r
------------------------------------------------------------------\r
-\r
-\r
---PCI Bus Commands \r
---C/BE[3..0] Command Type\r
---------------------------------------\r
---     0000            Interrupt Acknowledge\r
---     0001            Special Cycle\r
---     0010            I/O Read\r
---     0011            I/O Write\r
---     0100            Reserved\r
---     0101            Reserved\r
---     0110            Memory Read\r
---     0111            Memory Write\r
---\r
---     1000            Reserved\r
---     1001            Reserved\r
---     1010            Configuration Read\r
---     1011            Configuration Write\r
---     1100            Memory Read Multiple \r
---     1101            Dual Address Cycle\r
---     1110            Memory Read Line\r
---     1111            Memory Write and Invalidate\r
-\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
-\r
-       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";\r
-       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";\r
-       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";\r
-       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";\r
-       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";\r
-       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";\r
-       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";\r
-       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";\r
-       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";\r
-       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";\r
-       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";\r
-       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";\r
-       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";\r
-       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";\r
-       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";\r
-       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
-\r
-       signal          CONFIG_ADDR :std_logic_vector(7 downto 0); \r
-       signal          CONFIG_WRITE :std_logic_vector(3 downto 0); \r
-\r
-\r
-begin\r
-\r
---*******************************************************************\r
---******************* PCI Write Configuration Address ***************\r
---*******************************************************************\r
-\r
-       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
-\r
-\r
-       process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) \r
-       begin\r
-\r
-               if      CF_WR_COM = '1' and     IRDY_REGn = '0' and     TRDYn = '0'     then\r
-\r
-                       if CONFIG_ADDR = X"04" then\r
-                                CONFIG_WRITE   <= "0001";\r
-\r
-                        elsif CONFIG_ADDR = X"10" then\r
-                                CONFIG_WRITE   <= "0010";\r
-\r
-                        elsif  CONFIG_ADDR = X"3C" then\r
-                                CONFIG_WRITE   <= "0100";\r
-\r
---                     elsif   CONFIG_ADDR = X"40"     then    CONFIG_WRITE    <= "1000";\r
-                        else\r
-                                CONFIG_WRITE   <= "0000";\r
-                       end if;\r
-               else            \r
-                        CONFIG_WRITE   <= "0000";\r
-               end if;\r
-       end process;\r
-\r
-       CONF_WR_04H     <=      CONFIG_WRITE(0); \r
-       CONF_WR_10H     <=      CONFIG_WRITE(1);         \r
-       CONF_WR_3CH     <=      CONFIG_WRITE(2);        \r
---CONF_WR_40H  <=      CONFIG_WRITE(3);        \r
-\r
-end architecture CONFIG_WR_0_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_WR_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_WR_0 is
+    port
+       (
+       ADDR_REG                        :in             std_logic_vector(31 downto 0);
+       CF_WR_COM                       :in             std_logic;
+       IRDY_REGn                       :in             std_logic;
+       TRDYn                                   :in             std_logic;
+       CONF_WR_04H             :out    std_logic; 
+       CONF_WR_10H             :out    std_logic; 
+       CONF_WR_3CH             :out    std_logic
+--CONF_WR_40H          :out    std_logic 
+    );
+end entity CONFIG_WR_0;
+
+architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is
+
+--
+--
+--
+--
+--
+--                            PCI Configuration Space Header
+--
+--       \                        Bit
+--                       \
+--Address      |31                                     24|23                             16|15                    8|7                           0|      
+-----------------------------------------------------------------
+--00                   |Device ID                                                                      |Vendor ID                                                      |                                       
+--04                   |Status                                                                                 |Command                                                                |
+--08                   |Class Code                                                                     |Revision ID                                            |
+--0C                   |BIST                           |Header Type            |Latency T.     |Cache L.S.     |
+--10-24                |Base Address Register                                                                                                                  |
+--28                   |Cardbus CIS Pointer                                                                                                                            |
+--2C                   |Subsystem ID                                                           |Subsystem Vendor ID            |
+--30                   |Expansion ROM Base Address                                                                                                     |
+--34                   |Reserved                                                                                                                                                                               |
+--38                   |Reserved                                                                                                                                                                               |
+--3C                   |Max_Lat                |Min_Gnt                                |Int_Pin                |Int_Line               |
+--40-FF                |                                                                                                                                                                                                               |
+-----------------------------------------------------------------
+
+
+--PCI Bus Commands 
+--C/BE[3..0] Command Type
+--------------------------------------
+--     0000            Interrupt Acknowledge
+--     0001            Special Cycle
+--     0010            I/O Read
+--     0011            I/O Write
+--     0100            Reserved
+--     0101            Reserved
+--     0110            Memory Read
+--     0111            Memory Write
+--
+--     1000            Reserved
+--     1001            Reserved
+--     1010            Configuration Read
+--     1011            Configuration Write
+--     1100            Memory Read Multiple 
+--     1101            Dual Address Cycle
+--     1110            Memory Read Line
+--     1111            Memory Write and Invalidate
+
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+
+       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";
+       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";
+       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";
+       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";
+       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";
+       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";
+       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";
+       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";
+       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";
+       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";
+       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";
+       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";
+       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";
+       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";
+       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";
+       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+       signal          CONFIG_ADDR :std_logic_vector(7 downto 0); 
+       signal          CONFIG_WRITE :std_logic_vector(3 downto 0); 
+
+
+begin
+
+--*******************************************************************
+--******************* PCI Write Configuration Address ***************
+--*******************************************************************
+
+       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+
+       process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) 
+       begin
+
+               if      CF_WR_COM = '1' and     IRDY_REGn = '0' and     TRDYn = '0'     then
+
+                       if CONFIG_ADDR = X"04" then
+                                CONFIG_WRITE   <= "0001";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                CONFIG_WRITE   <= "0010";
+
+                        elsif  CONFIG_ADDR = X"3C" then
+                                CONFIG_WRITE   <= "0100";
+
+--                     elsif   CONFIG_ADDR = X"40"     then    CONFIG_WRITE    <= "1000";
+                        else
+                                CONFIG_WRITE   <= "0000";
+                       end if;
+               else            
+                        CONFIG_WRITE   <= "0000";
+               end if;
+       end process;
+
+       CONF_WR_04H     <=      CONFIG_WRITE(0); 
+       CONF_WR_10H     <=      CONFIG_WRITE(1);         
+       CONF_WR_3CH     <=      CONFIG_WRITE(2);        
+--CONF_WR_40H  <=      CONFIG_WRITE(3);        
+
+end architecture CONFIG_WR_0_DESIGN;
index ab8f54f3154d6540151980515974ad48409af1fc..c7e7340eec745eb9940addbf2b703213d397285e 100644 (file)
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONNECTING_FSM.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity CONNECTING_FSM is\r
-       port\r
-       (\r
-       PCI_CLOCK                               :in             std_logic; \r
-       RESET                                           :in             std_logic; \r
-       PSC_ENABLE                      :in             std_logic;\r
-       SYNC_S_FIFO_EFn :in             std_logic;\r
-       SPC_ENABLE                      :in             std_logic;\r
-       SYNC_R_FIFO_FFn :in             std_logic;\r
-       S_FIFO_Q_OUT            :in             std_logic_vector(7 downto 0);\r
-       S_FIFO_READn            :out    std_logic;\r
-       R_FIFO_WRITEn           :out    std_logic;\r
-       R_FIFO_D_IN                     :out    std_logic_vector(7 downto 0) \r
-       );\r
-end entity CONNECTING_FSM;\r
-\r
-architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is\r
-\r
-       signal REG                                              :std_logic_vector(7 downto 0);\r
-       signal HELP_0,HELP_1    :std_logic;\r
-       signal SIG_LOAD                         :std_logic;\r
-\r
-\r
---**********************************************************\r
---***         CONNECTING FSM CODIERUNG                   ***\r
---**********************************************************\r
---\r
---\r
---                                                 ---------- HELP_0\r
---                                                      |--------- HELP_1   \r
---                                                      ||-------- LOAD   \r
---                                                        |||------- WRITE   \r
---                                                                                                                                                                                        ||||------ READ   \r
---                                                                                                                                                                                              |||||     \r
-       constant        S0      :std_logic_vector(4 downto 0)   :=      "00011";--\r
-       constant        S1      :std_logic_vector(4 downto 0)   :=      "01010";--READ\r
-       constant        S2      :std_logic_vector(4 downto 0) :=        "10010";--READ\r
-       constant        S3      :std_logic_vector(4 downto 0) :=        "11110";--READ,LOAD\r
-       constant        S4      :std_logic_vector(4 downto 0) :=        "11011";--\r
-       constant        S5      :std_logic_vector(4 downto 0) :=        "01001";--WRITE\r
-       constant        S6      :std_logic_vector(4 downto 0) :=        "10001";--WRITE\r
-       constant        S7      :std_logic_vector(4 downto 0) :=        "11001";--WRITE\r
-\r
-       signal STATES   :std_logic_vector(4 downto 0);\r
-\r
---************************************************************\r
---***             FSM SPEICHER-AUTOMAT                     ***\r
---************************************************************\r
-\r
-       attribute       syn_state_machine       :       boolean;\r
-       attribute       syn_state_machine       of      STATES  :       signal  is      false;\r
-\r
---************************************************************\r
---***                          REGISTER BESCHREIBUNG                  ***\r
---************************************************************\r
-\r
-begin\r
-\r
-       process (PCI_CLOCK) \r
-       begin\r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then\r
-                       if                      SIG_LOAD        =       '1'     then    REG     <=      S_FIFO_Q_OUT;\r
-                               elsif   SIG_LOAD        =       '0'     then    REG     <=      REG;   \r
-                       end if;\r
-               end if;\r
-       end process;\r
-\r
---************************************************************\r
---***                          FSM BESCHREIBUNG                                 ***\r
---************************************************************\r
-\r
-       process (PCI_CLOCK)\r
-       begin  \r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then\r
-  \r
-                       if      RESET   =       '1'     then    STATES <= S0;\r
-                               else\r
-  \r
-                                       case    STATES is\r
-\r
-                                       when    S0      => \r
-                                               if      PSC_ENABLE                      = '1'   and\r
-                                                               SPC_ENABLE                      =       '1'     and\r
-                                                               SYNC_S_FIFO_EFn =       '1'     then\r
-\r
-                                                                                               STATES  <=      S1;\r
-                                                       else  \r
-                                                                                               STATES  <=      S0;\r
-                                               end if;\r
-\r
-                                       when    S1      =>      STATES  <=      S2;\r
-                                       when    S2      =>      STATES  <=      S3;\r
-                                       when    S3      =>      STATES  <=      S4;\r
-\r
-                                       when    S4      => \r
-                                               if      SYNC_R_FIFO_FFn =       '1'     then\r
-\r
-                                                                                               STATES  <=      S5;\r
-                                               else  \r
-                               STATES  <=      S4;\r
-                                               end if;\r
-\r
-                                       when    S5      =>      STATES  <=      S6;\r
-                                       when    S6      =>      STATES  <=      S7;\r
-                                       when    S7      =>      STATES  <=      S0;\r
-\r
-                                       when others => \r
-\r
-                                                                                               STATES  <=      S0; \r
-\r
-                               end case;               -- STATES    \r
-                       end if;                         -- RESET \r
-               end if;                                 -- PCI_CLOCK   \r
-       end process;                    -- PROCESS\r
-\r
---************************************************************\r
---***          ZUWEISUNG       signal/out      <=      STATES             ***\r
---************************************************************\r
-\r
-       HELP_0                          <=      STATES(4);  \r
-       HELP_1                          <=      STATES(3);\r
-       SIG_LOAD                        <=      STATES(2);\r
-       R_FIFO_WRITEn   <=      STATES(1);\r
-       S_FIFO_READn    <=      STATES(0);\r
-\r
-       R_FIFO_D_IN             <=      REG;\r
-\r
-end architecture CONNECTING_FSM_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONNECTING_FSM.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity CONNECTING_FSM is
+       port
+       (
+       PCI_CLOCK                               :in             std_logic; 
+       RESET                                           :in             std_logic; 
+       PSC_ENABLE                      :in             std_logic;
+       SYNC_S_FIFO_EFn :in             std_logic;
+       SPC_ENABLE                      :in             std_logic;
+       SYNC_R_FIFO_FFn :in             std_logic;
+       S_FIFO_Q_OUT            :in             std_logic_vector(7 downto 0);
+       S_FIFO_READn            :out    std_logic;
+       R_FIFO_WRITEn           :out    std_logic;
+       R_FIFO_D_IN                     :out    std_logic_vector(7 downto 0) 
+       );
+end entity CONNECTING_FSM;
+
+architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
+
+       signal REG                                              :std_logic_vector(7 downto 0);
+       signal HELP_0,HELP_1    :std_logic;
+       signal SIG_LOAD                         :std_logic;
+
+
+--**********************************************************
+--***         CONNECTING FSM CODIERUNG                   ***
+--**********************************************************
+--
+--
+--                                                 ---------- HELP_0
+--                                                      |--------- HELP_1   
+--                                                      ||-------- LOAD   
+--                                                        |||------- WRITE   
+--                                                                                                                                                                                        ||||------ READ   
+--                                                                                                                                                                                              |||||     
+       constant        S0      :std_logic_vector(4 downto 0)   :=      "00011";--
+       constant        S1      :std_logic_vector(4 downto 0)   :=      "01010";--READ
+       constant        S2      :std_logic_vector(4 downto 0) :=        "10010";--READ
+       constant        S3      :std_logic_vector(4 downto 0) :=        "11110";--READ,LOAD
+       constant        S4      :std_logic_vector(4 downto 0) :=        "11011";--
+       constant        S5      :std_logic_vector(4 downto 0) :=        "01001";--WRITE
+       constant        S6      :std_logic_vector(4 downto 0) :=        "10001";--WRITE
+       constant        S7      :std_logic_vector(4 downto 0) :=        "11001";--WRITE
+
+       signal STATES   :std_logic_vector(4 downto 0);
+
+--************************************************************
+--***             FSM SPEICHER-AUTOMAT                     ***
+--************************************************************
+
+       attribute       syn_state_machine       :       boolean;
+       attribute       syn_state_machine       of      STATES  :       signal  is      false;
+
+--************************************************************
+--***                          REGISTER BESCHREIBUNG                  ***
+--************************************************************
+
+begin
+
+       process (PCI_CLOCK) 
+       begin
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then
+                       if                      SIG_LOAD        =       '1'     then    REG     <=      S_FIFO_Q_OUT;
+                               elsif   SIG_LOAD        =       '0'     then    REG     <=      REG;   
+                       end if;
+               end if;
+       end process;
+
+--************************************************************
+--***                          FSM BESCHREIBUNG                                 ***
+--************************************************************
+
+       process (PCI_CLOCK)
+       begin  
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then
+  
+                       if      RESET   =       '1'     then    STATES <= S0;
+                               else
+  
+                                       case    STATES is
+
+                                       when    S0      => 
+                                               if      PSC_ENABLE                      = '1'   and
+                                                               SPC_ENABLE                      =       '1'     and
+                                                               SYNC_S_FIFO_EFn =       '1'     then
+
+                                                                                               STATES  <=      S1;
+                                                       else  
+                                                                                               STATES  <=      S0;
+                                               end if;
+
+                                       when    S1      =>      STATES  <=      S2;
+                                       when    S2      =>      STATES  <=      S3;
+                                       when    S3      =>      STATES  <=      S4;
+
+                                       when    S4      => 
+                                               if      SYNC_R_FIFO_FFn =       '1'     then
+
+                                                                                               STATES  <=      S5;
+                                               else  
+                               STATES  <=      S4;
+                                               end if;
+
+                                       when    S5      =>      STATES  <=      S6;
+                                       when    S6      =>      STATES  <=      S7;
+                                       when    S7      =>      STATES  <=      S0;
+
+                                       when others => 
+
+                                                                                               STATES  <=      S0; 
+
+                               end case;               -- STATES    
+                       end if;                         -- RESET 
+               end if;                                 -- PCI_CLOCK   
+       end process;                    -- PROCESS
+
+--************************************************************
+--***          ZUWEISUNG       signal/out      <=      STATES             ***
+--************************************************************
+
+       HELP_0                          <=      STATES(4);  
+       HELP_1                          <=      STATES(3);
+       SIG_LOAD                        <=      STATES(2);
+       R_FIFO_WRITEn   <=      STATES(1);
+       S_FIFO_READn    <=      STATES(0);
+
+       R_FIFO_D_IN             <=      REG;
+
+end architecture CONNECTING_FSM_DESIGN;
index 1baa801b7199d5695ff8a884c4313e7aff210e99..58c25abfc4d483bd9d7e7d321be0e78166a6fbc9 100644 (file)
--- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity FIFO_CONTROL is\r
-      Port ( FIFO_RDn : In    std_logic;\r
-             FLAG_IN_0 : In    std_logic;\r
-             FLAG_IN_4 : In    std_logic;\r
-                HOLD : In    std_logic;\r
-             KONST_1 : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PSC_ENABLE : In    std_logic;\r
-               R_EFn : In    std_logic;\r
-               R_FFn : In    std_logic;\r
-               R_HFn : In    std_logic;\r
-               RESET : In    std_logic;\r
-               S_EFn : In    std_logic;\r
-               S_FFn : In    std_logic;\r
-             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
-               S_HFn : In    std_logic;\r
-             SERIAL_IN : In    std_logic;\r
-             SPC_ENABLE : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
-             WRITE_XX1_0 : In    std_logic;\r
-             R_ERROR : Out   std_logic;\r
-             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_READn : Out   std_logic;\r
-             R_FIFO_RESETn : Out   std_logic;\r
-             R_FIFO_RETRANSMITn : Out   std_logic;\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             RESERVE : Out   std_logic;\r
-             S_ERROR : Out   std_logic;\r
-             S_FIFO_READn : Out   std_logic;\r
-             S_FIFO_RESETn : Out   std_logic;\r
-             S_FIFO_RETRANSMITn : Out   std_logic;\r
-             S_FIFO_WRITEn : Out   std_logic;\r
-             SERIAL_OUT : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic;\r
-             SR_ERROR : Out   std_logic;\r
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0));\r
-end FIFO_CONTROL;\r
-\r
-architecture SCHEMATIC of FIFO_CONTROL is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal XXXR_FIFO_WRITEn : std_logic;\r
-   signal XXXS_FIFO_READn : std_logic;\r
-   signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
-   signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
-\r
-   component SER_PAR_CON\r
-      Port ( PCI_CLOCK : In    std_logic;\r
-               RESET : In    std_logic;\r
-             SERIAL_IN : In    std_logic;\r
-             SPC_ENABLE : In    std_logic;\r
-             SYNC_R_FIFO_FFn : In    std_logic;\r
-             PAR_OUT : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic );\r
-   end component;\r
-\r
-   component PAR_SER_CON\r
-      Port (  PAR_IN : In    std_logic_vector (7 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PSC_ENABLE : In    std_logic;\r
-               RESET : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
-             SYNC_S_FIFO_EFn : In    std_logic;\r
-             S_FIFO_READn : Out   std_logic;\r
-             SER_OUT : Out   std_logic );\r
-   end component;\r
-\r
-   component FIFO_IO_CONTROL\r
-      Port ( FIFO_RDn : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-               RESET : In    std_logic;\r
-             SYNC_FLAG_1 : In    std_logic;\r
-             SYNC_FLAG_7 : In    std_logic;\r
-             WRITE_XX1_0 : In    std_logic;\r
-             R_ERROR : Out   std_logic;\r
-             R_FIFO_READn : Out   std_logic;\r
-             R_FIFO_RESETn : Out   std_logic;\r
-             R_FIFO_RETRANSMITn : Out   std_logic;\r
-             S_ERROR : Out   std_logic;\r
-             S_FIFO_RESETn : Out   std_logic;\r
-             S_FIFO_RETRANSMITn : Out   std_logic;\r
-             S_FIFO_WRITEn : Out   std_logic;\r
-             SR_ERROR : Out   std_logic );\r
-   end component;\r
-\r
-   component CONNECTING_FSM\r
-      Port ( PCI_CLOCK : In    std_logic;\r
-             PSC_ENABLE : In    std_logic;\r
-               RESET : In    std_logic;\r
-             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
-             SPC_ENABLE : In    std_logic;\r
-             SYNC_R_FIFO_FFn : In    std_logic;\r
-             SYNC_S_FIFO_EFn : In    std_logic;\r
-             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             S_FIFO_READn : Out   std_logic );\r
-   end component;\r
-\r
-   component FLAG_BUS\r
-      Port ( FLAG_IN_0 : In    std_logic;\r
-             FLAG_IN_4 : In    std_logic;\r
-                HOLD : In    std_logic;\r
-              KONS_1 : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-               R_EFn : In    std_logic;\r
-               R_FFn : In    std_logic;\r
-               R_HFn : In    std_logic;\r
-               S_EFn : In    std_logic;\r
-               S_FFn : In    std_logic;\r
-               S_HFn : In    std_logic;\r
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
-\r
-   RESERVE <= gnd;\r
-   I23 : SER_PAR_CON\r
-      Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
-                 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
-                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
-                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
-                 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
-   I22 : PAR_SER_CON\r
-      Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
-                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
-                 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
-                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
-                 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
-   I21 : FIFO_IO_CONTROL\r
-      Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
-                 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
-                 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
-                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
-                 R_FIFO_READn=>R_FIFO_READn,\r
-                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
-                 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
-                 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
-                 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
-                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
-   I20 : CONNECTING_FSM\r
-      Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
-                 RESET=>RESET,\r
-                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
-                 SPC_ENABLE=>SPC_ENABLE,\r
-                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
-                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
-                 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
-                 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
-                 S_FIFO_READn=>XXXS_FIFO_READn );\r
-   I19 : FLAG_BUS\r
-      Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
-                 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
-                 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
-                 S_HFn=>S_HFn,\r
-                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity FIFO_CONTROL is
+      Port ( FIFO_RDn : In    std_logic;
+             FLAG_IN_0 : In    std_logic;
+             FLAG_IN_4 : In    std_logic;
+    &nb