powercore
[raggedstone] / heartbeat / source / vga_main.vhd
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95764a11 1---------------------------------------------------------------------\r
2-- vga_main.vhd Demo VGA configuration module.\r
3---------------------------------------------------------------------\r
4-- Author: Barron Barnett\r
5-- Copyright 2004 Digilent, Inc.\r
6---------------------------------------------------------------------\r
7--\r
8-- This project is compatible with Xilinx ISE or Xilinx WebPack tools.\r
9--\r
10-- Inputs: \r
11-- mclk - System Clock\r
12-- Outputs:\r
13-- hs - Horizontal Sync\r
14-- vs - Vertical Sync\r
15-- red - Red Output\r
16-- grn - Green Output\r
17-- blu - Blue Output\r
18--\r
19-- This module creates a three line pattern on a vga display using a\r
20-- a vertical refresh rate of 60Hz. This is done by dividing the\r
21-- system clock in half and using that for the pixel clock. This in\r
22-- turn drives the vertical sync when the horizontal sync has reached\r
23-- its reset point. All data displayed is done by basic value\r
24-- comparisons.\r
25------------------------------------------------------------------------\r
26-- Revision History:\r
27-- 07/01/2004(BarronB): created\r
28------------------------------------------------------------------------\r
29library IEEE;\r
30use IEEE.STD_LOGIC_1164.ALL;\r
31use IEEE.STD_LOGIC_ARITH.ALL;\r
32use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
33\r
34\r
35entity vgaController is\r
36 Port ( mclk : in std_logic;\r
37 hs : out std_logic;\r
38 vs : out std_logic;\r
39 red : out std_logic;\r
40 grn : out std_logic;\r
41 blu : out std_logic);\r
42end vgaController;\r
43\r
44architecture Behavioral of vgaController is\r
45\r
46\r
47 constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line\r
48 constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display\r
49 \r
50 constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch\r
51 constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch\r
52 constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch\r
53 constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch\r
54 \r
55 signal hc, vc : std_logic_vector(9 downto 0); --These are the Horizontal and Vertical counters\r
56 signal clkdiv : std_logic; --Clock divider\r
57 signal vidon : std_logic; --Tells whether or not its ok to display data\r
58 signal vsenable : std_logic; --Enable for the Vertical counter\r
59\r
60begin\r
61 --This cuts the 50Mhz clock in half\r
62 process(mclk)\r
63 begin\r
64 if(mclk = '1' and mclk'EVENT) then\r
65 clkdiv <= not clkdiv;\r
66 end if;\r
67 end process; \r
68\r
69 --Runs the horizontal counter\r
70 process(clkdiv)\r
71 begin\r
72 if(clkdiv = '1' and clkdiv'EVENT) then\r
73 if hc = hpixels then --If the counter has reached the end of pixel count\r
74 hc <= "0000000000"; --reset the counter\r
75 vsenable <= '1'; --Enable the vertical counter to increment\r
76 else\r
77 hc <= hc + 1; --Increment the horizontal counter\r
78 vsenable <= '0'; --Leave the vsenable off\r
79 end if;\r
80 end if;\r
81 end process;\r
82\r
83 hs <= '1' when hc(9 downto 7) = "000" else '0'; --Horizontal Sync Pulse\r
84\r
85 process(clkdiv)\r
86 begin\r
87 if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled\r
88 if vc = vlines then --Reset when the number of lines is reached\r
89 vc <= "0000000000";\r
90 else vc <= vc + 1; --Increment the vertical counter\r
91 end if;\r
92 end if;\r
93 end process;\r
94\r
95 vs <= '1' when vc(9 downto 1) = "000000000" else '0'; --Vertical Sync Pulse\r
96\r
97 red <= '1' when (hc = "1010101100" and vidon ='1') else '0'; --Red pixel on at a specific horizontal count\r
98 grn <= '1' when (hc = "0100000100" and vidon ='1') else '0'; --Green pixel on at a specific horizontal count\r
99 blu <= '1' when (vc = "0100100001" and vidon ='1') else '0'; --Blue pixel on at a specific vertical count\r
100\r
101 vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches\r
102\r
103end Behavioral;\r
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