move address register

[raggedstone] / dhwk / source / pci / address_register.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: ADDR_REG.VHD\r
\r
library IEEE;\r
use IEEE.std_logic_1164.all;\r
\r
entity ADDRESS_REGISTER is\r
	port (\r
                PCI_CLOCK	:in	std_logic;\r
                PCI_RSTn	:in	std_logic;\r
                LOAD_ADDR_REG	:in	std_logic;\r
                AD_REG		:in	std_logic_vector (31 downto 0);\r
                ADDR_REG	:out	std_logic_vector (31 downto 0)\r
        );\r
end entity ADDRESS_REGISTER;\r
\r
architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is\r
	signal	REG_ADDR	:std_logic_vector (31 downto 0); \r
begin \r
\r
	process (PCI_CLOCK, PCI_RSTn) \r
	begin\r
		if	PCI_RSTn = '0'	then\r
                        REG_ADDR	<= X"00000000";\r
\r
		elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
			if LOAD_ADDR_REG = '1' then\r
                                REG_ADDR	<=	AD_REG;\r
			else\r
                                REG_ADDR	<=	REG_ADDR;\r
			end if;\r
		end if;\r
	end process;\r
\r
	ADDR_REG	<=	REG_ADDR;\r
\r
end architecture ADDR_REGI_DESIGN;\r