[raggedstone] / dhwk / source / pci / pci_top.vhd

-- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity PCI_TOP is
        Port ( FLAG : In std_logic_vector (7 downto 0);
               INT_REG : In std_logic_vector (7 downto 0);
               PCI_CBEn : In std_logic_vector (3 downto 0);
               PCI_CLOCK : In std_logic;
               PCI_FRAMEn : In std_logic;
               PCI_IDSEL : In std_logic;
               PCI_IRDYn : In std_logic;
               PCI_RSTn : In std_logic;
               R_FIFO_Q : In std_logic_vector (7 downto 0);
               REVISON_ID : In std_logic_vector (7 downto 0);
               VENDOR_ID : In std_logic_vector (15 downto 0);
               PCI_AD : InOut std_logic_vector (31 downto 0);
               PCI_PAR : InOut std_logic;
               AD_REG : Out std_logic_vector (31 downto 0);
               DEVSELn : Out std_logic;
               FIFO_RDn : Out std_logic;
               PCI_DEVSELn : Out std_logic;
               PCI_PERRn : Out std_logic;
               PCI_SERRn : Out std_logic;
               PCI_STOPn : Out std_logic;
               PCI_TRDYn : Out std_logic;
               READ_SEL : Out std_logic_vector (1 downto 0);
               READ_XX1_0 : Out std_logic;
               READ_XX3_2 : Out std_logic;
               READ_XX5_4 : Out std_logic;
               READ_XX7_6 : Out std_logic;
               REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
               REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
               REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
               TRDYn : Out std_logic;
               WRITE_XX1_0 : Out std_logic;
               WRITE_XX3_2 : Out std_logic;
               WRITE_XX5_4 : Out std_logic;
               WRITE_XX7_6 : Out std_logic );
end PCI_TOP;

architecture SCHEMATIC of PCI_TOP is

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';

        signal IRDY_REGn : std_logic;
        signal IO_WR_COM : std_logic;
        signal TRDYn_DUMMY : std_logic;
        signal READ_XX3_2_DUMMY : std_logic;
        signal USER_DATA_OUT : std_logic_vector (31 downto 0);
        signal CBE_REGn : std_logic_vector (3 downto 0);
        signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
        signal ADDR_REG : std_logic_vector (31 downto 0);
        signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);

        component USER_IO
                Port ( AD_REG : In std_logic_vector (31 downto 0);
                       ADDR_REG : In std_logic_vector (31 downto 0);
                       CBE_REGn : In std_logic_vector (3 downto 0);
                       FLAG : In std_logic_vector (7 downto 0);
                       INT_REG : In std_logic_vector (7 downto 0);
                       IO_WR_COM : In std_logic;
                       IRDY_REGn : In std_logic;
                       PCI_CLK : In std_logic;
                       R_FIFO_Q : In std_logic_vector (7 downto 0);
                       READ_SEL : In std_logic_vector (1 downto 0);
                       TRDYn : In std_logic;
                       READ_XX1_0 : Out std_logic;
                       READ_XX3_2 : Out std_logic;
                       READ_XX5_4 : Out std_logic;
                       READ_XX7_6 : Out std_logic;
                       REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
                       REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
                       REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
                       USER_DATA_OUT : Out std_logic_vector (31 downto 0);
                       WRITE_XX1_0 : Out std_logic;
                       WRITE_XX3_2 : Out std_logic;
                       WRITE_XX5_4 : Out std_logic;
                       WRITE_XX7_6 : Out std_logic );
        end component;

        component PCI_INTERFACE
                Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
                       PCI_CLOCK : In std_logic;
                       PCI_FRAMEn : In std_logic;
                       PCI_IDSEL : In std_logic;
                       PCI_IRDYn : In std_logic;
                       PCI_RSTn : In std_logic;
                       READ_FIFO : In std_logic;
                       REVISON_ID : In std_logic_vector (7 downto 0);
                       USER_DATA_OUT : In std_logic_vector (31 downto 0);
                       VENDOR_ID : In std_logic_vector (15 downto 0);
                       PCI_AD : InOut std_logic_vector (31 downto 0);
                       PCI_PAR : InOut std_logic;
                       AD_REG : Out std_logic_vector (31 downto 0);
                       ADDR_REG : Out std_logic_vector (31 downto 0);
                       CBE_REGn : Out std_logic_vector (3 downto 0);
                       DEVSELn : Out std_logic;
                       FIFO_RDn : Out std_logic;
                       IO_WR_COM : Out std_logic;
                       IRDY_REGn : Out std_logic;
                       PCI_DEVSELn : Out std_logic;
                       PCI_PERRn : Out std_logic;
                       PCI_SERRn : Out std_logic;
                       PCI_STOPn : Out std_logic;
                       PCI_TRDYn : Out std_logic;
                       READ_SEL : Out std_logic_vector (1 downto 0);
                       TRDYn : Out std_logic );
        end component;

begin

        READ_SEL <= READ_SEL_DUMMY;
        AD_REG <= AD_REG_DUMMY;
        READ_XX3_2 <= READ_XX3_2_DUMMY;
        TRDYn <= TRDYn_DUMMY;

        I19 : USER_IO
        Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
        ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
        FLAG(7 downto 0)=>FLAG(7 downto 0),
        INT_REG(7 downto 0)=>INT_REG(7 downto 0),
        IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
        PCI_CLK=>PCI_CLOCK,
        R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
        READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
        TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
        READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
        READ_XX7_6=>READ_XX7_6,
        REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
        REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
        REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
        USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
        WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
        WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
        I10 : PCI_INTERFACE
        Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
                   PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
                   PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
                   PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
                   REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
                   USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
                   VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
                   PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
                   PCI_PAR=>PCI_PAR,
                   AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                   ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                   CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
                   DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
                   IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
                   PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
                   PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
                   PCI_TRDYn=>PCI_TRDYn,
                   READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
                   TRDYn=>TRDYn_DUMMY );

end SCHEMATIC;
Commit	Line	Data
696ded12	1	-- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007
696ded12	2
696ded12	3	LIBRARY ieee;
	4
	5	USE ieee.std_logic_1164.ALL;
	6	USE ieee.numeric_std.ALL;
	7
	8
	9	entity PCI_TOP is
2612d712	10	Port ( FLAG : In std_logic_vector (7 downto 0);
	11	INT_REG : In std_logic_vector (7 downto 0);
	12	PCI_CBEn : In std_logic_vector (3 downto 0);
	13	PCI_CLOCK : In std_logic;
	14	PCI_FRAMEn : In std_logic;
	15	PCI_IDSEL : In std_logic;
	16	PCI_IRDYn : In std_logic;
	17	PCI_RSTn : In std_logic;
	18	R_FIFO_Q : In std_logic_vector (7 downto 0);
	19	REVISON_ID : In std_logic_vector (7 downto 0);
	20	VENDOR_ID : In std_logic_vector (15 downto 0);
	21	PCI_AD : InOut std_logic_vector (31 downto 0);
	22	PCI_PAR : InOut std_logic;
	23	AD_REG : Out std_logic_vector (31 downto 0);
	24	DEVSELn : Out std_logic;
	25	FIFO_RDn : Out std_logic;
	26	PCI_DEVSELn : Out std_logic;
	27	PCI_PERRn : Out std_logic;
	28	PCI_SERRn : Out std_logic;
	29	PCI_STOPn : Out std_logic;
	30	PCI_TRDYn : Out std_logic;
	31	READ_SEL : Out std_logic_vector (1 downto 0);
	32	READ_XX1_0 : Out std_logic;
	33	READ_XX3_2 : Out std_logic;
	34	READ_XX5_4 : Out std_logic;
	35	READ_XX7_6 : Out std_logic;
	36	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
	37	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
	38	REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
	39	TRDYn : Out std_logic;
	40	WRITE_XX1_0 : Out std_logic;
	41	WRITE_XX3_2 : Out std_logic;
	42	WRITE_XX5_4 : Out std_logic;
	43	WRITE_XX7_6 : Out std_logic );
696ded12	44	end PCI_TOP;
	45
	46	architecture SCHEMATIC of PCI_TOP is
	47
2612d712	48	SIGNAL gnd : std_logic := '0';
2612d712	49	SIGNAL vcc : std_logic := '1';
696ded12	50
2612d712	51	signal IRDY_REGn : std_logic;
	52	signal IO_WR_COM : std_logic;
	53	signal TRDYn_DUMMY : std_logic;
	54	signal READ_XX3_2_DUMMY : std_logic;
	55	signal USER_DATA_OUT : std_logic_vector (31 downto 0);
	56	signal CBE_REGn : std_logic_vector (3 downto 0);
	57	signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
	58	signal ADDR_REG : std_logic_vector (31 downto 0);
	59	signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
696ded12	60
2612d712	61	component USER_IO
	62	Port ( AD_REG : In std_logic_vector (31 downto 0);
	63	ADDR_REG : In std_logic_vector (31 downto 0);
	64	CBE_REGn : In std_logic_vector (3 downto 0);
	65	FLAG : In std_logic_vector (7 downto 0);
	66	INT_REG : In std_logic_vector (7 downto 0);
	67	IO_WR_COM : In std_logic;
	68	IRDY_REGn : In std_logic;
	69	PCI_CLK : In std_logic;
	70	R_FIFO_Q : In std_logic_vector (7 downto 0);
	71	READ_SEL : In std_logic_vector (1 downto 0);
	72	TRDYn : In std_logic;
	73	READ_XX1_0 : Out std_logic;
	74	READ_XX3_2 : Out std_logic;
	75	READ_XX5_4 : Out std_logic;
	76	READ_XX7_6 : Out std_logic;
	77	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
	78	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
	79	REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
	80	USER_DATA_OUT : Out std_logic_vector (31 downto 0);
	81	WRITE_XX1_0 : Out std_logic;
	82	WRITE_XX3_2 : Out std_logic;
	83	WRITE_XX5_4 : Out std_logic;
	84	WRITE_XX7_6 : Out std_logic );
	85	end component;
696ded12	86
2612d712	87	component PCI_INTERFACE
	88	Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
	89	PCI_CLOCK : In std_logic;
	90	PCI_FRAMEn : In std_logic;
	91	PCI_IDSEL : In std_logic;
	92	PCI_IRDYn : In std_logic;
	93	PCI_RSTn : In std_logic;
	94	READ_FIFO : In std_logic;
	95	REVISON_ID : In std_logic_vector (7 downto 0);
	96	USER_DATA_OUT : In std_logic_vector (31 downto 0);
	97	VENDOR_ID : In std_logic_vector (15 downto 0);
	98	PCI_AD : InOut std_logic_vector (31 downto 0);
	99	PCI_PAR : InOut std_logic;
	100	AD_REG : Out std_logic_vector (31 downto 0);
	101	ADDR_REG : Out std_logic_vector (31 downto 0);
	102	CBE_REGn : Out std_logic_vector (3 downto 0);
	103	DEVSELn : Out std_logic;
	104	FIFO_RDn : Out std_logic;
	105	IO_WR_COM : Out std_logic;
	106	IRDY_REGn : Out std_logic;
	107	PCI_DEVSELn : Out std_logic;
	108	PCI_PERRn : Out std_logic;
	109	PCI_SERRn : Out std_logic;
	110	PCI_STOPn : Out std_logic;
	111	PCI_TRDYn : Out std_logic;
	112	READ_SEL : Out std_logic_vector (1 downto 0);
	113	TRDYn : Out std_logic );
	114	end component;
696ded12	115
	116	begin
	117
2612d712	118	READ_SEL <= READ_SEL_DUMMY;
	119	AD_REG <= AD_REG_DUMMY;
	120	READ_XX3_2 <= READ_XX3_2_DUMMY;
	121	TRDYn <= TRDYn_DUMMY;
696ded12	122
2612d712	123	I19 : USER_IO
	124	Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
	125	ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
	126	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
	127	FLAG(7 downto 0)=>FLAG(7 downto 0),
	128	INT_REG(7 downto 0)=>INT_REG(7 downto 0),
	129	IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
	130	PCI_CLK=>PCI_CLOCK,
	131	R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
	132	READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
	133	TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
	134	READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
	135	READ_XX7_6=>READ_XX7_6,
	136	REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
	137	REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
	138	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
	139	USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
	140	WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
	141	WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
	142	I10 : PCI_INTERFACE
	143	Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
	144	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
	145	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
	146	PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
	147	REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
	148	USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
	149	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
	150	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
	151	PCI_PAR=>PCI_PAR,
	152	AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
	153	ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
	154	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
	155	DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
	156	IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
	157	PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
	158	PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
	159	PCI_TRDYn=>PCI_TRDYn,
	160	READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
	161	TRDYn=>TRDYn_DUMMY );
696ded12	162
696ded12	163	end SCHEMATIC;