`define WBW_ADDR_LENGTH 4
`define WBR_ADDR_LENGTH 4
-`define PCIW_ADDR_LENGTH 3
-`define PCIR_ADDR_LENGTH 3
+`define PCIW_ADDR_LENGTH 4
+`define PCIR_ADDR_LENGTH 4
`define FPGA
`define XILINX
-`define WB_RAM_DONT_SHARE
-`define PCI_RAM_DONT_SHARE
+//`define WB_RAM_DONT_SHARE
+//`define PCI_RAM_DONT_SHARE
`ifdef FPGA
`ifdef XILINX
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
-`define PCI_NUM_OF_DEC_ADDR_LINES 24
+`define PCI_NUM_OF_DEC_ADDR_LINES 19
// no. of PCI Target IMAGES
// - PCI provides 6 base address registers for image implementation.
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
-`define WB_IMAGE2
+//`define WB_IMAGE2
//`define WB_IMAGE3
//`define WB_IMAGE4
//`define WB_IMAGE5
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
-`define HEADER_VENDOR_ID 16'h1895
-`define HEADER_DEVICE_ID 16'h0001
+`define HEADER_VENDOR_ID 16'h4242
+`define HEADER_DEVICE_ID 16'h2323
`define HEADER_REVISION_ID 8'h01
-`define HEADER_SUBSYS_VENDOR_ID 16'h1895
-`define HEADER_SUBSYS_ID 16'h0001
+`define HEADER_SUBSYS_VENDOR_ID 16'h4242
+`define HEADER_SUBSYS_ID 16'h2323
`define HEADER_MAX_LAT 8'h1a
`define HEADER_MIN_GNT 8'h08
projects / raggedstone / commitdiff