perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd
[raggedstone] / dhwk / source / pci / comm_fsm.vhd
CommitLineData
696ded12 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: COMM_FSM.VHD
5
6library ieee;
6f242c75 7use ieee.std_logic_1164.all;
696ded12 8
9entity COMM_FSM is
6f242c75 10 port
11 (
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 IO_READ :in std_logic;
15 IO_WRITE :in std_logic;
16 CONF_READ :in std_logic;
17 CONF_WRITE :in std_logic;
18 DEVSELn :in std_logic;
19
20 IO_RD_COM : out std_logic;--> MUX_SEL(0)
21 CF_RD_COM :out std_logic;
22 IO_WR_COM :out std_logic;
23 CF_WR_COM :out std_logic
24 );
25end entity COMM_FSM;
696ded12 26
27architecture COMM_FSM_DESIGN of COMM_FSM is
28
29
6f242c75 30 --**********************************************************
31 --*** COMMAND FSM CODIERUNG ***
32 --**********************************************************
33 --
34 --
35 -- |--------- IO_RD_COM
36 -- ||-------- CF_RD_COM
37 -- |||------- IO_WR_COM
38 -- ||||------ CF_WR_COM
39 -- ||||
40 constant ST_IDLE_COMM :std_logic_vector (3 downto 0) := "0000";--
41 constant ST_CONF_WRITE :std_logic_vector (3 downto 0) := "0001";--
42 constant ST_IO_WRITE :std_logic_vector (3 downto 0) := "0010";--
43 constant ST_CONF_READ :std_logic_vector (3 downto 0) := "0100";--
44 constant ST_IO_READ :std_logic_vector (3 downto 0) := "1000";--
696ded12 45
6f242c75 46 signal COMM_STATE :std_logic_vector (3 downto 0);
696ded12 47
6f242c75 48 --************************************************************
49 --*** FSM SPEICHER-AUTOMAT ***
50 --************************************************************
696ded12 51
6f242c75 52 attribute syn_state_machine : boolean;
53 attribute syn_state_machine of COMM_STATE : signal is false;
696ded12 54
55begin
56
6f242c75 57 --**********************************************************
58 --*** COMMAND FSM ***
59 --**********************************************************
60
61 process (PCI_CLOCK, PCI_RSTn)
62 begin
63 if PCI_RSTn = '0' then
64 COMM_STATE <= "0000";
65
e687cadb 66 elsif (rising_edge(PCI_CLOCK)) then
6f242c75 67 case COMM_STATE is
68 when ST_IDLE_COMM =>
69 if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
70
71 elsif CONF_READ = '1' then
72 COMM_STATE <= ST_CONF_READ;
73
74 elsif IO_WRITE = '1' then
75 COMM_STATE <= ST_IO_WRITE;
76
77 elsif CONF_WRITE = '1' then
78 COMM_STATE <= ST_CONF_WRITE;
79
80 else
81 COMM_STATE <= ST_IDLE_COMM;
82 end if;
83
84 when ST_IO_READ =>
85 if DEVSELn = '1' then
86 COMM_STATE <= ST_IDLE_COMM;
87 end if;
88
89 when ST_CONF_READ =>
90 if DEVSELn = '1' then
91 COMM_STATE <= ST_IDLE_COMM;
92 end if;
93
94 when ST_IO_WRITE =>
95 if DEVSELn = '1' then
96 COMM_STATE <= ST_IDLE_COMM;
97 end if;
98
99 when ST_CONF_WRITE =>
100 if DEVSELn = '1' then
101 COMM_STATE <= ST_IDLE_COMM;
102 end if;
103
104 when others =>
105 COMM_STATE <= ST_IDLE_COMM;
106
107 end case; -- COMM_STATE
108 end if; -- CLOCK
109end process; -- PROCESS
110
111 IO_RD_COM <= COMM_STATE(3);
112 CF_RD_COM <= COMM_STATE(2);
113 IO_WR_COM <= COMM_STATE(1);
114 CF_WR_COM <= COMM_STATE(0);
115
116end architecture COMM_FSM_DESIGN;
Impressum, Datenschutz