perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd
authorsithglan <sithglan>
Sun, 11 Mar 2007 13:23:11 +0000 (13:23 +0000)
committersithglan <sithglan>
Sun, 11 Mar 2007 13:23:11 +0000 (13:23 +0000)
15 files changed:
dhwk/source/par_ser_con.vhd
dhwk/source/pci/address_register.vhd
dhwk/source/pci/comm_dec.vhd
dhwk/source/pci/comm_fsm.vhd
dhwk/source/pci/config_04h.vhd
dhwk/source/pci/config_10h.vhd
dhwk/source/pci/config_3Ch.vhd
dhwk/source/pci/connecting_fsm.vhd
dhwk/source/pci/cont_fsm.vhd
dhwk/source/pci/fifo_io_control.vhd
dhwk/source/pci/flag_bus.vhd
dhwk/source/pci/interrupt.vhd
dhwk/source/pci/io_reg.vhd
dhwk/source/pci/parity_out.vhd
dhwk/source/ser_par_con.vhd

index 2f183d9c07f66355cc3012abd54b03179e63e94c..92a01c0b023ac93f6f094d208002ba551a2cf9ce 100644 (file)
@@ -1,4 +1,4 @@
--- $Id: par_ser_con.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
+-- $Id: par_ser_con.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -43,7 +43,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
@@ -115,7 +115,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         SYNC <= SPC_RDY_IN;
                 end if;
         end process;
index 99360c5f65d419438adaa9dd7297a781f60ae2a7..56c480eb2087d0c92e211c94a3a399764eec05b2 100644 (file)
@@ -25,7 +25,7 @@ begin
                if      PCI_RSTn = '0'  then
                         REG_ADDR       <= X"00000000";
 
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+               elsif (rising_edge(PCI_CLOCK)) then
                        if LOAD_ADDR_REG = '1' then
                                 REG_ADDR       <=      AD_REG;
                        else
index c28d22224dd8631f0a2c758f15e2e4176e9302b3..2cd7bebb7ef2b13f25ab019c7f8efe19a2f3c0f0 100644 (file)
@@ -89,7 +89,7 @@ begin
         process (PCI_CLOCK, PCI_RSTn)
         begin
                 if PCI_RSTn = '0' then FRAME_REG_REGn <= '1';
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
 
                 FRAME_REG_REGn <= FRAME_REGn;
 
index 82ecece801a6b2b304c7c24e07cec11d8428d31c..773512898f5e45cbf676db2a9334de7f1c25e1a3 100644 (file)
@@ -63,7 +63,7 @@ begin
         if PCI_RSTn = '0' then
                 COMM_STATE <= "0000";
 
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
                 case COMM_STATE is
                 when ST_IDLE_COMM =>
                         if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
index 70d0c9f26b3005c74994698c6e6a7345b2de2baf..5e26083da73ec9eb0ec0da4e3d9a2e363579d3c5 100644 (file)
@@ -52,7 +52,7 @@ begin
                 CONF_STATUS(30) <= '0';
                 CONF_STATUS(31) <= '0';
 
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
                 if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
                         CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
                         CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
@@ -92,7 +92,7 @@ begin
                 CONF_COMMAND(15 downto 8) <= (others =>'0');
                 CONF_COMMAND( 6 downto 0) <= (others =>'0');
 
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
 
                 if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
                         CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
index ad55b17a5df52eab67a306793540f67235a8c9d5..4660c6ff4953f50c8883e9fa3131a9faf3da229c 100644 (file)
@@ -38,7 +38,7 @@ begin
         if PCI_RSTn = '0' then
                 CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
 
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
 
                 if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
                         CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
index 2c79f4fcdf0d86732b614c67029c5360fedf130a..00d93ebfac4511336939c5b45eb30164e3da563c 100644 (file)
@@ -47,7 +47,7 @@ begin
                 if PCI_RSTn = '0' then
                         CONF_INT_LINE <= (others => '0');
 
-                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                elsif (rising_edge(PCI_CLOCK)) then
                         if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
                                 CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
                         end if;
index eb444eaf02654dfb666421c4117aaba6502ff18a..421132f3f6cb3647523a066f85558ef65eac93bc 100644 (file)
@@ -66,7 +66,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if SIG_LOAD = '1' then
                                 REG <= S_FIFO_Q_OUT;
 
@@ -82,7 +82,7 @@ begin
 
 process (PCI_CLOCK)
 begin
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        if (rising_edge(PCI_CLOCK)) then
 
                 if RESET = '1' then
                         STATES <= S0;
index 4600784de3573369f390fa805c8b82ccd4f803f9..7ebd4c0ca2bf72c6aeefe8ee11c87c2da6898403 100644 (file)
@@ -88,7 +88,7 @@ begin
         begin
                 if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE;
 
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
 
                 case CONTROL_STATE is
                 when ST_IDLE =>
index 03f914ac38a39f6d6ad6cdd6ab50b59d1f2d2e94..be853950ed3bf3940ade573b0aae29fae09dffcb 100644 (file)
@@ -1,4 +1,4 @@
--- $Id: fifo_io_control.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -35,7 +35,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 S_FIFO_WRITEn <= '1';
                                 SIG_S_ERROR <= '0';
index 2b3c654646d0d5f693e64ce345f841d35829178f..5e6ba0211dce8b0c2593ce0b40e0497947cd7a4c 100644 (file)
@@ -46,7 +46,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         FF1_S_EFn <= not S_EFn;
                         FF1_S_HFn <= not S_HFn;
                         FF1_S_FFn <= not S_FFn;
@@ -59,7 +59,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if HOLD = '0' then
                                 FF2_S_EFn <= FF1_S_EFn;
                                 FF2_S_HFn <= FF1_S_HFn;
index a3709b6ba88f030a164af0e1e4fd55aea450e191..5d3b4734d46ee8ae8b2c5051579371c97ffae3eb 100644 (file)
@@ -75,7 +75,7 @@ begin
                         FF_A <= "00000000";
                         FF_B <= "00000000";
 
-                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                elsif (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 SET <= "00000000";
                                 FF_A <= "00000000";
@@ -105,7 +105,7 @@ begin
                 if (PCI_RSTn = '0') then
                         REG <= "00000000";
 
-                elsif(PCI_CLOCK'event and PCI_CLOCK = '1') then
+                elsif(rising_edge(PCI_CLOCK)) then
                         if(RESET = '1') then
                                 REG <= "00000000";
 
@@ -132,7 +132,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if(PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if(rising_edge(PCI_CLOCK)) then
                         SIG_PROPAGATE_INT_SECOND <= not SIG_PROPAGATE_INT;
                 end if;
         end process;
index ecbd9d67dbdbae908d0cc8cad8947b66e2361736..3003c367563076b62053cf9deef580566625a2dd 100644 (file)
@@ -49,7 +49,7 @@ begin
                         REG_IDSEL <= '0';
                         REG_PAR <= '0';
 
-                elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                elsif (rising_edge(PCI_CLOCK)) then
                         REG_AD <= IO_DATA;
                         REG_CBEn <= PCI_CBEn;
                         REG_FRAMEn <= PCI_FRAMEn;
index c8ecfa7859a450832b4e4dda1e251e632e300713..e169ba3df172b7634c749b09216b477f1bf25ead 100644 (file)
@@ -44,7 +44,7 @@ begin
                 PERR_FF <= '0';
                 SERR_FF <= '0';
 
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+        elsif (rising_edge(PCI_CLOCK)) then
                 SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
                 PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
         end if;
index d68124d3920f59c513161bdb8fa376acda83594e..6c45577a523436f3c3dbef4e37d4a19a1b83786a 100644 (file)
@@ -1,4 +1,4 @@
--- $Id: ser_par_con.vhd,v 1.3 2007-03-11 12:24:35 sithglan Exp $
+-- $Id: ser_par_con.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -46,7 +46,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
@@ -129,7 +129,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
                 end if;
         end process;
@@ -137,7 +137,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 STARTBIT <= "0000";
                         else
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