[raggedstone] / dhwk / source / pci / pci_interface.vhd

-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity PCI_INTERFACE is
        Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
               PCI_CLOCK : In std_logic;
               PCI_FRAMEn : In std_logic;
               PCI_IDSEL : In std_logic;
               PCI_IRDYn : In std_logic;
               PCI_RSTn : In std_logic;
               READ_FIFO : In std_logic;
               REVISON_ID : In std_logic_vector (7 downto 0);
               USER_DATA_OUT : In std_logic_vector (31 downto 0);
               VENDOR_ID : In std_logic_vector (15 downto 0);
               PCI_AD : InOut std_logic_vector (31 downto 0);
               PCI_PAR : InOut std_logic;
               AD_REG : Out std_logic_vector (31 downto 0);
               ADDR_REG : Out std_logic_vector (31 downto 0);
               CBE_REGn : Out std_logic_vector (3 downto 0);
               DEVSELn : Out std_logic;
               FIFO_RDn : Out std_logic;
               IO_WR_COM : Out std_logic;
               IRDY_REGn : Out std_logic;
               PCI_DEVSELn : Out std_logic;
               PCI_PERRn : Out std_logic;
               PCI_SERRn : Out std_logic;
               PCI_STOPn : Out std_logic;
               PCI_TRDYn : Out std_logic;
               READ_SEL : Out std_logic_vector (1 downto 0);
               TRDYn : Out std_logic );
end PCI_INTERFACE;

architecture SCHEMATIC of PCI_INTERFACE is

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';

        signal IRDY_REGn_DUMMY : std_logic;
        signal PAR_REG : std_logic;
        signal PERR : std_logic;
        signal SERR : std_logic;
        signal CF_RD_COM : std_logic;
        signal CF_WR_COM : std_logic;
        signal LAR : std_logic;
        signal MY_ADDR : std_logic;
        signal SERR_CHECK : std_logic;
        signal IDSEL_REG : std_logic;
        signal FRAME_REGn : std_logic;
        signal PERR_CHECK : std_logic;
        signal OE_PCI_PAR : std_logic;
        signal OE_PCI_PERR : std_logic;
        signal TRDYn_DUMMY : std_logic;
        signal CONF_DATA_10H : std_logic_vector (31 downto 0);
        signal CONF_DATA_04H : std_logic_vector (31 downto 0);
        signal CONF_DATA : std_logic_vector (31 downto 0);
        signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
        signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
        signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
        signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);

        component STEUERUNG
                Port ( AD_REG : In std_logic_vector (31 downto 0);
                       CBE_REGn : In std_logic_vector (3 downto 0);
                       FRAME_REGn : In std_logic;
                       IDSEL_REG : In std_logic;
                       IO_SPACE : In std_logic;
                       MY_ADDR : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       READ_FIFO : In std_logic;
                       CF_RD_COM : Out std_logic;
                       CF_WR_COM : Out std_logic;
                       DEVSELn : Out std_logic;
                       FIFO_RDn : Out std_logic;
                       IO_RD_COM : Out std_logic;
                       IO_WR_COM : Out std_logic;
                       LAR : Out std_logic;
                       OE_PCI_PAR : Out std_logic;
                       OE_PCI_PERR : Out std_logic;
                       PCI_DEVSELn : Out std_logic;
                       PCI_STOPn : Out std_logic;
                       PCI_TRDYn : Out std_logic;
                       PERR_CHECK : Out std_logic;
                       READ : Out std_logic;
                       SERR_CHECK : Out std_logic;
                       TRDYn : Out std_logic );
        end component;

        component PARITY
                Port ( OE_PCI_PAR : In std_logic;
                       OE_PCI_PERR : In std_logic;
                       PA_ER_RE : In std_logic;
                       PAR_IN : In std_logic_vector (35 downto 0);
                       PAR_REG : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       PERR_CHECK : In std_logic;
                       SERR_CHECK : In std_logic;
                       SERR_ENA : In std_logic;
                       PCI_PAR : InOut std_logic;
                       PCI_PERRn : Out std_logic;
                       PCI_SERRn : Out std_logic;
                       PERR : Out std_logic;
                       SERR : Out std_logic );
        end component;

        component VERGLEICH
                Port ( IN_A : In std_logic_vector (31 downto 0);
                       IN_B : In std_logic_vector (31 downto 0);
                       GLEICH_OUT : Out std_logic );
        end component;

        component IO_MUX_REG
                Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
                       LOAD_ADDR_REG : In std_logic;
                       PCI_CBEn : In std_logic_vector (3 downto 0);
                       PCI_CLOCK : In std_logic;
                       PCI_FRAMEn : In std_logic;
                       PCI_IDSEL : In std_logic;
                       PCI_IRDYn : In std_logic;
                       PCI_PAR : In std_logic;
                       PCI_RSTn : In std_logic;
                       READ_SEL : In std_logic_vector (1 downto 0);
                       USER_DATA : In std_logic_vector (31 downto 0);
                       PCI_AD : InOut std_logic_vector (31 downto 0);
                       AD_REG : Out std_logic_vector (31 downto 0);
                       ADDR_REG : Out std_logic_vector (31 downto 0);
                       CBE_REGn : Out std_logic_vector (3 downto 0);
                       FRAME_REGn : Out std_logic;
                       IDSEL_REG : Out std_logic;
                       IRDY_REGn : Out std_logic;
                       PAR_REG : Out std_logic );
        end component;

        component CONFIG_SPACE_HEADER
                Port ( AD_REG : In std_logic_vector (31 downto 0);
                       ADDR_REG : In std_logic_vector (31 downto 0);
                       CBE_REGn : In std_logic_vector (3 downto 0);
                       CF_RD_COM : In std_logic;
                       CF_WR_COM : In std_logic;
                       IRDY_REGn : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       PERR : In std_logic;
                       REVISION_ID : In std_logic_vector (7 downto 0);
                       SERR : In std_logic;
                       TRDYn : In std_logic;
                       VENDOR_ID : In std_logic_vector (15 downto 0);
                       CONF_DATA : Out std_logic_vector (31 downto 0);
                       CONF_DATA_04H : Out std_logic_vector (31 downto 0);
                       CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
        end component;

begin

        ADDR_REG <= ADDR_REG_DUMMY;
        AD_REG <= AD_REG_DUMMY;
        CBE_REGn <= CBE_REGn_DUMMY;
        READ_SEL <= READ_SEL_DUMMY;
        TRDYn <= TRDYn_DUMMY;
        IRDY_REGn <= IRDY_REGn_DUMMY;

        I7 : STEUERUNG
        Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
        CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
        FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
        IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,
        PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
        READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,
        CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,
        FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),
        IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,
        OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
        PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
        PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),
        SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );
        I5 : PARITY
        Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
                   PA_ER_RE=>CONF_DATA_04H(6),
                   PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                   PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),
                   PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
                   PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,
                   SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
                   PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
                   PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
        I4 : VERGLEICH
        Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
        IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
        GLEICH_OUT=>MY_ADDR );
        I2 : IO_MUX_REG
        Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
                   LOAD_ADDR_REG=>LAR,
                   PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
                   PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
                   PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
                   PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
                   READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
                   USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),
                   PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
                   AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
                   ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
                   CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
                   FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
                   IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );
        I1 : CONFIG_SPACE_HEADER
        Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
        ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
        CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
        CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,
        IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,
        PCI_RSTn=>PCI_RSTn, PERR=>PERR,
        REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),
        SERR=>SERR, TRDYn=>TRDYn_DUMMY,
        VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
        CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );

end SCHEMATIC;
Commit	Line	Data
696ded12	1	-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007
696ded12	2
696ded12	3	LIBRARY ieee;
	4
	5	USE ieee.std_logic_1164.ALL;
	6	USE ieee.numeric_std.ALL;
	7
	8
	9	entity PCI_INTERFACE is
2612d712	10	Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
	11	PCI_CLOCK : In std_logic;
	12	PCI_FRAMEn : In std_logic;
	13	PCI_IDSEL : In std_logic;
	14	PCI_IRDYn : In std_logic;
	15	PCI_RSTn : In std_logic;
	16	READ_FIFO : In std_logic;
	17	REVISON_ID : In std_logic_vector (7 downto 0);
	18	USER_DATA_OUT : In std_logic_vector (31 downto 0);
	19	VENDOR_ID : In std_logic_vector (15 downto 0);
	20	PCI_AD : InOut std_logic_vector (31 downto 0);
	21	PCI_PAR : InOut std_logic;
	22	AD_REG : Out std_logic_vector (31 downto 0);
	23	ADDR_REG : Out std_logic_vector (31 downto 0);
	24	CBE_REGn : Out std_logic_vector (3 downto 0);
	25	DEVSELn : Out std_logic;
	26	FIFO_RDn : Out std_logic;
	27	IO_WR_COM : Out std_logic;
	28	IRDY_REGn : Out std_logic;
	29	PCI_DEVSELn : Out std_logic;
	30	PCI_PERRn : Out std_logic;
	31	PCI_SERRn : Out std_logic;
	32	PCI_STOPn : Out std_logic;
	33	PCI_TRDYn : Out std_logic;
	34	READ_SEL : Out std_logic_vector (1 downto 0);
	35	TRDYn : Out std_logic );
696ded12	36	end PCI_INTERFACE;
	37
	38	architecture SCHEMATIC of PCI_INTERFACE is
	39
2612d712	40	SIGNAL gnd : std_logic := '0';
	41	SIGNAL vcc : std_logic := '1';
	42
	43	signal IRDY_REGn_DUMMY : std_logic;
	44	signal PAR_REG : std_logic;
	45	signal PERR : std_logic;
	46	signal SERR : std_logic;
	47	signal CF_RD_COM : std_logic;
	48	signal CF_WR_COM : std_logic;
	49	signal LAR : std_logic;
	50	signal MY_ADDR : std_logic;
	51	signal SERR_CHECK : std_logic;
	52	signal IDSEL_REG : std_logic;
	53	signal FRAME_REGn : std_logic;
	54	signal PERR_CHECK : std_logic;
	55	signal OE_PCI_PAR : std_logic;
	56	signal OE_PCI_PERR : std_logic;
	57	signal TRDYn_DUMMY : std_logic;
	58	signal CONF_DATA_10H : std_logic_vector (31 downto 0);
	59	signal CONF_DATA_04H : std_logic_vector (31 downto 0);
	60	signal CONF_DATA : std_logic_vector (31 downto 0);
	61	signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
	62	signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
	63	signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
	64	signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);
	65
	66	component STEUERUNG
	67	Port ( AD_REG : In std_logic_vector (31 downto 0);
	68	CBE_REGn : In std_logic_vector (3 downto 0);
	69	FRAME_REGn : In std_logic;
	70	IDSEL_REG : In std_logic;
	71	IO_SPACE : In std_logic;
	72	MY_ADDR : In std_logic;
	73	PCI_CLOCK : In std_logic;
	74	PCI_RSTn : In std_logic;
	75	READ_FIFO : In std_logic;
	76	CF_RD_COM : Out std_logic;
	77	CF_WR_COM : Out std_logic;
	78	DEVSELn : Out std_logic;
	79	FIFO_RDn : Out std_logic;
	80	IO_RD_COM : Out std_logic;
	81	IO_WR_COM : Out std_logic;
	82	LAR : Out std_logic;
	83	OE_PCI_PAR : Out std_logic;
	84	OE_PCI_PERR : Out std_logic;
	85	PCI_DEVSELn : Out std_logic;
	86	PCI_STOPn : Out std_logic;
	87	PCI_TRDYn : Out std_logic;
	88	PERR_CHECK : Out std_logic;
	89	READ : Out std_logic;
	90	SERR_CHECK : Out std_logic;
	91	TRDYn : Out std_logic );
	92	end component;
	93
	94	component PARITY
	95	Port ( OE_PCI_PAR : In std_logic;
	96	OE_PCI_PERR : In std_logic;
	97	PA_ER_RE : In std_logic;
	98	PAR_IN : In std_logic_vector (35 downto 0);
	99	PAR_REG : In std_logic;
	100	PCI_CLOCK : In std_logic;
	101	PCI_RSTn : In std_logic;
	102	PERR_CHECK : In std_logic;
	103	SERR_CHECK : In std_logic;
104	SERR_ENA : In std_logic;
105	PCI_PAR : InOut std_logic;
106	PCI_PERRn : Out std_logic;
107	PCI_SERRn : Out std_logic;
108	PERR : Out std_logic;
109	SERR : Out std_logic );
110	end component;
111
11b038c2	112	component VERGLEICH
	113	Port ( IN_A : In std_logic_vector (31 downto 0);
	114	IN_B : In std_logic_vector (31 downto 0);
	115	GLEICH_OUT : Out std_logic );
	116	end component;
	117
2612d712	118	component IO_MUX_REG
	119	Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);
	120	LOAD_ADDR_REG : In std_logic;
	121	PCI_CBEn : In std_logic_vector (3 downto 0);
	122	PCI_CLOCK : In std_logic;
	123	PCI_FRAMEn : In std_logic;
	124	PCI_IDSEL : In std_logic;
	125	PCI_IRDYn : In std_logic;
	126	PCI_PAR : In std_logic;
	127	PCI_RSTn : In std_logic;
	128	READ_SEL : In std_logic_vector (1 downto 0);
	129	USER_DATA : In std_logic_vector (31 downto 0);
	130	PCI_AD : InOut std_logic_vector (31 downto 0);
	131	AD_REG : Out std_logic_vector (31 downto 0);
	132	ADDR_REG : Out std_logic_vector (31 downto 0);
	133	CBE_REGn : Out std_logic_vector (3 downto 0);
	134	FRAME_REGn : Out std_logic;
	135	IDSEL_REG : Out std_logic;
	136	IRDY_REGn : Out std_logic;
	137	PAR_REG : Out std_logic );
	138	end component;
	139
	140	component CONFIG_SPACE_HEADER
	141	Port ( AD_REG : In std_logic_vector (31 downto 0);
	142	ADDR_REG : In std_logic_vector (31 downto 0);
	143	CBE_REGn : In std_logic_vector (3 downto 0);
	144	CF_RD_COM : In std_logic;
	145	CF_WR_COM : In std_logic;
	146	IRDY_REGn : In std_logic;
	147	PCI_CLOCK : In std_logic;
	148	PCI_RSTn : In std_logic;
	149	PERR : In std_logic;
	150	REVISION_ID : In std_logic_vector (7 downto 0);
	151	SERR : In std_logic;
	152	TRDYn : In std_logic;
	153	VENDOR_ID : In std_logic_vector (15 downto 0);
	154	CONF_DATA : Out std_logic_vector (31 downto 0);
	155	CONF_DATA_04H : Out std_logic_vector (31 downto 0);
	156	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
	157	end component;
696ded12	158
	159	begin
	160
2612d712	161	ADDR_REG <= ADDR_REG_DUMMY;
	162	AD_REG <= AD_REG_DUMMY;
	163	CBE_REGn <= CBE_REGn_DUMMY;
	164	READ_SEL <= READ_SEL_DUMMY;
	165	TRDYn <= TRDYn_DUMMY;
	166	IRDY_REGn <= IRDY_REGn_DUMMY;
	167
	168	I7 : STEUERUNG
	169	Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
	170	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
	171	FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
	172	IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,
	173	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
	174	READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,
	175	CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,
	176	FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),
	177	IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,
	178	OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
	179	PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
	180	PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),
	181	SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );
	182	I5 : PARITY
	183	Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
	184	PA_ER_RE=>CONF_DATA_04H(6),
	185	PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
	186	PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),
	187	PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
	188	PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,
	189	SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
	190	PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
	191	PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
11b038c2	192	I4 : VERGLEICH
	193	Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
	194	IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
	195	GLEICH_OUT=>MY_ADDR );
2612d712	196	I2 : IO_MUX_REG
	197	Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
	198	LOAD_ADDR_REG=>LAR,
	199	PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
	200	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
	201	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
	202	PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
	203	READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
	204	USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),
	205	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
	206	AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
	207	ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
	208	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
	209	FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
	210	IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );
	211	I1 : CONFIG_SPACE_HEADER
	212	Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
	213	ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
	214	CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
	215	CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,
	216	IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,
	217	PCI_RSTn=>PCI_RSTn, PERR=>PERR,
	218	REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),
	219	SERR=>SERR, TRDYn=>TRDYn_DUMMY,
	220	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
	221	CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
	222	CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
	223	CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
696ded12	224
696ded12	225	end SCHEMATIC;